Body Biasing for Analog Design:

Practical Experiences in 22 nm FD-SOI

Sunil Satish Rao, Benjamin Prautsch, Ashish Shrivastava, Torsten Reich
Fraunhofer IIS/EAS, Institute for Integrated Circuits, Division Engineering of Adaptive Systems, Dresden, Germany
{sunil.rao, benjamin.prautsch, ashish.shrivastava, torsten.reich}@eas.iis.fraunhofer.de

Abstract—This paper presents the practical application of (e.g. PMOS in nwell) for regular threshold voltage (RVT) or
body biasing control of ultra-deep submicron FD-SOI the flipped well option (e.g. PMOS in pwell) for low threshold
technologies for analog and mixed-signal designs. The body voltage (LVT). The conventional option allows reverse body
biasing control is dedicated for dynamic control of the trade- biasing (RBB) to negative voltages while the flipped well
off between speed vs. power consumption for advanced digital option allows forward body biasing (FBB). Thereby, the back
circuits. However, in this work we focus on trading-off and gate voltage magnitude can exceeded the supply magnitude to
improvement of analog circuit performances. Three different further increase the effect of varying the threshold voltage.
circuits were explored and designed: an all CMOS bandgap Also, both options allow the back gate voltage to slightly
reference, a 500 MSps current-steering DAC, and a 12-bit move towards the respective negative direction (e.g. -300 mV
sigma-delta modulator. All designs were verified and realized in FBB). RVT and LVT devices trade-off power consumption
in Globalfoundries 22 nm FD-SOI technology. and maximum frequency. RVT devices reduce leakage while
Keywords—Ultra deep submicron; 22 nm FD-SOI; Data LVT devices show more leakage and allow higher operation
converters; Reference generators; Body biasing, Analog Design frequencies due to more driving current [2, 4]. So, it is an
essential and early design decision which transistor type is to
I. INTRODUCTION be used.
Integrated circuits, especially digital cores, are facing a Most often, the back gate is used in order to adapt digital
huge rise of complexity for next-generation applications with circuit behavior regarding a power-speed trade-off as e.g. in
high computing-power and/or high speed requirements. State- SRAM cells [5]. Since advanced digital circuits may benefit
of-the-art bulk CMOS technologies were extremely shrunk from several voltage levels of the back gate, dynamic body
over last decades to handle these challenges, which are biasing has already been presented [6].
expanded by the requirement of reduced power consumption. Apart from the application in digital circuits, a variety of
Techniques such as dynamic frequency scaling or dynamic new design trade-offs and topologies is achievable in analog
voltage scaling are well established to trade off processing circuit design. Rather than only targeting power versus speed,
speed versus power consumption in digital embedded systems the capability of changing the transistor’s threshold voltage
[1]. Managing the still growing power budget with shrinking during function opens an entire new field of opportunities. A
the feature size of semiconductor technologies simultaneously, variety of advantages, such as low-voltage, low-power, near-
give major design challenges in future complex digital systems. ideal body factor, good subthreshold behavior and current
State-of-the-art bulk CMOS technologies can be replaced by
drive are reported [7]. In [8] it was shown that low-power
FD-SOI (fully depleted silicon-on-insulator) technologies,
applications can benefit from the FD-SOI process trade-offs.
which offer a new feature for power and speed scaling. This
feature, named body biasing, will be introduced in Section II. Particular design benefits using increased intrinsic gain have
Body biasing is known to be beneficial to trade off digital been utilized for OTA design [9].
circuit performance (e.g. dynamic trade off speed versus power Utilizing the back gate behavior, one can also imagine that
consumption). Within this work the benefit of body biasing to process variation is compensated or that new feedback
analog circuits was investigated and demonstrated in different strategies will result in completely new topologies.
analog/mixed-signal circuit designs, described in Section III. A
conclusion on different beneficial effects on the presented III. APPLICATION TO ANALOG/MIXED-SIGNAL DESIGN
circuits is summarized in Section IV. In order to evaluate and utilize the capability of FD-SOI,
three analog IPs were developed showing the capability of
II. BODY BIASING FUNDAMENTALS valuable live trade-off selection which is not possible with
The major advantage of modern FD-SOI processes is the bulk processes. All IPs, namely all CMOS bandgap reference,
introduction of a fourth terminal – the back gate – to the MOS current-steering DAC, and low-power sigma-delta (ΣΔ)
transistor. This terminal allows controlling the threshold modulator have been analyzed and designed regarding the
voltage by about 85 mV/V when changing the back gate achievable back-gate-controlled trade-offs and improvements.
voltage [2, 3]. Here, it must be considered which well option The IPs were simulated on either schematic level including
is to be used. Possible are either the conventional well option
major parasitics or on layout level (if computationally
possible) and will be fabricated in near future.
A. All CMOS Bandgap Reference
Voltage reference generators are used extensively in many
applications in digital and analog circuits. Since the demand
for battery operated device is increasing, the craving for low-
power and low voltage circuits is increasing as well. This
results in a demand for low voltage reference generators which
should be stable over supply voltage, process and temperature
variations. Bandgap voltage references generate a stable
voltage over the corners and process variations [10]. The
traditional bandgap voltage reference generates an output
voltage equal to the silicon energy gap voltage of around
1.25 V [11]. The principle behind the bandgap reference is
given in [10]. The voltage across the base-emitter junction
of bipolar junction transistor (BJT) has a negative temperature
coefficient called as complimentary to the absolute Fig. 1 Proposed all CMOS bandgap voltage reference with body biasing.
temperature (CTAT). On the other hand, the (thermal
voltage) has a positive temperature coefficient and it is called
proportional to absolute temperature (PTAT) which is
multiplied by K times (adjusted by sizing). So, the voltage
reference is the summation of voltage and and
has low temperature dependency due to cancelation of
temperature variation by the effect of PTAT and CTAT [10].
Within this paper we focus on a 22 nm FD-SOI technology
[4], where the supply voltage is limited to 800 mV. So, the
conventional bandgap reference cannot be used. The solution
is to design an all CMOS voltage reference circuit as proposed
in [12]. In this work a modified version of the work presented
in [12] is designed and the use of body biasing is illustrated.
The voltage reference is shown in Fig. 1. Transistors M1-
M4 realize a differential amplifier to control the same voltage
on the two branches of the voltage reference. MD1-MD3 are
called dynamic-threshold MOS (DTMOS) [13] which act as
diodes. The threshold voltage varies dynamically when the
gate and substrate of MOS transistors are connected to form a
DTMOS. Hence, only CMOS technology is used to produce
the behavior of the diode by the MOS, avoiding additional
fabrication steps [13].
The advantage of body biasing is taken by all the
Fig. 2 Temperature coefficient of the bandgap versus body bias voltage for
transistors except MD1-MD3 (DTMOSs). It is seen that the
nominal, best and worst corner.
performance of the voltage reference increases in terms of
temperature coefficient (TC) when the PMOS body bias is
A Monte-Carlo sample with and without body biasing is
changed from VDD to VSS and the NMOS body bias is
shown in
changed from VSS to VDD. When both body biases change
Fig. 3 and Fig. 4, respectively. The power supply rejection
simultaneously, TC reduces by half. The reason is found in the
ratio is 55 dB. The reference generates an output voltage of
improved linearity of both PTAT and CTAT.
530 mV with a power consumption of 2.3 µW. The layout of
By simulation studies we see the following results. The
the voltage reference is shown in Fig. 5.
post-layout simulation is made for a temperature variation of
165 °C (-40 °C to 125 °C) and a supply variation of ±10 %. B. 500 MSps Current-Steering DAC
The results with and without body biasing are produced here. For modern high speed telecommunication systems the
As mentioned before, the extensive use of body biasing from required hardware should provide high speed at low power
VDD to VSS and vice-versa is performed to show the effect and high resolution digital-to-analog and analog-to-digital
on the performance of the voltage reference. Fig. 2 shows the converters [14]. In this paper, we have implemented a 10-bit
overall variation of TC (across corners) when body biasing is segmented current steering DAC. The basic block diagram is
applied to both NMOS and PMOS simultaneously. The TC shown in Fig. 6 [15].
decreases by half when Vbiasn equals VDD and Vbiasp equals The digital input word is segmented into a binary
VSS. segmented array (4 bits in our design) to switch binary
 Fig. 6 Block diagram of the segmented current steering DAC;
adapted from [15].

Fig. 3 Monte-Carlo simulation of the bandgap without body biasing.

Fig. 7 Schematic block of the implemented DAC; adapted from [15].

weighted current sources and thermometer

segmented array (6 bits in our design) to switch the unary
current sources. realizes the least significant bits and
realizes the most significant bits. A delay buffer is used to
equalize the delay to the latched switches caused by different
paths of unary and binary code. Latches are added to minimize
the timing error to the differential switches. The output current
is connected to resistors to get the respective output voltage.
The schematic diagram of the implemented CS-DAC is shown
in Fig. 7. It adapts the structure presented in [15] while body
biasing is utilized additionally.
Fig. 4 Monte-Carlo simulation of the bandgap applying body biasing.
The binary LSB sinks 1 µA current and the unary sinks
16 µA of current by each single branch. It has 4 binary current
sources (1 µA, 2 µA, 4 µA, and 8 µA) and MSB current
sources of 16 µA each. The differential output voltage ranges
from +500 mV to -500 mV with an output common mode of
550 mV. The power consumption of the whole DAC is
1.3 mW with an INL of ±0.7 LSB and a DNL of ±0.5 LSB.
The body biasing technique is applied to the NMOS wide
swing current mirrors.
The body biasing voltage was varied from reverse biasing
(Vbiasn ≈ -300 mV) to full biasing (Vbiasn = VDD). It is seen
that the reverse body biasing (RBB) is more beneficial than
the forward body biasing (FBB) with respect to both low
power and high accuracy (while increasing the settling time).
Body biasing on current mirrors shows that as we go less than
0 V to -300 mV (RBB), the power consumption reduces by
half and the settling time increase for the same load. The
Fig. 5 Bandgap reference layout in 22 nm FD-SOI technology. power consumption for a body biasing voltage of 0 V (VSS) is
436 µW with a settling time of 684 ps and for -300 mV it is
278 µW with a settling time of 730 ps. Fig. 8 shows the graph
 Fig. 8. Power consumption and settling time variation with respect to the
body bias voltage.

for overall variation of body biasing from -300 mV to

800 mV. The negative voltage (-300 mV) can be generated by Fig. 9 Layout of the 10-bit DAC Layout in 22 nm FD-SOI technology.
using a voltage generator such as presented in [6] which
produces a voltage from -2 V to +2 V. There are different (d) high speed [19, 20]. Large application fields are covered
possibilities to utilize body biasing here: 1) static body biasing by successive-approximation (SAR), sigma-delta (ΣΔ), and
can be applied to adjust the operating point, 2) quasi-static pipelined ADCs [19]. Accordingly, sigma-delta ADCs have
body biasing can be applied (e.g. to compensate process large coverage across applications, providing high resolutions.
variations) via a programmable body bias voltage, and But due to the op-amp utilized, it consumes comparatively
3) adaptive body biasing can be applied to configure the high power. However, it would be significant and
circuit performance online (e.g. trading off sampling rate vs. advantageous to design ultra-low power sigma-delta
power consumption, Fig. 8). The simulations are made on modulators with high resolution. In order to achieve this aim,
schematic level due to the computational complexity. in this work a sigma-delta modulator was designed, taking
However, low-level blocks were analyzed using the extracted advantage of the 22 nm FD-SOI technology.
view. The total layout size of the 10-bit DAC is 250 µm X By combining oversampling and loop filter in the
400 µm, and the layout is shown in Fig. 9. modulator to shape noise and then by using a digital filter to
Layout and schematic of the entire current mirror matrix remove noise, it is possible to attain high dynamic range,
were created fully automatic within about two minutes by aid which is the basic principle of sigma-delta ADC. Designing in
of a procedural generator – a so-called Intelligent IP (IIP) [16].
We have already used Intelligent IP generators extensively in
developing a 12-bit DAC in 28 nm FD-SOI [16, 17], with
silicon available, where we optimized yield by decreasing the
current sources’ variation utilizing static body biasing. This
highly technology-independent IIP was now also successfully
utilized for the Globalfoundries 22 nm FD-SOI target
technology.
C. Low-Power Sigma-Delta Modulator
With more battery-powered devices, the demand of low
power design of analog-to-digital-converters (ADCs) is rising
up, in order to minimize the power requirements and to
increase battery life. In this direction several researches and
designs have been accomplished [18]. ADCs can be classified
into four broad sections of application (a) data acquisition, (b) Fig. 10 Schematic diagram of the core operational amplifier with body
biasing applied; adapted from [22].
precision industrial measurement (c) voice band and audio and
small feature size technology makes the ΣΔ modulator power
efficient but on the other hand it poses problems to achieve
mandatory requirement (high gain op-amp) for the ΣΔ
modulator. Power reduction in the modulator can also be
acquired by choosing proper components as for example
switched capacitor common mode feedback (SC-CMFB) for
operational amplifier (op-amp) and small value capacitors. In
addition, gain bandwidth and slew rate of the op-amp are also
considerable factors in power consumption of the modulator.
In this work, a third order discrete time sigma-delta
modulator was designed in 22 nm FD-SOI technology. The
contained operational amplifier is shown in Fig. 10. The
modulator is implemented with switched capacitors and the
operational amplifier acts as loop filter which further
suppresses quantization noise in the signal bandwidth after
oversampling. Further reduction of noise is achieved by
cascading loop filters as it was done in [21]. The operational
amplifier used in this modulator was designed using forward Fig. 11 Plot of both ENOB (worst case) and power consumption (worst
case) of the sigma-delta modulator over body bias voltage.
body biasing [22] (see Fig. 10). This reduces the threshold
voltage, which in turn makes it possible to stack more
transistors between rail to rail (cascading) despite of low
voltage supply. Thus, the operational amplifier can actually
achieve its requirements and specification, although using well-
known topologies from “larger” technologies. In the presented
sigma-delta modulator, a folded cascade operational amplifier
has been used.
The performance of this modulator is analyzed for ENOB
(effective number of bits) and power consumption. Basically,
ENOB is dependent on several parameters as for example
oversampling ratio, gain of the amplifier etc. Since in this work
the operational amplifier uses the body biasing technique,
different body biasing voltage levels were analyzed for their
effect on the overall performance of the converter (see Fig. 11).
Different body bias voltage levels for PMOS and NMOS Fig. 12 Layout of the sigma-delta modulator in 22 nm FD-SOI technology.
transistors of the op-amp result in trading-off ENOB and power
consumption. In our particular analysis, it can be seen from shifts the output voltage swings of the op-amp which results
Fig. 11 that without body biasing (same as standard bulk: again in distortion in the modulator and subsequently gives
VbiasP = 0.8 V, VbiasN = 0.0 V), the ENOB is comparably low. very low minimal ENOB.
When the bulk of both PMOS and NMOS is at 400 mV, the Fig. 11 shows that the power consumption increases with
ENOB is maximized. After this point the ENOB reduces again. forward body biasing. It is evident from both curves that at
This can be understood as that without body biasing the VbiasP = VbiasN = 400mV the modulator has the optimal
threshold voltage is higher and the current in the op-amp is performance regarding ENOB. For this point Table 1 shows the
less, which is insufficient for charging the capacitors in the modulator verification results. The layout of the modulator is
modulator. Therefore, noise and distortion is created causing depicted in Fig. 12.
degraded SNR and ENOB. Increasing the body bias voltage
IV. BODY BIASING EFFECT ON ANALOG DESIGN
TABLE 1 VERIFICATION RESULTS OF THE SIGMA-DELTA MODULATOR The FD-SOI back gate is a new terminal the analog
Input signal Bandwidth 20 kHz designer is able to use during the design phase. The tunable
threshold voltage is a feature which results in various impacts.
Clock frequency 8 MHz One advantage can be an increased level of circuit
Oversampling ratio 200 robustness compared to classical bulk designs. The bandgap
reference circuit presented in this paper showed better
Supply Voltage 800 mV temperature stability due to optimized back gate voltage.
ENOB 11.5 bit Another advantage can be an increase of the accuracy
(across Monte-Carlo) of current mirror sources due to stronger
Peak SNDR 70.95 dB inversion. This effect was seen in the presented CS-DAC.
SFDR 71.9 dB Furthermore, trading-off sampling rate versus power
consumption via body biasing could be demonstrated here.
Power Consumption 72.8 µW Further, the super-low threshold voltage capability of FD-
SOI MOS transistors with forward biased back gate, allows
using “older” circuit topologies which show several levels of
transistor stacking. Since those devices show an extremely low
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