Unit-3

Central Processing Unit:

General Register Organization, Stack Organization, Addressing Modes, Reduced
instruction set computer, Complex instruction set computer, instruction formats
Content
´ Introduction

´ General Register Organization

´ Stack Organization

´ Instruction formats

´ Addressing Modes

´ Data Transfer and Manipulation

´ Program Control and Program Interrupt

´ Reduced Instruction Set Computer

´ Complex Instruction Set Computer

 Register
Set

Introduction Control
Arithmetic
logic Unit
(ALU)
´ Part of computer that perform bulk of data processing operations – CPU

´ Register Set – Store intermediate data used during execution of instruction

´ ALU – Performs the required microoperations for executing the instructions
´ Control – Supervises the transfer of information among registers and instructs the
ALU as to which operation to perform

User who programs the computer in machine or assembly language must be aware
of the register set, the memory structure, the type of data supported by the
instructions and the function that each instruction performs

How registers communicate with ALU through buses and operation of memory stacks
Types of instruction formats, the addressing modes used to retrieve data from memory
and typical instructions commonly incorporated in computers
Major Components of CPU

´ Storage Components
´ Registers
´ Flags
´ Execution (Processing) Components
´ Arithmetic Logic Unit(ALU)
´ Arithmetic calculations, Logical computations, Shifts/Rotates
´ Transfer Components
´ Bus
´ Control Components
´ Control Unit
Register

´ In Basic Computer, there is only one general purpose register –

Accumulator (AC)
´ In modern CPUs, there are many general purpose registers

´ It is advantageous to have many registers

´ Transfer between registers within the processor are relatively fast
´ Going “off the processor” to access memory is much slower

´ Important:
´ How many registers will be the best ?
General Register Organization
Input
Clock

R1
R2
R3
R4
R5
R6
R7
Load
(7 lines)
SELA { MUX MUX } SELB
3x8
A bus B bus
decoder

SELD
OPR ALU

Output
 Operation of Control Unit
´ The control unit
´ Directs the information flow through ALU by
´ Selecting various Components in the system
3 3 3 5
´ Selecting the Function of ALU SELA SELB SELD OPR

Control Word
´ Example: 𝑹𝟏 ← 𝑹𝟐 + 𝑹𝟑
´ [1] MUX A selector (𝑆𝐸𝐿𝐴): 𝐵𝑈𝑆 𝐴 ← 𝑅2
´ [2] MUX B selector (𝑆𝐸𝐿𝐵): 𝐵𝑈𝑆 𝐵 ← 𝑅3
´ [3] ALU operation selector (OPR): ALU to ADD (A+B)
´ [4] Decoder destination selector (𝑆𝐸𝐿𝐷): 𝑅1 ← 𝑂𝑢𝑡 𝐵𝑢𝑠
Control Word
3 3 3 5

SELA SELB SELD OPR

Encoding of register selection fields

Binary
Code SELA SELB SELD
000 Input Input None
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7

´ SELA, SELB and SELD – Decimal number equivalent to binary number

´ SELA and SELB = 000 – External Input data,
´ SELD = 000, no destination register, but content is available in external
output
ALU Control ´ Subtract Micro-operation
𝑅1 ← 𝑅2 − 𝑅3

´ Encoding of ALU operations Field: SELA SELB SELD OPR

Symbol: R2 R3 R1 SUB
OPR
Select Operation Symbol Control Word: 010 011 001 00101
00000 Transfer A TSFA
00001 Increment A INCA
00010 ADD A + B ADD ´ Examples of Micro-operations
00101 Subtract A - B SUB
00110 Decrement A DECA Symbolic Designation
01000 AND A and B AND Microoperation SELA SELB SELD OPR Control Word
01010 OR A and B OR
01100 XOR A and B XOR R1 ¬ R2 - R3
01110 Complement A COMA R4 ¬ R4 Ú R5
10000 Shift right A SHRA
11000 Shift left A SHLA R6 ¬ R6 + 1
R7 ¬ R1
Output ¬ R2
Output ¬ Input
R4 ¬ shl R4
R5 ¬ 0
ALU Control ´ Subtract Micro-operation
𝑅1 ← 𝑅2 − 𝑅3

´ Encoding of ALU operations Field: SELA SELB SELD OPR

Symbol: R2 R3 R1 SUB
OPR
Select Operation Symbol Control Word: 010 011 001 00101
00000 Transfer A TSFA
00001 Increment A INCA
00010 ADD A + B ADD ´ Examples of Micro-operations
00101 Subtract A - B SUB
00110 Decrement A DECA Symbolic Designation
01000 AND A and B AND Microoperation SELA SELB SELD OPR Control Word
01010 OR A and B OR
01100 XOR A and B XOR R1 ¬ R2 - R3 R2 R3 R1 SUB 010 011 001 00101
01110 Complement A COMA R4 ¬ R4 Ú R5 R4 R5 R4 OR 100 101 100 01010
10000 Shift right A SHRA
11000 Shift left A SHLA R6 ¬ R6 + 1 R6 - R6 INCA 110 000 110 00001
R7 ¬ R1 R1 - R7 TSFA 001 000 111 00000
Output ¬ R2 R2 - None TSFA 010 000 000 00000
Output ¬ Input Input - None TSFA 000 000 000 00000
R4 ¬ shl R4 R4 - R4 SHLA 100 000 100 11000
R5 ¬ 0 R5 R5 R5 XOR 101 101 101 01100
Content
´ Introduction

´ General Register Organization

´ Stack Organization

´ Instruction formats

´ Addressing Modes

´ Data Transfer and Manipulation

´ Program Control and Program Interrupt

´ Reduced Instruction Set Computer

´ Complex Instruction Set Computer

Stack Organization

´ Stack – Last In First Out (LIFO)

´ Stack in digital computers is a memory unit with address register
´ Count only after initial value is loaded into it
´ Register that holds the address for stack – Stack Pointer (SP)
´ Always points to the top of the stack
´ Two operations of stack are the insertion and deletion of items
´ PUSH – Inserting a new item on top
´ POP – Deletion of one item
Operation is simulated by Incrementing and Decrementing the SP register
 Register Stack
´ 64 = 26 (0 – 63) Flags
63

FULL EMPTY

´ FULL = 1, when stack is full

´ 111111 + 1 = 1 000000 Stack pointer
4
´ EMTY = 1, when stack is empty SP C 3
6 bits B 2
´ 000000 – 1 = 111111
A 1
´ Push, Pop operations 0

´ Initially, SP = 0, EMPTY = 1, FULL = 0 DR

´ PUSH ´ POP
𝑆𝑃 ← 𝑆𝑃 + 1 Increment SP 𝐷𝑅 ← 𝑀[𝑆𝑃] Read item from top of stack
𝑀 𝑆𝑃 ← 𝐷𝑅 Write item on top of Stack 𝑆𝑃 ← 𝑆𝑃 − 1 Decrement SP

𝐼𝑓 𝑆𝑃 = 0 𝑡ℎ𝑒𝑛 𝐹𝑈𝐿𝐿 ← 1 Check if stack is full 𝐼𝑓 𝑆𝑃 = 0 𝑡ℎ𝑒𝑛 𝐸𝑀𝑇𝑌 ← 1 Check if stack is empty
𝐸𝑀𝑇𝑌 ← 0 Mark stack not empty 𝐹𝑈𝐿𝐿 ← 0 Mark the stack not full
 Memory Stack Organization
1000

´ Computer Memory partitioned into three segments PC

Program
(instructions)
´ Program (PC) [Fetch to read instructions]
´ Data (AR) [Execution to read operand] Data
AR
(operands)
´ Stack Segments (SP) [Push and Pop items]
3000
SP
stack
´ Initially SP at 4001 and stack grows with decreasing addresses
3997
´ PUSH ´ POP 3998
´ 𝑆𝑃 ← 𝑆𝑃 − 1 3999
´ 𝐷𝑅 ← 𝑀 𝑆𝑃
4000
´ 𝑀 𝑆𝑃 ← 𝐷𝑅 ´ 𝑆𝑃 ← 𝑆𝑃 + 1 4001

´ Most computers do not provide hardware to check stack overflow (full

stack) or underflow (empty stack) ← must be done in software
´ Stack limits can be checked by using two processor register
´ Upper limit (3000) – to be checked after PUSH operation
´ Lower limit (4001) – to be checked after POP operation
Reverse Polish Notation

´ Common mathematical method (Infix notation) of writing arithmetic

expressions imposes difficulties when evaluated by computer
´ Infix Notation – Each operator written between operands

𝐴∗𝐵+𝐶∗𝐷
´ Example
´ 𝐴+𝐵 Infix notation
´ +𝐴𝐵 Prefix or Polish Notation
´ 𝐴𝐵 + Postfix or Reverse Polish Notation (RPN)
Reverse Polish Notation is very suitable for stack manipulation
Reverse Polish Notation …

´ Any arithmetic expression can be expressed in parenthesis-free Polish

notation, including reverse Polish notation

𝐴∗𝐵+𝐶∗𝐷

𝐴𝐵 ∗ 𝐶𝐷 ∗ +
´ First Inner parenthesis followed outer parenthesis
´ Multiplication and division operation before addition and subtraction

𝐴 + 𝐵 ∗ [𝐶 ∗ 𝐷 + 𝐸 + 𝐹]

𝐴𝐵 + 𝐷𝐸 + 𝐶 ∗ 𝐹 +∗
Evaluation of Arithmetic Expressions

´ Employed in electronics calculators and computers

3∗4 + 5∗6
´ In Reverse Polish notation
34 ∗ 56 ∗ +
´ Stack Operations Top of Stack

6
4 5 5 30
3 3 12 12 12 12 42

3 4 * 5 6 * +
Content
´ Introduction

´ General Register Organization

´ Stack Organization

´ Instruction formats

´ Addressing Modes

´ Data Transfer and Manipulation

´ Program Control and Program Interrupt

´ Reduced Instruction Set Computer

´ Complex Instruction Set Computer

Instruction Formats

´ Instruction Fields

´ OP-code field – specifies the operation to be performed

´ Address field – designates memory address(es) or a processor register(s)
´ Mode field – determines how the address field is to be interpreted (to get
effective address or the operand)

´ The number of address fields in the instruction format depends on the

internal organization of CPU
Processor Organization

´ In general, most processors are organized in one of three ways

´ Single register (Accumulator) organization
´ Basic Computer is a good example
´ Accumulator is the only general purpose register
´ General register organization
´ Used by most modern computer processors
´ Any of the registers can be used as the source or destination for computer
operations
´ Stack organization
´ All operations are done using the hardware stack
Processor Organization

Single accumulator organization

´ All operations are performed with an implied accumulator register and
address field
´ Example:

𝐴𝐷𝐷 𝑋

´ 𝐴𝐶 ← 𝐴𝐶 + 𝑀[𝑋]
Processor Organization
General register organization
´ Generally requires three register address field
Example:

𝐴𝐷𝐷 𝑅1, 𝑅2, 𝑅3

´ 𝑅1 ← 𝑅2 + 𝑅3

´ Registers can be reduced to two if destination register same as one of the

source register
Example:

𝐴𝐷𝐷 𝑅1, 𝑅2
´ 𝑅1 ← 𝑅1 + 𝑅2
Processor Organization
General register organization
´ One register and other as memory address
Example:

𝐴𝐷𝐷 𝑅1, 𝑋
´ 𝑅1 ← 𝑅1 + 𝑀[𝑋]

´ Move instruction
Example:

𝑀𝑂𝑉 𝑅1, 𝑅2
´ 𝑅1 ← 𝑅2 or 𝑅2 ← 𝑅1 (depends on particular computer)
Processor Organization
Stack organization
´ Would use PUSH and POP instruction with address field
Example:

𝑃𝑈𝑆𝐻 𝑋
𝑇𝑂𝑆 ← 𝑀[𝑋]

´ ADD instruction doesn’t require address field as it is performed on the

operand on the TOS and Result is stored on TOS
´ Example:

𝐴𝐷𝐷
Three Address Instructions

´ Each address field for processor Register or Memory operand

𝑋 = 𝐴+𝐵 ∗ 𝐶+𝐷

´ 𝐴𝐷𝐷 𝑅1, 𝐴, 𝐵 𝑅1 ← 𝑀 𝐴 + 𝑀[𝐵]

´ 𝐴𝐷𝐷 𝑅2, 𝐶, 𝐷 𝑅2 ← 𝑀 𝐶 + 𝑀 𝐷
´ 𝑀𝑈𝐿 𝑋, 𝑅1, 𝑅2 𝑀 𝑋 ← 𝑅1 ∗ 𝑅2
Two Address Instructions

´ Most common in commercial computers

´ Each address field for processor Register or Memory operand

𝑋 = 𝐴+𝐵 ∗ 𝐶+𝐷

´ 𝑀𝑂𝑉 𝑅1, 𝐴 𝑅1 ← 𝑀 𝐴
´ 𝐴𝐷𝐷 𝑅1, 𝐵 𝑅1 ← 𝑅1 + 𝑀 𝐵
´ 𝑀𝑂𝑉 𝑅2, 𝐶 𝑅2 ← 𝑀 𝐶
´ 𝐴𝐷𝐷 𝑅2, 𝐷 𝑅2 ← 𝑅2 + 𝑀 𝐷
´ 𝑀𝑈𝐿 𝑅1, 𝑅2 𝑅1 ← 𝑅1 ∗ 𝑅2
´ 𝑀𝑂𝑉 𝑋, 𝑅1 𝑀[𝑋] ← 𝑅1
One Address Instructions

´ Used as implied accumulator (AC)

𝑋 = 𝐴+𝐵 ∗ 𝐶+𝐷

´ 𝐿𝑂𝐴𝐷 𝐴 𝐴𝐶 ← 𝑀 𝐴
´ 𝐴𝐷𝐷 𝐵 𝐴𝐶 ← 𝐴𝐶 + 𝑀 𝐵
´ 𝑆𝑇𝑂𝑅𝐸 𝑇 𝑀[𝑇] ← 𝐴𝐶
´ 𝐿𝑂𝐴𝐷 𝐶 𝐴𝐶 ← 𝑀 𝐶
´ 𝐴𝐷𝐷 𝐷 𝐴𝐶 ← 𝐴𝐶 + 𝑀 𝐷
´ 𝑀𝑈𝐿 𝑇 𝐴𝐶 ← 𝐴𝐶 ∗ 𝑀[𝑇]
´ 𝑆𝑇𝑂𝑅𝐸 𝑋 𝑀[𝑋] ← 𝐴𝐶
Zero Address Instructions

´ Stack Organization (PUSH and POP), Reverse Polish Notation

𝑋 = 𝐴+𝐵 ∗ 𝐶+𝐷

´ 𝑃𝑈𝑆𝐻 𝐴 𝑇𝑂𝑆 ← 𝐴
´ 𝑃𝑈𝑆𝐻 𝐵 𝑇𝑂𝑆 ← 𝐵
´ 𝐴𝐷𝐷 𝑇𝑂𝑆 ← (𝐴 + 𝐵)
´ 𝑃𝑈𝑆𝐻 𝐶 𝑇𝑂𝑆 ← 𝐶
´ 𝑃𝑈𝑆𝐻 𝐷 𝑇𝑂𝑆 ← 𝐷
´ 𝐴𝐷𝐷 𝑇𝑂𝑆 ← (𝐶 + 𝐷)
´ 𝑀𝑈𝐿 𝑇𝑂𝑆 ← 𝐶 + 𝐷 ∗ 𝐴 + 𝐵
´ 𝑃𝑂𝑃 𝑋 𝑀[𝑋] ← 𝑇𝑂𝑆
Content
´ Introduction

´ General Register Organization

´ Stack Organization

´ Instruction formats

´ Addressing Modes

´ Data Transfer and Manipulation

´ Program Control and Program Interrupt

´ Reduced Instruction Set Computer

´ Complex Instruction Set Computer

Addressing Mode

´ Specifies a rule for interpreting or modifying the address field of the

instruction (before the operand is actually referenced)
´ Variety of addressing modes
´ to give programming flexibility to the user
´ to use the bits in the address field of the instruction efficiently
1. Implied Mode
´ Address of the operands are specified implicitly in the definition of the instruction
´ No need to specify address in the instruction
´ EA = AC, or EA = Stack[SP]
´ Examples from Basic Computer - CLA, CME, INR
Addressing Mode …
2. Immediate Mode
´ Instead of specifying the address of the operand, operand itself is specified
´ No need to specify address in the instruction
´ However, operand itself needs to be specified
´ Sometimes, require more bits than the address
´ Fast to acquire an operand
3. Register Mode
´ Address specified in the instruction is the register address
´ Designated operand need to be in a register
´ Shorter address than the memory address
´ Saving address field in the instruction
´ Faster to acquire an operand than the memory addressing
´ EA = IR(R) (IR(R): Register field of IR)
Addressing Mode …

4. Register Indirect Mode

´ Instruction specifies a register which contains the memory address of the
operand
´ Saving instruction bits since register address is shorter than the memory address
´ Slower to acquire an operand than both the register addressing or memory
addressing
´ EA = [IR(R)] ([x]: Content of x)
5. Autoincrement or Autodecrement Mode
´ When the address in the register is used to access memory, the value in the
register is incremented or decremented by 1 automatically
Addressing Mode …
6. Direct Address Mode
´ Instruction specifies the memory address which can be used directly to access
the memory
´ Faster than the other memory addressing modes
´ Too many bits are needed to specify the address for a large physical memory
space
7. Indirect Addressing Mode
´ The address field of an instruction specifies the address of a memory location
that contains the address of the operand
´ When the abbreviated address is used large physical memory can be addressed
with a relatively small number of bits
´ Slow to acquire an operand because of an additional memory access
Addressing Mode …
8. Relative Addressing Mode
´ The Address fields of an instruction specifies the part of the address (abbreviated
address) which can be used along with a designated register to calculate the
address of the operand
´ Address field of the instruction is short
´ Large physical memory can be accessed with a small number of address bits

´ Three different Relative Addressing Modes depending on R;

´ PC Relative Addressing Mode (R = PC)
´ EA = PC + IR(address)

´ Indexed Addressing Mode (R = IX, where IX: Index Register)

´ EA = IX + IR(address)

´ Base Register Addressing Mode

´ (R = BAR, where BAR: Base Address Register)

´ EA = BAR + IR(address)
 Example – Addressing Mode Address Memory

200 Load to AC Mode

PC = 200 201
Address = 500
Next instruction
Two Word Instruction R1 = 400
202

What will be the Effective Address as AC content 399 450

XR = 100
400 700

´ Direct Address AC
´ Immediate Operand 500 800

´ Indirect Address
´ Relative Address 600 900

´ Indexed Address
´ Register 702 325

´ Register Indirect
´ Autoincrement 800 300

´ Auto decrement
 Example – Addressing Mode Address Memory

200 Load to AC Mode

PC = 200 201
Address = 500

202 Next instruction

R1 = 400

399 450
XR = 100
400 700

Addressing Effective Content AC

Mode Address of AC 500 800

Direct address 500 /* AC ¬ (500) */ 800

Immediate operand 201 /* AC ¬ 500 */ 500
600 900
Indirect address 800 /* AC ¬ ((500)) */ 300
Relative address 702 /* AC ¬ (PC+500) */ 325
Indexed address 600 /* AC ¬ (RX+500) */ 900
Register - /* AC ¬ R1 */ 400 702 325
Register indirect 400 /* AC ¬ (R1) */ 700
Autoincrement 400 /* AC ¬ (R1)+ */ 700
Autodecrement 399 /* AC ¬ -(R) */ 450
800 300
Content
´ Introduction

´ General Register Organization

´ Stack Organization

´ Instruction formats

´ Addressing Modes

´ Data Transfer and Manipulation

´ Program Control and Program Interrupt

´ Reduced Instruction Set Computer

´ Complex Instruction Set Computer

Data Transfer and Manipulation

´ Most computer instructions can be classified into three categories

´ Data Transfer Instructions

´ Transfer of data from one location to another without changing the binary information
content

´ Data Manipulation Instructions

´ Performs arithmetic, logic and shift operations

´ Program Control Instructions

´ Provides decision making capabilities and change the path taken by the program
when executed
 Data Transfer Instructions
´ Transfer of data from one location to another without changing the binary
information content
´ Memory – Processor registers, Processor registers – Input/Output and
between Processor registers themselves

Name Mnemonic
Load LD
Store ST Data Transfer Instructions with Different Addressing Modes
Move MOV
Exchange XCH Assembly
Input IN Mode Convention Register Transfer
Output OUT Direct address LD ADR AC ¬ M[ADR]
Push PUSH Indirect address LD @ADR AC ¬ M[M[ADR]]
Pop POP Relative address LD $ADR AC ¬ M[PC + ADR]
Immediate operand LD #NBR AC ¬ NBR
Index addressing LD ADR(X) AC ¬ M[ADR + XR]
Register LD R1 AC ¬ R1
Register indirect LD (R1) AC ¬ M[R1]
Autoincrement LD (R1)+ AC ¬ M[R1], R1 ¬ R1 + 1
Autodecrement LD -(R1) R1 ¬ R1 - 1, AC ¬ M[R1]
 Data Manipulation Instructions
´ Performs arithmetic, logic and shift operations
´ Three basic types
´ Arithmetic instructions
´ Logical and bit manipulation instructions
´ Shift instructions

Arithmetic Instructions Logical and Bit Manipulation Shift Instructions

Instructions
Name Mnemonic Name Mnemonic Name Mnemonic
Increment INC Clear CLR
Logical shift right SHR
Decrement DEC Complement COM
Logical shift left SHL
Add ADD AND AND
Subtract SUB Arithmetic shift right SHRA
OR OR
Multiply MUL Arithmetic shift left SHLA
Exclusive-OR XOR
Divide DIV Clear carry CLRC Rotate right ROR
Add with Carry ADDC Rotate left ROL
Set carry SETC
Subtract with Borrow SUBB Complement carry COMC Rotate right thru carry RORC
Negate(2’s Complement) NEG Enable interrupt EI Rotate left thru carry ROLC
Disable interrupt DI
Content
´ Introduction

´ General Register Organization

´ Stack Organization

´ Instruction formats

´ Addressing Modes

´ Data Transfer and Manipulation

´ Program Control and Program Interrupt

´ Reduced Instruction Set Computer

´ Complex Instruction Set Computer

Program Control Instruction
(+1) In-Line Sequencing (Next instruction is fetched from the next adjacent
location in the memory)
PC

Address from other source; Current Instruction, Stack, etc; Branch,

Conditional Branch, Subroutine, etc

Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Call CALL
Return RTN
Compare(by Subtraction- ) CMP
Test(by AND) TST * CMP and TST instructions do not retain their
results of operations ( - and AND, resp.).
They only set or clear certain Flags.
Flag, Processor Status Word

´ In Basic Computer, the processor had several (status) flags – 1 bit value that
indicated various information about the processor’s state – E, FGI, FGO, I,
IEN, R
´ In some processors, flags like these are often combined into a register – the
Processor Status Register (PSR); sometimes called a Processor Status Word
(PSW)
´ Common flags in PSW are
Status Flag Circuit
´ C (Carry): Set to 1 if the carry out of the ALU is 1
A B
´ S (Sign): The MSB bit of the ALU’s output (F7) 8 8
c7
´ Z (Zero): Set to 1 if the ALU’s output is all 0’s
8-bit ALU
c8
´ V (Overflow): Set to 1 if there is an overflow F7 - F0
V Z S C
F7

Check for 8
zero output
F
Conditional Branch Instruction
Mnemonic Branch condition Tested condition
BZ Branch if zero Z=1
BNZ Branch if not zero Z=0
BC Branch if carry C=1
BNC Branch if no carry C=0
BP Branch if plus S=0
BM Branch if minus S=1
BV Branch if overflow V=1
BNV Branch if no overflow V=0

Unsigned compare conditions (A - B)

BHI Branch if higher A>B
BHE Branch if higher or equal A³B
BLO Branch if lower A<B
BLOE Branch if lower or equal A£B
BE Branch if equal A=B
BNE Branch if not equal A¹B

Signed compare conditions (A - B)

BGT Branch if greater than A>B
BGE Branch if greater or equal A³B
BLT Branch if less than A<B
BLE Branch if less or equal A£B
BE Branch if equal A=B
BNE Branch if not equal A¹B
Subroutine Call and Return
´ Subroutine Call
´ Call subroutine
´ Jump to subroutine
´ Branch to subroutine
´ Branch and save return address

´ Two Most Important Operations are Implied;

´ Branch to the beginning of the Subroutine, Same as the Branch or Conditional
Branch
´ Save the Return Address to get the address of the location in the Calling Program
upon exit from the Subroutine
CALL
SP ¬ SP - 1
´ Locations for storing Return Address M[SP] ¬ PC
´ Fixed Location in the subroutine (Memory) PC ¬ EA

´ Fixed Location in memory RTN

PC ¬ M[SP]
´ In a processor Register
SP ¬ SP + 1
´ In memory stack
´ most efficient way
Program Interrupt
Types of Interrupts
´ External interrupts – External Interrupts initiated from the outside of CPU and
Memory
´ I/O Device → Data transfer request or Data transfer complete
´ Timing Device → Timeout
´ Power Failure
´ Operator
´ Internal interrupts (traps) – Internal Interrupts are caused by the currently running
program
´ Register, Stack Overflow
´ Divide by zero
´ OP-code Violation
´ Protection Violation
´ Software Interrupts – Both External and Internal Interrupts are initiated by the
computer HW. Software Interrupts are initiated by the executing an instruction.
´ Supervisor Call
1. Switching from a user mode to the supervisor mode
2. Allows to execute a certain class of operations which are not allowed in the user mode
Interrupt Procedure

Interrupt Procedure and Subroutine Call

´ The interrupt is usually initiated by an internal or an external signal rather than
from the execution of an instruction (except for the software interrupt)
´ The address of the interrupt service program is determined by the hardware
rather than from the address field of an instruction
´ An interrupt procedure usually stores all the information necessary to define the
state of CPU rather than storing only the PC.

´ The state of the CPU is determined from:

´ Content of the PC
´ Content of all processor registers
´ Content of status bits

Many ways of saving the CPU state depending on the CPU architectures
Content
´ Introduction

´ General Register Organization

´ Stack Organization

´ Instruction formats

´ Addressing Modes

´ Data Transfer and Manipulation

´ Program Control and Program Interrupt

´ Reduced Instruction Set Computer

´ Complex Instruction Set Computer

RISC and CISC

´ More than 100 and sometimes even more than 200 instructions
´ Employ a variety of data types and larges number of addressing modes
´ Large Number of Instructions – Complex Instruction Set Computer (CISC)

´ Early computers (1980s) had small and simple instruction sets – Minimize the
hardware used to implement them
´ Fewer instructions – Simple constructions – Execution is much faster
´ Limit the use of memory – Reduced Instruction Set Computer (RISC)
 RISC – Historical Background
IBM System/360, 1964
´ The real beginning of modern computer architecture
´ Distinction between Architecture and Implementation
´ Architecture: The abstract structure of a computer seen by an assembly-language
programmer

Hardware
µ-program
Compiler
High-Level Instruction Hardware
Language Set
Architecture
Hardware

Implementation

´ Continuing growth in semiconductor memory and microprogramming

´ A much richer and complicated instruction sets
´ CISC(Complex Instruction Set Computer)
CISC
Arguments Advanced at that time
´ Richer instruction sets would simplify compilers
´ Richer instruction sets would alleviate the software crisis
´ move as much functions to the hardware as possible
´ Richer instruction sets would improve architecture quality

CISC
´ These computers with many instructions and addressing modes came to be
known as Complex Instruction Set Computers (CISC)
´ One goal for CISC machines was to have a machine language instruction
to match each high-level language statement type
 Complex Instruction Set Computers

´ Another characteristic of CISC computers is that they have instructions that act directly on
memory addresses
For example,
ADD L1, L2, L3
that takes the contents of M[L2] adds it to the contents of M[L3] and stores the result in
location M[L1]
´ An instruction like this takes three memory access cycles to execute
´ makes for a potentially very long instruction execution cycle
´ The problems with CISC computers are
´ The complexity of the design may slow down the processor,
´ The complexity of the design may result in costly errors in the processor design and implementation
´ Many of the instructions and addressing modes are used rarely, if ever
 Summary: Criticism on CISC
High Performance General Purpose Instructions
´ Complex Instruction
´ Format, Length, Addressing Modes
´ Complicated instruction cycle control due to the complex decoding HW and decoding process
´ Multiple memory cycle instructions
´ Operations on memory data
´ Multiple memory accesses/instruction
´ Microprogrammed control is necessity
´ Microprogram control storage takes substantial portion of CPU chip area
´ Semantic Gap is large between machine instruction and microinstruction
´ General purpose instruction set includes all the features required by individually different
applications
´ When any one application is running, all the features required by the other applications are extra
burden to the application
RISC – Reduced Instruction Set Computers

´ In the late ‘70s and early ‘80s there was a reaction to the shortcomings of the CISC style of
processors
´ Reduced Instruction Set Computers (RISC) were proposed as an alternative
´ The underlying idea behind RISC processors is to simplify the instruction set and reduce
instruction execution time
´ RISC processors often feature:
´ Few instructions
´ Few addressing modes
´ Only load and store instructions access memory
´ All other operations are done using on-processor registers
´ Fixed length instructions
´ Single cycle execution of instructions
´ The control unit is hardwired, not microprogrammed
RISC – Reduced Instruction Set Computers

´ Since all but the load and store instructions use only registers for operands, only
a few addressing modes are needed
´ By having all instructions the same length, reading them in is easy and fast
´ The fetch and decode stages are simple
´ The instruction and address formats are designed to be easy to decode
´ Unlike the variable length CISC instructions, the opcode and register fields of
RISC instructions can be decoded simultaneously
´ The control logic of a RISC processor is designed to be simple and fast
´ The control logic is simple because of the small number of instructions and the
simple addressing modes
´ The control logic is hardwired, rather than microprogrammed, because
hardwired control is faster