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DigitalLogic ComputerOrganization L16 SingleCycleProcessorP2 Handout

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Phan Tuấn Khôi
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20 views

DigitalLogic ComputerOrganization L16 SingleCycleProcessorP2 Handout

Uploaded by

Phan Tuấn Khôi
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 35

DIGITAL LOGIC AND

COMPUTER ORGANIZATION
Lecture 16: Single Cycle Microprocessor (P2)
ELEC3010
ACKNOWLEGEMENT

I would like to express my special thanks to Professor Zhiru Zhang


School of Electrical and Computer Engineering, Cornell University
and Prof. Rudy Lauwereins, KU Leuven for sharing their teaching
materials.

2
COVERED IN THIS COURSE
❑ Binary numbers and logic gates
❑ Boolean algebra and combinational logic
❑ Sequential logic and state machines
❑ Binary arithmetic
Digital logic
❑ Memories

❑ Instruction set architecture


❑ Processor organization Computer
❑ Caches and virtual memory
❑ Input/output Organization
❑ Advanced topics
3
LET’S BUILD A MICROPROCESSOR!

4
RF REVIEW

What need to be
changed if the RF
has 32 registers?

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CONTROL UNIT (CU)
❑ Regulates the interaction between data and operations on
data (i.e., datapath)
❑ Series of control words control the datapath to perform a
sequence of operations
❑ The sequence of operations performed by the CU may be
affected by the ALU Condition Codes
▪ Z: Zero
▪ N: Negative
▪ Also V: Overflow and C: Carry out
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DATAPATH + CONTROL UNIT

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SEQUENCE OF OPERATIONS

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SEQUENCE OF OPERATIONS

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SEQUENCE OF OPERATIONS

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SEQUENCE OF OPERATIONS

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CAN YOU DO IT?

What are the values of different fields in the instruction when executing the following instructions:
ADD R2, R3, R7
ADDI R4, R6, 2
LOAD R2, 2(R1)
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UNSIGNED MULTIPLICATION
❑ Form each partial product by multiplying a single digit of
the multiplier by the multiplicand
❑ Add shifted partial products to get result

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ITERATIVE (SHIFT AND ADD) MULTIPLICATION

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ITERATIVE (SHIFT AND ADD) MULTIPLICATION

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CAN YOU DO IT?

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OPERATION SEQUENCE FOR ITERATIVE MULTIPLICATION

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PROGRAMMABLE CONTROL UNIT
❑ Datapath (RF, ALU, RAM, muxes) is flexible
❑ However, FSM-based multiplier control unit is “hardwired”
▪ New operation sequence would require new state machine
❑ Programmable control unit
▪ Control words stored in RAM
▪ State machine replaced by a Program Counter plus branch
operations
▪ Flexible: Can run different sequences of control words
(programs)

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PROGRAM COUNTER (PC)
❑ Special register that points to the location (address) in
RAM of the next control word
❑ Updated every clock cycle
❑ Sequential execution (default behavior)
▪ Control words read from sequential RAM locations
▪ PC increments after each control word read
❑ Branch operations
▪ Special control flow operations
▪ Condition code determines whether to branch or not
▪ If so, next RAM address is PC + branch offset

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PC-BASED CONTROL UNIT

Assumption: each RAM row can store 1 control word


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BRANCH OPERATIONS
❑ Used to jump to a different part of the program
❑ Consists of a condition and an offset
❑ Condition
▪ Checks to see whether the result of the last instruction met a
specified criteria, such as
• Zero (Z = 1), Negative (N = 1)
❑ Offset
▪ How far ahead, or back, to jump within the program if the
condition is met

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BRANCH OPERATIONS

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BRANCH OPERATIONS

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CAN YOU DO IT?

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PROGRAMMABLE MULTIPLICATION

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PROVIDING EVEN MORE FLEXIBILITY
❑ Replace control words with
instructions
▪ More intuitive and not specific to
particular hardware
▪ Shorter than control words
▪ Instruction decoder (hardwired
logic) creates the control words
from the instruction

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OUR INSTRUCTION FORMATS

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R-TYPE INSTRUCTIONS

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I-TYPE: ALU WITH IMMEDIATE

What is Min/Max of IMM?

How many Opcodes?

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I-TYPE: LOAD AND STORE

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MEMORY OPERATIONS
❑ The smallest addressable quantity in a modern memory
system is a byte (8 bits)
▪ A memory address points to a byte

❑ LB (Load Byte): reads the byte at this address

❑ LW (Load Word): reads a word this address, which in our


case is 2 bytes

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I-TYPE: BRANCH

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ITERATIVE MULTIPLICATION REVISITED

Assumption: One
instruction is stored in 2
rows (i.e., 2 bytes) of
the instruction memory

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PROGRAMMABLE SINGLE-CYCLE PROCESSOR

❑ Instruction RAM holds the program to be run


▪ Here, each instruction is 16 bits (2 bytes)
❑ Decoder derives control word from the instruction
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BEFORE NEXT CLASS

• Textbook: 7.5.1-7.5.2
• Next time:
Pipelined Microprocessor

35

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