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DigitalLogic ComputerOrganization L8 FSM Handout

The document discusses sequential logic and finite state machines. It covers Moore and Mealy state machines, including their design procedures and implementations. Examples of pattern detection and pushbutton lock state machines are presented.

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Phan Tuấn Khôi
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10 views

DigitalLogic ComputerOrganization L8 FSM Handout

The document discusses sequential logic and finite state machines. It covers Moore and Mealy state machines, including their design procedures and implementations. Examples of pattern detection and pushbutton lock state machines are presented.

Uploaded by

Phan Tuấn Khôi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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DIGITAL LOGIC AND

COMPUTER ORGANIZATION
Lecture 8: Sequential Logic
Finite State Machines (2)
ELEC3010
ACKNOWLEGEMENT

I would like to express my special thanks to Professor Zhiru Zhang


School of Electrical and Computer Engineering, Cornell University
and Prof. Rudy Lauwereins, KU Leuven for sharing their teaching
materials.

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COVERED IN THIS COURSE
❑ Binary numbers and logic gates
❑ Boolean algebra and combinational logic
❑ Sequential logic and state machines
❑ Binary arithmetic
Digital logic
❑ Memories

❑ Instruction set architecture


❑ Processor organization Computer
❑ Caches and virtual memory
❑ Input/output Organization
❑ Advanced topics
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CAN YOU DO IT?
MOORE OR MEALY?

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CAN YOU DO IT?
MOORE OR MEALY?

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FSM DESIGN PROCEDURE
Last lecture

(1) Understand the problem statement and determine inputs


and outputs
(2) Identify states and create a state diagram
(3) Determine the number of required FFs
(4) Implement combinational logic for outputs and next state
(5) Simulate the circuit to test its operation

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FSM DESIGN PROCEDURE

(1) Understand the problem statement and determine inputs


and outputs
(2) Identify states and create a state diagram This lecture

(3) Determine the number of required FFs


(4) Implement combinational logic for outputs and next state
(5) Simulate the circuit to test its operation

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EXAMPLE FSM: PATTERN DETECTOR
❑ Monitors the input, and outputs a 1 whenever a specified
input pattern is detected
❑ Example: Output a 1 whenever 111 is detected on the
input over 3 consecutive clock cycles
– Overlapping patterns also detected (1111...)
❑ Input In
❑ Output Out
❑ Reset causes FSM to start in initial state
❑ Clock input not shown (always present)

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111 PATTERN DETECTOR: MOORE STATE DIAGRAM

Moore

Mealy

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TRANSITION/OUTPUT TABLE
❑ Shows the next state (S*) and output values for each
combination of current state (S) and inputs
❑ Used to derive the minimized state transition (S*) and
output Boolean equations

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MOORE TRANSITION/OUTPUT TABLE

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MEALY TRANSITION/OUTPUT TABLE

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STATE ENCODING
❑ Binary encoding:
▪ N states need log2N FFs
▪ Example: S0=00; S1=01; S2=10; S3=11

❑ One-hot encoding:
▪ Each state has 1 flip-flop, Q of 1 FF =1, Q of others=0
▪ Example: S0=0001
S1=0010
S2=0100
S3=1000

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STATE ENCODING-BINARY

Moore

Init=00

Got1=01

Got11=10

Got111=11

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IMPLEMENT COMBINATIONAL LOGIC

Moore

Q0n = D0
Q1n = D1 Q1Q0
Q1Q0 In 00 01 11 10
In 00 01 11 10
0
0
1 1 1 1
1 1 1 1

D1=InQ1 + InQ0 D0=InQ1 + InQ0’ Out=Q1Q0


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STATE ENCODING-BINARY

Mealy

Init=00

Got1=01

Got11=10

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IMPLEMENT COMBINATIONAL LOGIC

Mealy

Q0n = D0
Q1n = D1 Q1Q0 Out
Q1Q0 In 00 01 11 10 Q1Q0
In 00 01 11 10 In 00 01 11 10
0 x
0 xx 0 x
1 1 x
1 1 x 1 1 x 1

D1=InQ1 + InQ0 D0=InQ1’Q0’ Out=InQ1


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STATE ENCODING-ONE HOT

Moore

Init=0001

Got1=0010

Got11=0100

Got111=1000

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PUSHBUTTON LOCK: MOORE STATE DIAGRAM

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PUSHBUTTON LOCK: MEALY STATE DIAGRAM

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ANALYZING THE SEQUENTIAL LOGIC

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TRANSITION AND OUTPUT EQUATIONS

S0* =
S1* =
Out =

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RECONSTRUCT STATE DIAGRAM

❑ Complete the transition/output table and state diagram


❑ Identify the functionality of the FSM

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BEFORE NEXT CLASS

• Textbook: 4.1- 4.4 (Verilog only)


• Next time: Verilog

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