MICROPROCESSOR 8085 &

MICROCONTROLLER 8051
 Programmable DMA Controller

• Direct Memory Access uses hardware for

accessing the memory, that hardware is
called a DMA Controller.

• Transfers the data between I/O devices and

main memory with very less interaction
with the processor.

• DMA Controller is a control unit, which has

the work of transferring data.

• DMA Controller also contains an address

unit, which generates the address and
selects an I/O device for the transfer of
data
Types of Direct Memory Access (DMA)
There are four popular types of DMA.
1. Single-Ended DMA 2. Dual-Ended DMA
3. Arbitrated-Ended DMA 4. Interleaved DMA

Single-Ended DMA
• Reading and Writing from a single memory address
• Simplest DMA
Dual-Ended DMA:
• Read and Write from two memory addresses
• More advanced than single-ended DMA
Arbitrated-Ended DMA:
• Reading and Writing to several memory addresses.
• More advanced than Dual-Ended DMA.
Interleaved DMA:
• Read from one memory address and write from another memory address.
Working of DMA Controller
The DMA controller registers have three registers as follows.
• Address register – It contains the address to specify the desired location in memory.
• Word count register – It counts the number of words to be transferred.
• Control register – It specifies the transfer mode.

All registers in the DMA appear to the CPU as I/O interface registers. Therefore, the CPU can both read and write into the DMA registers
under program control via the data bus.
• The unit communicates with the CPU through the data bus and control lines.
• Through the use of the address bus and allowing the DMA and RS register to select inputs, the register within the DMA is chosen
by the CPU.
• RD and WR are two-way inputs.
• When BG (bus grant) input is 0, the CPU can communicate with DMA registers.
• When BG (bus grant) input is 1, the CPU has relinquished the buses and DMA can communicate directly with the memory.

The CPU initializes the DMA by sending the given

information through the data bus.
• The starting address of the memory block
where the data is available (to read) or where
data is to be stored (to write).
• It also sends word count which is the number
of words in the memory block to be read or
written.
• Control to define the mode of transfer such as
read or write.
• A control to begin the DMA transfer

Working Diagram of DMA Controller

Modes of Data Transfer in DMA
During the DMA Transfer CPU can perform only those operation in which it doesn’t require the access of
System Bus which means mostly CPU will be in blocked state.
For how much time CPU remains in the blocked state or we can say for how much time CPU will give the
control of DMAC of system buses will actually depend upon the following modes of DMA Transfer and after that
CPU will take back control of system buses from DMAC.

There are 3 modes of data transfer in DMA that are described below.
1. Burst Mode: In this mode Burst of data (entire data or burst of block containing data) is transferred
before CPU takes control of the buses back from DMAC.
This is the quickest mode of DMA Transfer since at once a huge amount of data is being transferred.
Pros:
Fastest mode of DMA Transfer
Cons:
Less user friendly because during the DMA transfer CPU will be blocked.
Percentage of Time CPU remains blocked:
Let time taken to prepare the data be Tx and time taken to transfer the data be Ty. Then percentage of time
CPU remains blocked due to DMA is as follows.

Percentage of time CPU remains in blocked state = Ty * 100% / Tx + Ty

2. Cycle Stealing Mode: Slow I/O device will take some time to prepare data (or word) and within that
time CPU keeps the control of the buses.
Once the data or the word is ready CPU give back control of system buses to DMAC for 1-cycle in which the
prepared word is transferred to memory.
As compared to Burst mode this mode is little bit slowest since it requires little bit of time which is
actually consumed by IO device while preparing the data.
Pros:
Most Efficient way for DMA Transfer.
CPU won’t be blocked entire time.
Cons:
Rate of DMA Transfer will be less.
Percentage of Time CPU remains blocked:
Let time taken to prepare data be Tx and time taken to transfer the data be Ty. Then percentage of time
CPU remains blocked due to DMA is as follows.
Percentage of time CPU remains in blocked state = Ty * 100% / Tx
3. Interleaving Mode: Whenever CPU does not require the system buses then only control of buses will be
given to DMAC.
In this mode, CPU will not be blocked due to DMA at all.
This is the slowest mode of DMA Transfer since DMAC has to wait might be for so long time to just even get
the access of system buses from the CPU itself.
Hence due to which less amount of data will be transferred.
Pros:
CPU will not be blocked at all.
Cons:
Slowest DMA transfer rate.
Percentage of Time CPU remains blocked:
Since, DMA will use System Bus only when CPU is not using it So,
Percentage of time CPU remains in blocked state = 0%
 Programmable Interrupt Controller (PIC)

 There are 5 hardware interrupts in Intel 8085 microprocessors.

 By connecting Intel 8259 with these microprocessors, we can increase their interrupt handling capability.
 Intel 8259 combines the multi-interrupt input sources into a single interrupt output.
 Interfacing of single PIC provides 8 interrupts inputs from IR0-IR7.
 Increased from 5 to 8 interrupts after interfacing 8259 with 8085 microprocessor.

Features of Intel 8259 PIC are as follows:

1. Designed for Intel 8085 and Intel 8086 microprocessor.
2. Programmed either in level triggered or in edge triggered interrupt level.
3. Mask individual bits of interrupt request register.
4. Increase interrupt handling capability upto 64 interrupt level by cascading.
5. Clock cycle is not required.
 The Block Diagram consists of 8 blocks.
There are total 28 pins in Intel 8259 PIC. Data Bus Buffer, Read/Write Logic, Cascade Buffer
Comparator, Control Logic, Priority Resolver and 3 registers-
ISR, IRR, IMR.
Data bus buffer
It acting as a buffer (mediator).
It takes the control word from the 8085 microprocessor and transfer it to the control logic of 8259
microprocessor.
After selection of Interrupt by 8259 microprocessor, it transfer the opcode of the selected Interrupt and address of
the Interrupt service sub routine to the other connected microprocessor.
It consists of 8 bits represented as D0-D7 in the block diagram. Thus, shows that a maximum of 8 bits data can be
transferred at a time.

Read/Write logic
It works only when the value of pin CS is low.
The flow of data depending upon the inputs of RD and WR.
These two pins are active low pins used for read and write operations.

Control Logic
It is the centre of the PIC and controls the functioning of every block.
It has pin INTR which is connected with other microprocessor for taking interrupt request and pin INT for giving
the output.
If 8259 is enabled, and the other microprocessor Interrupt flag is high then this causes the value of the output
INT pin high and in this way 8259 responds to the request made by other microprocessor.
Interrupt request register (IRR)
It stores all the interrupt level which are requesting for Interrupt services.

Interrupt Service register (ISR)

It stores the interrupt level which are currently being executed.

Interrupt Mask register (IMR)

It stores the interrupt level which have to be masked by storing the masking bits of the interrupt level.

Priority resolver
After examinations of all the three registers and set the priority of interrupts and according to that the highest
priority is set in ISR register.
Also, it reset the interrupt level which is already been serviced in IRR register.

Cascade buffer
To increase the Interrupt handling capability, a more number of pins cascaded by using cascade buffer.
So, during increment of interrupt capability, CSA lines are used to control multiple interrupt structure.

SP/EN (Slave program/Enable buffer) pin is set to high, works in master mode else in slave mode.
In Non Buffered mode, SP/EN pin is used to specify whether 8259 work as master or slave.
In Buffered mode, SP/EN pin is used as an output to enable data bus.
Advantages
Interrupt Management: designed to handle interrupts efficiently and effectively
Flexibility: customized to suit the specific needs of a given system
Compatibility: compatible with a wide range of microprocessors
Multiple Interrupt Inputs: manage up to 8 interrupt inputs
Ease of Use: simple interface pins and registers

Disadvantages
Cost: relatively affordable but costlier if multiple PICs are required
Limited Number of Interrupts: up to 8 interrupt inputs may be insufficient for some applications
Complex Programming: programming the 8259 can be complex
Limited Functionality: does not include more advanced features, such as DMA or advanced error
correction
 Programmable Communication Interface (PCI)

 The 8251A is a programmable serial communication interface chip designed for synchronous and
asynchronous serial data communication.
 It supports the serial transmission of data.
 It is packed in a 28 pin DIP.
 It is also called USART (Universal Synchronous Asynchronous Receiver Transmitter).

Block Diagram:
The functional block diagram of 8251A consists of five sections. They are:
 Read/Write control logic unit
 Transmitter unit
 Receiver unit
 Data bus buffer unit
 Modem control unit.
Block Diagram:
The functional block diagram of 8251A
consists of five sections. They are:
 Read/Write control logic unit
 Transmitter unit
 Receiver unit
 Data bus buffer unit
 Modem control unit.
Read/Write control logic:
 The Read/Write Control logic interfaces the 8251A with CPU, determines the functions of the 8251A
according to the control word written into its control register.
 It monitors the data flow.
 This section has three registers and they are control register, status register and data buffer.
 The eight parallel lines, D7-D0, connect to the system data bus so that data words and control/status
words can be transferred to and from the device.
 The chip select (CS) input is connected to an address decoder so the device is enabled when addressed.
 The signals RD, WR, CS and C/D are used for read/write operations with these three registers.
 It has two internal addresses, a control address which is selected when C/D is high (1), and a data
address which is selected when C/D input is low (0).
 When the RESET is high, it forces 8251A into the idle mode.
 The CLK (clock input) is necessary for 8251A for communication with CPU and this clock does not control
either the serial transmission or the reception rate.
Transmitter section:
 The transmitter section accepts parallel data from CPU and converts them into serial data.
 The transmitter section is double buffered, i.e., it has a buffer register to hold an 8-bit parallel data and
another register called output register to convert the parallel data into serial bits.
 When output register is empty, the data is transferred from buffer to output register. Now the
processor can again load another data in buffer register.
 Transmit buffer - This block is used for parallel to serial
converter that receives a parallel byte for conversion into
serial signal and further transmission onto the common channel.
• TXD: It is an output signal, if its value is one, means
transmitter will transmit the data.
 Transmit control – This block is used to control the data
transmission with the help of following pins:
• TXRDY: It means transmitter is ready to transmit data
character.
• TXEMPTY: An output signal which indicates that TXEMPTY
pin has transmitted all the data characters and transmitter is
empty now.
• TXC: An active-low input pin which controls the data
transmission rate of transmitted data.
• The clock frequency can be 1, 16 or 64 times the baud rate.
Receiver Section:
 The receiver section accepts serial data and convert them
into parallel data.
 The receiver section is double buffered, i.e., it has an input
register to receive serial data and convert to parallel, and a
buffer register to hold the parallel data.
 When the RxD line goes low, the control logic assumes it as a
START bit, waits for half a bit time and samples the line again.
 If the line is still low, then the input register accepts the
following bits, forms a character and loads it into the buffer
register.
 The CPU reads the parallel data from the buffer register.
 When the input register loads a parallel data to buffer register,
the RxRDY line goes high, i.e., it is ready to receive the data.
 The clock signal RxC controls the rate at which bits are
received by the USART.
 During asynchronous mode, the signal SYNDET/BRKDET will
indicate the break in the data transmission.
 During synchronous mode, the signal SYNDET/BRKDET will
indicate the reception of synchronous character.
MODEM Control:
 A device converts analog signals to digital signals and vice-versa and
helps the computers to communicate over telephone lines or cable wires.
 This unit takes care of handshake signals for MODEM interface.
 The following are active-low pins of Modem.
• DSR: Data Set Ready signal is an input signal.
• DTR: Data terminal Ready is an output signal.
• CTS: It is an input signal which controls the data transmit
circuit.
• RTS: It is an output signal which is used to set the status RTS.
 Programmable Counter / Interval Timer

 8254 is a device designed to solve the timing control problems in a microprocessor.

 It has 3 independent counters, each capable of handling clock inputs up to 10 MHz, and size of each counter is 16
bit.
 It operates in +5V regulated power supply and has 24 pin signals.
 All modes are software programmable.
 The 8254 is an advanced version of 8253 which did not offered the feature of read back command.
Block Diagram:
The functional block diagram of 8254 consists of 6 sections. They are:
 Read/Write control logic unit
 Control Register
 Data bus buffer unit
 3no’s of Counters
Block Diagram:
The functional block diagram of 8254
consists of 6 sections. They are:
• Read/Write control logic unit
• Control Register
• Data bus buffer unit
• 3no’s of Counters
Read/Write control logic:
 It includes 5 signals, i.e. RD, WR, CS, and the address lines A0 & A1.
 In the peripheral I/O mode, the RD and WR signals are connected to IOR and IOW, respectively.
 In the memory mapped I/O mode, these are connected to MEMR and MEMW.
 Address lines A0 & A1 of the CPU are connected to lines A0 and A1 of the 8253/54, and CS is tied to a
decoded address.
 The control word register and counters are selected according to the signals on lines A0 & A1.

A1 A0 Result
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Word Register
X X No Selection
Control Word Register:
 This register is accessed when lines A0 & A1 are at logic 1.
 It is used to write a command word, which specifies the counter to be used, its mode, and either a read or
write operation.
 Following table shows the result for various control inputs.

A1 A0 RD WR CS Result
0 0 1 0 0 Write Counter 0
0 1 1 0 0 Write Counter 1
1 0 1 0 0 Write Counter 2
1 1 1 0 0 Write Control Word
0 0 0 1 0 Read Counter 0
0 1 0 1 0 Read Counter 1
1 0 0 1 0 Read Counter 2
1 1 0 1 0 No operation
X X 1 1 0 No operation
X X X X 1 No operation
Data Bus Buffer:
 It is a tri-state, bi-directional, 8-bit buffer, which is used to interface
the 8253/54 to the system data bus.
 It has three basic functions −
• Programming the modes of 8253/54.
• Loading the count registers.
• Reading the count values.

Counters:
 Each counter consists of a single, 16 bit-down counter, which can be
operated in either binary or BCD.
 Its input and output is configured by the selection of modes stored in the
control word register.
 The programmer can read the contents of any of the three counters
without disturbing the actual count in process.
 It has 3 counters each with two inputs (Clock and Gate) and one output.
Gate is used to enable or disable counting. When any value of count is
loaded and value of gate is set(1), after every step value of count is
decremented by 1 until it becomes zero.
Applications –

• To generate an accurate time delay

• As an event counter
• Square wave generator
• Rate generator
• Digital one shot