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VHDL Lab Report

The document describes a laboratory exercise completed by a student. It includes code snippets and output figures for 5 tasks involving VHDL basics and uploading code to an FPGA board. It discusses an issue of pins already being assigned and how it was resolved by changing pin properties.

Uploaded by

Navindu Perera
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
45 views

VHDL Lab Report

The document describes a laboratory exercise completed by a student. It includes code snippets and output figures for 5 tasks involving VHDL basics and uploading code to an FPGA board. It discusses an issue of pins already being assigned and how it was resolved by changing pin properties.

Uploaded by

Navindu Perera
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Sri Lanka Institute of Information Technology

B.Sc. Engineering (Hons) Degree

Year 3 – Semester 2 (2022)

EC3102 – Advanced Digital Design

Laboratory Exercise 3

Name: Perera P. N. D
EN Number: EN20401412
Date of Performance: 31-08-2022
Date of Submission: 07-09-2022
Continuous Assessment Cover
Sheet
Faculty of Engineering
Module Details
Module Code EC3102 Module Title Advanced Digital Design
Program: SLIIT Course: BSc
Stream: Mechatronics

Assessment details
Title Lab 3 Group assignment NO
If yes, Group No.
Lecturer/ Instructor Mr. Sachith Perera Date of Performance 31-08-2022
Due date 07-09-2022 Date submitted 06-09-2022

Student statement and signature


By this declaration, I/we confirm my/our understanding and acceptance that the work reported in this report is my/our own work. I/we also
understand the consequences of engaging in plagiarism or copying others work without proper citation. Any material used in this work (whether
from published sources, the internet or elsewhere) have been fully acknowledged and referenced and are without fabrication or falsification of
data.
[Copying or plagiarism will result in a “0” mark for the continuous assessment and “F” for the module after an investigation on academic
misconduct;

All academic misconduct is considered seriously and defined as dishonest and in direct opposition to the values of a learning community.
Misconduct may result in penalties from failure to exclusion from the campus.
Further help and guidance on how to avoid academic misconduct can be obtained from your academic advisor/tutor]

By this declaration, I/we confirm my understanding and acceptance that-


• I/we have adhered to relevant ethical guidelines and procedures in the completion of the assignment.
• I/we have not allowed another student to have access to or copy from this work.
• This work has not been submitted previously.
[The Institute may request an electronic copy of this work for submission to the Plagiarism detection facility (TURNITIN). You must make sure
that an electronic copy of your work is available in these circumstances]

Details of the student/s submitting the assignment Signature


ID Number Name (As per the institute records )

EN20401412 Perera P N D

OFFICE USE ONLY


Receiving Officer Specific comments about the work (including overall comments and
(seal, signature, date) guidelines for improvement)
Tutor: Signature: Date:

Marks: [ All marks are subject to external moderation and approval of board
of examinations]
Part I

Figure 1 Part I Code

Figure 2 Part I Pin assignment


Figure 3 Part I Final output on Altera board
Task II

Figure 4 Part II code

Figure 5 Part II pin assignment


Figure 6 Part II final output on Altera Board
Task III

Figure 7 Part III code

Figure 8 Part III Pin assignment


Figure 9 Part III final output on Alter Board
Part IV

Figure 10 Part IV Code

Figure 11 Part IV pin assignment


Figure 12 Part IV output for random input waveform

Figure 13Part IV final output on Altera board


Part V
Figure 14 Part V code
Figure 15 Part V pin assignment

Figure 16 Part V final output on Altera board (SET STATE)


Figure 17 Part V final output on Altera board (RESET STATE)

Conclusion
For concluding this lab, I would mention that, we were able to learn mre about VHDL
basics, and specially we were able to upload some codes to FGPA Altera DE2-70 board and
check how the code really works in a practical situations. And one problem we faced, when
pins are assigned is, some pins are already assigned by default. And those pins can not use
for some other work because it shows that the pin is already assigned. To over come this
problem we found some steps,

Go to the Assignments menu> Device


Select Device and Pin Options

Go to tab on right Dual-Purpose Pins

Double click nCEO


Select Use as regular I/O

By following these steps we could dismiss the error on PIN_AD25. Finally the laboratory
experiment was successful.

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