Digital Systems

Exclusive OR/ Exclusive NOR

The Exclusive OR (EXOR) function is an important
Boolean function used extensively in logic circuits. Uses
for the EXOR gate include:
1. Adders/subtractors
2. Parity Generators/Checkers
3. Signature analyzers
4. Pseudo-random sequence generators
Definitions
The EXclusive OR relation is defined as: xy = x'y + xy'
The EXclusive NOR relation, otherwise
known as Equivalence is defined as: (xy)' = xy + x'y'
Tables for EXOR/ EXNOR
Operator Rules: EXOR EXNOR

x y xy x y (xy)'
or xy
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1
The Exclusive Or function means:
x OR y, but NOT BOTH
The Exclusive Nor function, denoted by the operator , is
sometimes known as the "Equivalence" function. Why?
 EXOR/EXNOR Extensions
The EXOR function w(xy) = w(xy)' + w'(xy)
can be extended to 3 = w(xy'+x'y)' + w'(xy'+x'y)
or more variables. For = w[(xy')'(x'y)'] + w'xy' + w'x'y
more than 2 variables, = w[(x'+y)(x+y')] + w'xy' + w'x'y
it is called a modulo 2 = w[x'x+x'y'+xy+yy']+w'xy'+w'x'y
sum (Mod 2 sum), not = w[0+x'y'+xy+0]+w'xy'+w'x'y
EXOR: = wx'y'+wxy+w'xy'+w'x'y
These identities can x0 = x x1 = x'
be shown to hold: xx = 0 xx' = 1
xy' = (xy)' x'y = (xy)'
Further commutative
and associative laws xy = yx
apply thus: (xy)z = x(yz) = xyz
EXOR Implementations
X
The simple SOP
implementation uses
the following XY

structure:
Y

A NAND only
implementation is:
 EXOR Implementations
(Cont.)
The AND-OR implementation is simply a SOP form of the
equation defining the EXOR function:
xy = x' y + x y'
The multiple level NAND implementation is a little more
interesting. The last two stages implement the SOP form for:
xy = x T + y T where: T = (xy)' = (x'+y')
Substituting for T we get:
xy = x (x'+y')+ y (x'+y')
= x x' + x y' + x' y +y y'
= 0 + x y' + x' y + 0
= x y' + x' y
Odd Function
Going back to 3-input Mod 2 Sum definition:
w(xy) = w(xy)' + w'(xy)
which becomes: (100) (111) (010) (001)
= wx'y'+wxy+w'xy'+w'x'y
We see that the function value is "1" for one, or three "ones" in
the input variables.
This extends to an "N" input EXOR function which attains a
value of "1" if and only if the number of ones in the input
variable set is odd. Thus the Mod 2 Sum function is called the
Odd Function.
Multiple input EXOR functions are difficult to implement in
practice, so a multilevel tree structure is used to implement
the function, using 2-input EXOR gates as blocks.
Odd Function Implementation
Three-Input Odd Function:

Four Input Odd Function:

These structures are also called parity trees, since the

ODD Function is really a parity function.
K-Maps of ODD and EVEN
y y

1 1 1 1

1 1 1 1
x x
1 1 1 1
w w
1 1 1 1
Note: n bit Odd or Even
z z
function, there will be
Odd Function Even Function
(2**n)/2 or 2**(n-1) product
v=0 y v=1 y terms of n variables
1 1 1 1 (minterms)!
1 1 1 1
x x
1 1 1 1
w w
1 1 1 1

z z

Odd Function of Five Bits

 Parity Generators/Checkers
We can use a parity tree to generate parity which is then
appended to the data
X
Example: Y
Three-bit EVEN
P
parity generator
Z

We can use a 4-bit parity tree to check the3-Bit

codeword Parity
for G
correct parity. Here C=0 if the parity is correct as
generated above, and C=1 if an error has occurred.
Example:
Three-bit EVEN
parity checker
Integrated Circuits
SSI -- Small Scale Integration -- gates, simple logic
functions, and basic storage elements. (~10 gates)
MSI -- Medium Scale Integration -- tend to be simple
functions that can be packaged in the 14 to 24 pin
packages. (~10 to 100 gates)
LSI -- Large Scale Integration -- regular, programmable
structures such as PAL, PROM, and PLD Devices, or
custom devices. (~100 to a few 1000 gates)
VLSI -- Very Large Scale Integration -- tend to be custom
microprocessors and regular memory components. (Many
gates)
Digital Logic Families
Logic elements are constructed from various circuit
components.
Based on physical characteristics, they are organized into
families. Here are a few families:
RTL Resistor-Transistor Logic (old)
DTL Diode-Transistor Logic (old)
TTL Transistor-Transistor Logic
ECL Emitter Coupled Logic
MOS Metal Oxide Semiconductor
CMOS Complementary Metal-Oxide Semiconductor
Bi- Bipolar Complementary Metal-Oxide
CMOS Semiconductor
Compatibility
Logic device families have characteristics which are
defined by some of the following parameters:
Fan-in -- the number of inputs available on a gate.
Fan-out -- the number of inputs the output of one gate can drive.
Logic Levels -- The signal values defining "1" and "0".
Propagation Delay -- The time for an input signal change to
propagate to the output.
Noise Margin -- the amount of noise a logic signal will tolerate
without error.
Power Supply -- the voltages required to allow the circuit to
operate.
Power Dissipation -- the amount of power a circuit consumes.
Propagation Delay
Propagation delay is the time for a change in the input of a
gate to propagate to the output.
Delay is usually measured from the 50% of logic level voltage
reference points.
High-to-low (tPHL) and low-to-high (tPLH) output signal
changes may have different propagation delays.
High-to-low (tPHL) and low-to-high (tPLH) propagation delays
are measured on output transitions.
A "0" to "1" input transition causes a "1" to "0" output
transition if the gate inverts, and a "0" to "1" output
transition if the gate does not invert.
Propagation Delay Example
What is the delay for:
In A a string of inverters?
a string of buffers?
B

B
TPHL

TPLH
In

TPLH
A TPHL
Positive and Negative Logic
The same physical gate can have different logical meanings
depending on how we interpret the signal levels.
Positive Logic
 Logic 1 is set to high (more positive) signal levels
 Logic 0 is set to low (less positive) signal levels
Negative Logic
 Logic 1 is set to low (more negative) signal levels
 Logic 0 is set to high (less negative) signal levels

A gate which implements a Positive Logic AND function

will implement a Negative Logic OR function.
Positive and Negative Logic
Given this signal level table: Input Output
X Y
L L L
L H H
What logic function is H L H
implemented? H H H

Positive (H = 1) Negative (H = 0)
Logic (L = 0) Logic (L = 1)
0 0 0 1 1 1
0 1 1 1 0 0
1 0 1 0 1 0
1 1 1 0 0 0
Positive and Negative Logic (Cont.)
Rearranging the negative logic terms to be in proper
function table order we get:
Positive (H = 1) Negative (H = 0)
Logic (L = 0) Logic (L = 1)
0 0 0 0 0 0
0 1 1 0 1 0
1 0 1 1 0 0
1 1 1 1 1 1

Positive logic "OR", Negative Logic "AND"

Logic Conventions
Symbols:
XYZ
X
Z
CKT
LLL
Y
LHH
Logic Circuit
HLH
HHH

X X
Z Z
Y Y
Positive Logic
Negative Log