0% found this document useful (0 votes)
30 views

Subscription For CADEMICS - Digital Program - 2024 - 1st Semester

The document is a subscription form for two digital courses on RTL digital design and verification offered in the first semester of 2024 as part of the CADEMICS program. The courses will cover concepts of digital design using HDL and fundamentals of verification using SystemVerilog. The form collects student and university information for subscription.

Uploaded by

hg
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
30 views

Subscription For CADEMICS - Digital Program - 2024 - 1st Semester

The document is a subscription form for two digital courses on RTL digital design and verification offered in the first semester of 2024 as part of the CADEMICS program. The courses will cover concepts of digital design using HDL and fundamentals of verification using SystemVerilog. The form collects student and university information for subscription.

Uploaded by

hg
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 6

12/7/23, 4:49 PM Subscription for CADEMICS - Digital program - 2024 - 1st Semester

Subscription for CADEMICS - Digital program -


2024 - 1st Semester
Welcome to CADEMICS program, trough CADEMICS Program, Cadence will offer two trainings on the first semester of
2024.

RTL Digital Design e Verification:

RTL Digital Design:

In this course, the student will learn the concepts for digital design, in modern IC digital flow (VLSI flow), the chip intent
is described in a Hardware Description Language (HDL) in a special level of abstraction known as Register Transfer
Level (RTL), the RTL source code is used for other phases of the project such as logical synthesis and physical
implementation. This training will cover how to capture a design intent coding the RTL source code. This training
part of a series, it was designed to fit in one semester.

Verification:

This course will cover the fundamentals of functional verification using Systemverilog Language. Verification is an
important step in a ASIC design flow, this is the phase in which a verification professional will write testcases,
regressions to verify the circuit and run cover analysis to try to find bugs before the chip is fabricated. This training
part of a series, it was designed to fit in one semester

These courses are available to universities participants of the Cadence - SBMicro University APCI program. If your
University is not a member of this program, please contact your university and ask them to reach out to SBMicro
https://forms.office.com/pages/responsepage.aspx?id=xTVg0-ZsYkaj3Odi5hrkySDSDCKyrwNKmAzYDXlCGUhUN1NXU1M3OExEMVdSV1FNMFFRUTZZOERSOC4u 1/6
12/7/23, 4:49 PM Subscription for CADEMICS - Digital program - 2024 - 1st Semester

(https://sbmicro.org.br/programas/apci) in order to proceed with the University subscription.

You will receive a confirmation email after you submit your subscription. We will send you some follow up emails with
instructions on how to access the trainings, please, watch your email for further instructions.

SCHEDULE (Subject to changes)

Subscription from Dec 4th, 2023 up to Feb 2nd, 2024

Verification
First online sync ups with TFO team, every other Tuesday, starting Feb 20th 5:30pm

Digital Design:
First online sync ups with TFO team, every other Thursday, starting Feb 20th 5:30pm

We will provide more details on the schedule shortly.

Student information

1. Name *

HIMAGOWRI V

2. LinkedIn

https://forms.office.com/pages/responsepage.aspx?id=xTVg0-ZsYkaj3Odi5hrkySDSDCKyrwNKmAzYDXlCGUhUN1NXU1M3OExEMVdSV1FNMFFRUTZZOERSOC4u 2/6
12/7/23, 4:49 PM Subscription for CADEMICS - Digital program - 2024 - 1st Semester

https://www.linkedin.com/in/himagowri-v-7t/

3. Enter your email (Only valid university email will be accepted) *

[email protected]

University information

4. University Name *

Cadence

Current Status information

5. University period *

Semester

Annual

6. What Year/Semester are you at *

https://forms.office.com/pages/responsepage.aspx?id=xTVg0-ZsYkaj3Odi5hrkySDSDCKyrwNKmAzYDXlCGUhUN1NXU1M3OExEMVdSV1FNMFFRUTZZOERSOC4u 3/6
12/7/23, 4:49 PM Subscription for CADEMICS - Digital program - 2024 - 1st Semester

10

11

12

Other

7. Type *
https://forms.office.com/pages/responsepage.aspx?id=xTVg0-ZsYkaj3Odi5hrkySDSDCKyrwNKmAzYDXlCGUhUN1NXU1M3OExEMVdSV1FNMFFRUTZZOERSOC4u 4/6
12/7/23, 4:49 PM Subscription for CADEMICS - Digital program - 2024 - 1st Semester

Graduation

Post Graduation (not Master or PhD)

Specialization

Master

PhD

Postdoc

Other

8. Your Major *

Electrical Engineering

Computing Engineering

Computer Science

Systems Engineering

Mathematics

Physics

https://forms.office.com/pages/responsepage.aspx?id=xTVg0-ZsYkaj3Odi5hrkySDSDCKyrwNKmAzYDXlCGUhUN1NXU1M3OExEMVdSV1FNMFFRUTZZOERSOC4u 5/6
12/7/23, 4:49 PM Subscription for CADEMICS - Digital program - 2024 - 1st Semester

Electronics and communication

9. What is your ID (Matrícula) *

PES1UG20EC902

Chose your Program

10. Question *

CADEMICS - RTL Digital Design 2024-1

CADEMICS - Verification 2024-1

This content is created by the owner of the form. The data you submit will be sent to the form owner. Microsoft is not responsible for the
privacy or security practices of its customers, including those of this form owner. Never give out your password.
Microsoft Forms | AI-Powered surveys, quizzes and polls Create my own form
The owner of this form has not provided a privacy statement as to how they will use your response data. Do not provide personal or sensitive
information. | Terms of use

https://forms.office.com/pages/responsepage.aspx?id=xTVg0-ZsYkaj3Odi5hrkySDSDCKyrwNKmAzYDXlCGUhUN1NXU1M3OExEMVdSV1FNMFFRUTZZOERSOC4u 6/6

You might also like