Pastyear
Pastyear
1. (a) Design a 16-bit adder that uses four 4-bit carry-lookahead adders along with additional logic
circuits to generate c4, c8, c12, and c16 from c0 and GiII and PiII variables. Calculate the number of logic
gates needed to build the circuit. [3]
(b) Show that if a bit-pair recording of the multiplier is used for an n x n multiplication, then the
number of CSA levels required to reduce the number of summands in the multiplication to two vectors
is 1.7log2n – 3.4. [3]
2. (a) Consider a floating-point number represented in 12-bit with 1-bit for sign, 5-bit for exponent, and
6-bit for the mantissa. The ordering of sign, exponent and mantissa in the number is same as that in
IEEE. The 6-bit mantissa is normalized as in the IEEE format, with an implied 1 to the left of the
binary point. The end values of the exponenet 0 and 31 used to signify exact 0 and infinity,
respectively. Represent the number -1/8 in this format. [3]
(b) Using bit-pairing recoding of multipliers, multiply the signed numbers A = 010111 and B = 110110.
Assume that A is the multiplicand and B is the multiplier. [3]
3. (a) The following number use the IEEE 32-bit floating-point format. What is the equivalent decimal
value? [3]
1 10000011 11000000000000000000000
(b) Draw the Big-endian and Little-endian layout for the given data structure [3]
struct {
int i; //0x 11121314
int j; //0x 15161718
}
4. (a) A computer has 32-bit instructions and 12-bit addresses. If there are 250 two-address instructions,
how many one-address instructions can be formulated? [3]