Be Computer Engineering Semester 3 2017 December Digital Logic Design and Analysis Cbcgs
Be Computer Engineering Semester 3 2017 December Digital Logic Design and Analysis Cbcgs
SEMESTER 3
Digital Logic Design And Analysis
DECEMBER 2017-CBCS
Remainder
8 1762 2
220 4 ∴ (1762)10 = (3342)8
27 3
3 3
Fractional part :
0. 46
8
3 68 ∴ (0.42)10 = (0.353)8
8
5 44 ∴ (1762.46)10 = (3342.353)8
8
3 52
2 1762 0
881 1 ∴ (1762)10 = (11011100010)8
440 0
220 0
110 0
55 1
27 1
13 1
6 0
3 1
1 1
Fractional part :
0. 46
2
0 92 ∴ (0.42)10 = (0.011)2
2
1 84 ∴ (1762.46)10 = (11011100010.011)2
2
1 68
Remainder
16 1762 2
110 E ∴ (1762)10 = (6E2)16
6 6
Fractional part :
0. 46
16
7 36 ∴ (0.42)10 = (0.75C)2
16
5 76 ∴ (1762.46)10 = (6E2.75C)2
16
C 16
X=(1010001)
(g) Implement the following Boolean equation using NAND gates only.
Y= AB+CDE+F [2]
Ans : In this y can be implemented using 3 input nand and 2 input nand
gates.
(h) Explain the term prime implicant. [2]
Ans :
i) A group of related 1's (implicant) on a Karnaugh map which is not subsumed by
any other implicant in the same map. Equivalently (in terms of Boolean algebra), a
product term which is a "minimal" implicant in the sense that removing any of its
literals will yield a product term which is not an implicant (on a Karnaugh map it
would appear "maximal").
ii) A group of related 0's (implicant) on a Karnaugh map which is not subsumed by
any other implicant (of 0's) in the same map.
(ii) A ripple carry adder is a logic circuit in which the carry-out of each full adder is
the carry in of the succeeding next most significant full adder. It is called a ripple carry
adder because each carry bit gets rippled into the next  stage.
(iii)In a ripple carry adder the sum and carry out bits of any half adder stage is not
valid until the carry in of that stage occurs.
(iv)Propagation delays inside the logic circuitry is the reason behind this. Propagation
delay is time elapsed between the application of an input and occurance of the
corresponding output.
(v)Consider a NOT gate, When the input is “0” the output will be “1” and vice versa.
The time taken for the NOT gate’s output to become “0” after the application of logic
“1” to the NOT gate’s input is the propagation delay here.
(v)Similarly the carry propagation delay is the time elapsed between the application of
the carry in signal and the occurance of the carry out (Cout) signal.
(vi) Sum out S0 and carry out Cout of the Full Adder 1 is valid only after the
propagation delay of Full Adder 1.
(vii) In the same way, Sum out S3 of the Full Adder 4 is valid only after the joint
propagation delays of Full Adder 1 to Full Adder 4. In simple words, the final
result of the ripple carry adder is valid only after the joint propogation delays of
all full adder circuits inside it.
A B C D
1 0 0 0 1
2 0 0 1 0
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
Step 2:
Create the following table in which the binary number with equal number of
1's are grouped together. For e.g. the first group contains binary numbers with
only one number of 1's, second group contains binary numbers with two 1's
and so on.
Step 3: In the next step compare every element of group 1 with elements in
group 2, elements of group 2 with 3, etc. In general compare elements of nth
group with elements of n+1th group. If only 1 element is changing in the
comparison the mark it with an underscore. Put a tick mark against both the
elements if the elements are present in the comparison. For e.g. in m1 and m5
the A, C, D bits are same but only B bit changes, so an underscore is put
against it.
Step 4: In this step again match the values of nth group with n+1th group and
mark tick against the ones that gets matched, followed by underscore to the
single bits that change. Since m1 m5, d2 m6 are not getting matched with any
other no tick marks is put against them.
Step 5: Now make the last table which contains the prime implicant and the
min terms involved (Prime implicants are the ones that do not get matched).
Write them in their alphabet form with 0 bit represented as bars. In this step
write all the numbers which were given in the question (not the don't care
ones). Put a cross below the numbers which contain the minterms.
Prime Minterms 1 5 6 12 13 14
Implicant Involved
BC 4, 5, 12, 13 ˟ ˟ ˟
BD 4, 6, 12, 14 ˟ ˟ ˟
ACD 1, 5 ˟ ˟
ACD 2, 6 ˟
If the column of the numbers contain only one cross then the prime implicant
belonging to the single cross belonging row is considered. In this case the
columns of 1, 13 and 14 contain only 1 crosses so the row belonging to them is
considered which are BC, BD, ACD. These are the reduced answer.
Y = BC + BD + ACD
∴ F(A,B,C,D) = BC + BD + ACD
A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
We will require two 8:1 multiplexer to implement a full adder. One for sum
and one for carry.
In 8:1 MUX we have 3 selection lines, assigning them A, B, C.For sum :
For carry :
(b) Implement the following functions using demultiplexer.
F1(A,B,C)=∑𝐦(0,3,7) F2(A,B,C)=∑𝐦(1,2,5) [5]
Ans :
(1) F1 (A, B, C) = 𝛴m(0, 3, 7)
Number of variables = 3
Number of select lines = 3
Number of lines = 23 = 8
F(A,B,C,D)=∏m(0,1,2,8,9,12,13,14)
K-map is given by
Circuit Diagram :
Q.4(a) Compare TTL and CMOS logic withn respect to fan in,fan out
Propogation delay,power consumption,noise margin,current and
Voltage parametes. [5]
Ans :
Parameter TTL CMOS
Propagation Delay 1 to 200nsec 1.5 to 33nsec
Power consumption Relatively High Depends on Vcc
Noise Margin 0.3-0.5 0.3Vcc
Current High (0.2-2mA) Low (1uA)
Voltage 5V 3-18V
Fan in High fan in Low fan in
Fan out Approx. 10 >50
Transistor used BJT FET
Type Current controlled Voltage controlled
Current devices current device
(b) Draw the circuit of SR flip flop using two NOR gates and write the
Architecture body for the same using structural modelling. [5]
Ans :
SR FLIP FLOP
Architectural Body :
begin
PROCESS(CLOCK)
begin
tmp:=tmp;
tmp:='Z';
tmp:='0';
else
tmp:='1';
end if;
end if;
Q <= tmp;
i) BCD adder adds two BCD digits and produces output as a BCD digit. A
BCD or Binary Coded Decimal digit cannot be greater than 9.
ii)The two BCD digits are to be added using the rules of binary addition. If
sum is less than or equal to 9 and carry is 0, then no correction is needed. The
sum is correct and in true BCD form.
iii)But if sum is greater than 9 or carry =1, the result is wrong and correction
must be done.
S3 S2 S1 S0 Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
vi) The Boolean expression is, Y=S3S2+S3S1Y=S3S2+S3S1
vii)The BCD adder is shown below. The output of the combinational circuit
should be 1 if Cout of adder-1 is high. Therefore Y is ORed with Cout of adder
1.
viii)The output of combinational circuit is connected to B1B2 inputs of adder-2
and B3=B1+0B3=B1+0 as they are connected to ground permanently. This
makes B3B2B1B0B3B2B1B0 = 0110 if Y' = 1.
Qn 𝑄𝑛+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
3.Conversion Table:
S R 𝑄𝑛 𝑄𝑛+1 J K
0 0 0 0 0 X
0 1 1 1 X 0
0 0 0 0 0 X
0 1 1 0 X 1
1 0 0 1 1 X
1 1 1 1 X 0
1 0 - - X X
1 1 - - X X
4. Logical expressions for the inputs :
Simplify the logical expressions for the inputs of the given flip-flop (J and K) in terms
of the inputs of the desired flip-flop (S and R) and the flip-flop's present-state, Qn.This
can be done by following any logical simplification technique like that of the
K-map.
5. Circuit Diagram :
S J 𝑄𝑛
CLK JK FF
R K 𝑄𝑛+1
(B) JK TO D FF :
D Q 𝑄̅
0 0 0
0 1 0
1 0 1
1 1 1
2.Excitation Table of JK FF:
Qn 𝑄𝑛+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
3.Conversion Table :
D 𝑄𝑛 𝑄𝑛+1 J K
0 0 0 0 X
0 1 1 0 1
1 0 0 1 X
1 1 0 1 0
4.Use a K-map to obtain the logical expressions for the inputs J and K
in terms of D and Qn.
5. Circuit Diagram:
D J 𝑄𝑛
CLK JK FF
K
𝑄𝑛+1
(b) Design 3 bit synchronous counter using T flip flops. [10]
(ii)The only way we can build such a counter circuit from T flip-flops is to
connect all the clock inputs together, so that each and every flip-flop receives the
exact same clock pulse at the exact same time.
(iii) For an up counter that means it will count from value 0 to 7 for interval
difference of 1.
(viii)The output of first T flip-flop toggles for every negative edge of clock
signal.
(ix)The output of second T flip-flop toggles for every negative edge of clock
signal if Q0Q0 is 1.
(x)The output of third T flip-flop toggles for every negative edge of clock signal
if both Q0Q0 & Q1Q1 are 1.
(Here we can write Q3Q2Q1=Q2Q1Q0).
Q.6 Write short note on (any four) [20]
Ans :
i) The state table representation of a sequential circuit consists of three
sections labeled present state, next state and output.
iii) The next state shows the states of flip-flops after the clock pulse, and
the output section lists the value of the output variables during the
present state.
iv) The 4-bit wide ALU can perform all the traditional add / subtract /
decrement operations with or without carry, as well as AND /
NAND, OR / NOR, XOR, and shift.
ii) These circuits when suitably manipulated can be made to count till
an intermediate level also. This means that instead of counting till 7, we
can terminate the process by resetting the counter just at, say, 5. Such
counters are then known as mod-N counters.
D1 Q1 D0 Q0
CLK
Sequence Generator
Truth Table :
CLK 𝑄3 𝑄2 𝑄1 𝑄0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0