Lab 5 EEPROM
Lab 5 EEPROM
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed.
When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.
EEARH and EEARL – EEPROM Address Register
Bit 15 14 13 12 11 10 9 8
Bit 7 6 5 4 3 2 1 0