Arithmetic instructions

 Addition
 Subtraction
 Multiplication
 Division
 BCD and ASCII arithmetic instruction
Basic logic operation
 AND, OR, NOT, XOR
Shift and Rotate instruction
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 Syntax:- ADD Destination, source
 Algorithm:- destination = destination + source
 Where (Destination , source combination)

 Flag affected

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 Syntax:- ADC Destination, source
 Algorithm:-destination = destination + source + cf
 Where (Destination , source combination)

 Flag affected

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 The source and destination can not be both memory
 Both source and destination must be the same size
(Both word and byte)

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 Syntax:- INC Destination
 Algorithm:-destination = destination + 1
 Where destination can be a register or memory location
 Example
MOV AX, 5 ;
INC AX ; AX= 6

 Flag affected

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 Syntax:- SUB Destination, source
 Algorithm:- destination = destination - source
 Where (Destination , source combination)

 Flag affected

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 Syntax:- SBB Destination, source
 Algorithm:-destination = destination – source - cf
 Where (Destination , source combination)

EXAMPLE
STC ; set carry flag
MOV al, 4 ; al =4
SBB al,2 ; al =1

 Flag affected

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 Syntax:- DEC Destination
 Algorithm: destination = destination + 1
 Where destination can be a register or memory location
 Example
MOV AX, 5 ;
DEC AX ; AX= 4

 Flag affected

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 Syntax:- NEG Destination
 where destination can be register or a memory location
 Algorithm: destination = 2’s compliment of destination.

 Flags Affected

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 Mul (Unsigned multiplication)
 Syntax:- mul operand (where operand can be a
register or a memory location
 Algorithm:

 Flags Affected : AF, PF, SF and ZF

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 Syntax:- imul operand
 Where operand can be Register or memory location
 Algorithm (what it does)

 Example

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 Div(unsigned division)
 Syntax:- DIV operand
 Where operand can be a register or memory location
 Algorithm

 All flags are undefined (0) after DIV instruction

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 Syntax:- idiv operand
 Where operand can be a register or memory location
 Algorithm:-

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 BCD Arithmetic
 DAA(decimal adjust after addition )
 DAS (Decimal adjust after subtraction)
 Syntax DAA (no operand)
 Function:-
 Corrects the result of addition of two packed BCD values
 Algorithm

•Works only on AL
•Updates all Flags

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 AAA (Ascii adjust after addition)
 Function:
 Corrects result in AH and AL after addition when working
with BCD values.

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 Algorithm :
 If Low nibble of AL>9, or AF = 1, then
 AL = AL+6, Af and CF + 1 and also higher nibble of Al is cleared
to 0
 Else
 AF and CF = 0
 Works only on AL

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AAS (ASCII adjust after subtraction)
AAM (ASCII adjust after multiplication)
AaD (ascii adjust before division)

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 Included in this groups of instruction are
 AND,
 OR,
 XOR,
 NOT and
 TEST(which is a kind of And operator)

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 Syntax: AND operand1, operand2
 Where OP1, op2 combination can be

 Function: Logical AND between all bits of two

operands. Result is stored in operand1
 Algorithm

Flags Affected
•Both CF and OF = 0
•PF,SF and ZF affected
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 Syntax or operand1, operand2
 Where op1,op2 combination can be

 Function:-Logical OR between all bits of two

operands. Result is stored in first operand.
 Algorithm:

Flags Affected
•Both CF and OF = 0
•PF,SF and ZF affected
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 Syntax xor operand1, operand2
 Where op1,op2 combination can be

 Function:-Logical XOR (Exclusive OR) between all

bits of two operands. Result is stored in first operand
 Algorithm:

Flags Affected
•Both CF and OF = 0
•PF,SF and ZF affected

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 Syntax not operand
 Where operand can be a register or memory location
 Function:-Invert each bit of the operand.
 Algorithm:

 No flag is affected

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 Syntax:- test operand1, operand2
 Where op1,op2 combination can be

 Function:- Logical AND between all bits of two

operands for flags only. These flags are effected: ZF,
SF, PF. Result is not stored anywhere.
 Algorithm:

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shl - Logical Shift Left

CF REG 0

shr - Logical Shift Right

0 REG CF

sal - Arithmetic Shift Left (same as logical)

CF REG 0

sar - Arithmetic Shift Right (sign bit is preserved)

REG CF
MSB

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 The SHL (shift left) instruction performs a logical
left shift on the destination operand, filling the
lowest bit with 0. CF REG 0
 Operand types:
 SHL reg,immediate
 SHL mem,immmediate
 SHL reg,CL
 SHL mem,CL
 All flags are affected

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 Shifting left 1 bit multiplies a number by 2
 mov dl,5 ;dl= 00000101 (5 in decimal)
 shl dl,1 ;dl = 00001010(10 in decimal)
 Shifting left n bits multiplies the operand by 2n

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 SHR Destination, count (Destination can be a register
or a memory location and count can be an immediate
value or can be stored in CL
 The SHR (shift right) instruction performs a logical
right shift on the destination operand. The highest
bit position is filled with a zero.
 All flags are affected 0 REG CF

 Shifting right n bits divides the operand by 2n

 MOV DL,80
 SHR DL,1 ; DL = 40
 SHR DL,2 ; DL = 10

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 SAR Destination, count (Destination can be a register
or a memory location and count can be an immediate
value or can be stored in CL
 SAR (shift arithmetic right) performs a right
arithmetic shift on the destination operand.
 An arithmetic shift preserves the number's sign.
 All flags are affected
 EXAMPLE: REG CF
MOV DL,-80
SAR DL,1 ; DL = -40
SAR DL,2 ; DL = -10

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 ROL Destination, count (Destination can be a register
or a memory location and count can be an
immediate value or can be stored in CL
 ROL (rotate) shifts each bit to the left. The highest
bit is copied into both the Carry flag and into the
lowest bit
CF REG
 No bits are lost
 EXAMPLE:
MOV Al,11110000b
ROL Al,1 ; AL = 11100001b and CF = 1

MOV Dl,3Fh
ROL Dl,4 ; DL = F3h

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 ROR Destination, count (Destination can be a register
or a memory location and count can be an immediate
value or can be stored in CL
 ROR (rotate right) shifts each bit to the right. The
lowest bit is copied into both the Carry flag and into
the highest bit
CF REG
 No bits are lost
 EXAMPLE:
MOV AL,11110000b
ROR AL,1 ; AL = 01111000b
MOV DL,3Fh
ROR DL,4 ; DL = F3h

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 RCL Destination, count (Destination can be a register
or a memory location and count can be an immediate
value or can be stored in CL
 RCL (rotate carry left) shifts each bit to the left and
Copies the Carry flag to the least significant bit and
also Copies the MSB to the Carry flag
 EXAMPLE : CF REG
CLC ; CF = 0
MOV BL,88H ; CF = 0,BL = 10001000b
RCL BL,1 ; CF = 1,BL = 00010000b
RCL BL,1 ; CF = 0,BL = 00100001b

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 RCR Destination, count (Destination can be a register
or a memory location and count can be an immediate
value or can be stored in CL
 RCR (rotate carry right) shifts each bit to the right
and Copies the Carry flag to the most significant bit
and also Copies the least significant bit to the Carry
flag
CF REG
 EXAMPLE
STC ; CF = 1
MOV AH,10H ; CF = 1,AH = 00010000
RCR AH,1 ; CF = 0,AH = 10001000

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 MNEMONIC MEANING OPERATION
 CLC Clear Carry Flag CF = 0
 STC Set Carry Flag CF=1
 CMC Complement Carry Flag CF = !CF
 CLD Clear Direction Flag DF =0
 STD Set Direction Flag DF =1
 CLI Clear Interrupt Flag IF = 0
 STI Set Interrupt Flag IF = 1

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 Compare: CMP D,S
 (D) – (S) is used in setting or resetting the flags
 If (D) = (S) then ZF=0
 If (D) > (S) then ZF=0, CF=0
 If(D) < (S) then ZF=0, CF=1
 Flags Affected CF, AF, OF, PF, SF, ZF

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 These instructions works with
 Flag register(D flag, direction flag)
 Destination index (DI)
 Source index (SI)
 The direction flag (D, located in the flag register)
selects the auto-increment or the auto-decrement
operation for the DI and SI registers during string
operations.
 The CLD instruction clears the D flag and the STD
instruction sets it .
 CLD instruction selects the auto-increment mode and STD
selects the auto-decrement mode
 DI and SI
 Duringexecution of string instruction, memory
accesses occur through DI and SI registers.
 DI offset address accesses data in the extra segment
for all string instructions that use it
 SI offset address accesses data by default
in the data segment
 Operation
 Copy byte at DS:[SI] to ES:[DI]. Update SI and DI.
 After operation
 ES:[DI] = DS:[SI]
 if DF = 0 then

 SI = SI + 1
 DI = DI + 1
 Else

 SI = SI – 1
 DI = DI – 1
 Syntax :LODSB (LOAD STRING)
 Operation
 Load byte at DS:[SI] into AL. Update SI based on DF.
 After excution
 Al = DS:[SI]
 if DF = 0 then
 SI = SI + 1
 Else
 SI = SI – 1

 LODSW bring a word from DS:[SI] to AX registers

 Doesnot affect any flags
 Store string
 Operation
 Store byte at ES:[SI] into AL. Update SI based on DF.
 After the operation
 For STOSB
 ES:[DI] = AL

 if DF = 0 then
 DI = DI + 1

 Else
 DI = DI – 1
  For STOSW
 ES:[DI] = AX

 if DF = 0 then
DI = DI + 2

 Else
DI = DI - 2
 STOSB (stores a byte) stores the byte in AL at the
extra segment memory location addressed by DI.
 STOSW (stores a word) stores AX in the memory
location addressed by DI

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 The repeat prefix (REP) is added to any string data
transfer instruction except LODS.
 REP prefix causes CX to decrement by 1 each time the string
instruction executes;
 after CX decrements, the string instruction repeats
 If CX reaches a value of 0, the instruction terminates
and the program continues.
 If CX is loaded with 100 and a REP STOSB instruction
executes, the microprocessor automatically repeats
the STOSB 100 times
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 SCAN STRING
 SYNTAX: SCAS <String>
 Compares a word in AX or byte in AL with a byte or
word pointed to ES:DI and sets the flags
(AF,PF,OF,SF,ZF)
 Set flags as per (AL or AX) - ((ES)0h+(DI))
 (DI) = (DI) ± 1 or 2 based on DF

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 Compare (DS:SI) with (ES:DI)
 Operation:
 Set flags as per ((DS)0+(SI)) - ((ES)0+(DI))
 (SI) =(SI) ± 1 or 2
 (DI) = (DI) ± 1 or 2
 All status flags(AF,PF,OF,SF,ZF) are affected

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