ANNA UNIVERSITY

UNIVERSITY COLLEGE OF ENGINEERING- DINDIGUL

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

CS3351 – DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION
LABORATORY.

NAME :
REGISTER NO. :
BRANCH :

ANNA UNIVERSITY
1
 UNIVERSITY COLLEGE OF ENGINEERING – DINDIGUL
DINDIGUL – 62422

BONAFIDE CERTIFICATE
This is to certify that is a bonafide record of work done by
Mr./Ms.________________________________________
in _____________________________________________
laboratory during the academic year 2022-2023
University Registration no.:

Staff In charge Head of the Department

Submitted for the university Practical Examination held on __________________

INTERNAL EXAMINER EXTERNAL EXAMINER

INDEX

2
EXPT NAME OF THE EXPERIMENT PAGE DATE OF SIGNATURE
NO. NO. COMPLETIO
N
1. Verification of Boolean theorems using logic 4
gates.
2. Design and implementation of combinational 9
circuits using gates for arbitrary functions.
3. Implementation of 4-bit binary 15
adder/subtractor circuits.
4. Implementation of code converters. 19
5. Implementation of BCD adder, encoder and 31
decoder circuits
6. Implementation of functions using 33
Multiplexers.
7. Implementation of the synchronous counters 38
8. Implementation of a Universal Shift register. 43
9. Simulator based study of Computer 47
Architecture

EXPT NO.: 01
VERIFICATION OF BOOLEAN THEOREMS USING LOGIC GATES.
DATE :

3
AIM:
To verify the Boolean Theorems using logic gates.

APPARATUS REQUIRED:
SL. NO. COMPONENT SPECIFICATION QTY.
1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. IC TRAINER KIT - 1
5. CONNECTING WIRES - As per required

THEORY:

BASIC BOOLEAN LAWS

1. Commutative Law
The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law
1. A+AB = A
2. A+AB = A+B

5. Involution (or) Double complement Law

1. A = A

6. Idempotent Law
1. A+A = A
2. A.A = A

4
7. Complementary Law
1. A+A' = 1
2. A.A' = 0
8. De Morgan’s Theorem
1. The complement of the sum is equal to the sum of the product of the individual
complements.

A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

5
Demorgan’s Theorem
a) Proof of equation (1):
Construct the two circuits corresponding to the functions A’. B’and (A+B)’ respectively. Show
that for all combinations of A and B, the two circuits give identical results. Connect these
circuits and verify their operations.

6
b) Proof of equation (2) :
Construct two circuits corresponding to the functions A’+B’and (A.B)’ A.B, respectively.
Show that, for all combinations of A and B, the two circuits give identical results. Connect
these circuits and verify their operations.

7
We will also use the following set of postulates:
P1: Boolean algebra is closed under the AND, OR, and NOT operations.
P2: The identity element with respect to • is one and + is zero. There is no identity
element with respect to logical NOT.
P3: The • and + operators are commutative.
P4: • and + are distributive with respect to one another. That is,
A • (B + C) = (A • B) + (A • C) and A + (B • C) = (A + B) • (A + C).
P5: For every value A there exists a value A’ such that A•A’ = 0 and A+A’ = 1.
This value is the logical complement (or NOT) of A.
P6: • and + are both associative. That is, (A•B)•C = A•(B•C) and (A+B)+C = A+(B+C).
You can prove all other theorems in boolean algebra using these postulates.

PROCEDURE:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to Vcc .
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.

RESULT:
Thus the above stated Boolean laws are verified.

8
EXPT NO.: 02 DESIGN AND IMPLEMENT HALF/FULL ADDER AND
SUBTRACTOR.
DATE :

AIM:
To design and construct half adder, full adder, half subtractor and full subtractor
circuits and verify the truth table using logic gates.

APPARATUS REQUIRED:
SL.NO. COMPONENT SPECIFICATION QTY.
1. AND GATE IC 7408 1
2. X-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
4. OR GATE IC 7432 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 23

THEORY:

HALF ADDER:
A half adder has two inputs for the two bits to be added and two outputs one from
the sum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Above circuit is
called as a carry signal from the addition of the less significant bits sum from the X-OR Gate
the carry out from the AND gate.

FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it
consists of three inputs and two outputs. A full adder is useful to add three bits at a time but
a half adder cannot do so. In full adder sum output will be taken from X-OR Gate, carry
output will be taken from OR Gate.

HALF SUBTRACTOR:
The half subtractor is constructed using X-OR and AND Gate. The half subtractor has
two input and two outputs. The outputs are difference and borrow. The difference can be
applied using X-OR Gate, borrow output can be implemented using an AND Gate and an
inverter.

FULL SUBTRACTOR:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor
the logic circuit should have three inputs and two outputs. The two half subtractor put
together gives a full subtractor .The first half subtractor will be C and A B. The output will be
difference output of full subtractor. The expression AB assembles the borrow output of the
half subtractor and the second term is the inverted difference output of first X-OR.

9
10
11
12
13
PROCEEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:
Thus, the half adder, full adder, half subtractor and full subtractor circuits are
designed, constructed and verified the truth table using logic gates .

14
EXPT NO.: 03
IMPLEMENTATION OF 4-BIT BINARY ADDER/SUBTRACTOR
DATE : CIRCUITS.

AIM:
To design and implement 4-bit adder and subtractor using basic gates and MSI
device IC 7483.

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY.

1. IC IC 7483 1
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 40

THEORY:

4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It
can be constructed with full adders connected in cascade, with the output carry from each
full adder connected to the input carry of next full adder in chain. The augends bits of ‘A’
and the addend bits of ‘B’ are designated by subscript numbers from right to left, with
subscript 0 denoting the least significant bits. The carries are connected in chain through the
full adder. The input carry to the adder is C0 and it ripples through the full adder to the
output carry C4.

4 BIT BINARY SUBTRACTOR:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data
input ‘B’ and the corresponding input of full adder. The input carry C0 must be equal to 1
when performing subtraction.

4 BIT BINARY ADDER/SUBTRACTOR:

The addition and subtraction operation can be combined into one circuit with one common
binary adder. The mode input M controls the operation. When M=0, the circuit is adder
circuit. When M=1, it becomes subtractor.

4 BIT BCD ADDER:

Consider the arithmetic addition of two decimal digits in BCD, together with an input carry
from a previous stage. Since each input digit does not exceed 9, the output sum cannot be
greater than 19, the 1 in the sum being an input carry. The output of two decimal digits
must be represented in BCD and should appear in the form listed in the columns.

15
ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2 decimal digits,
together with the input carry, are first added in the top 4 bit adder to produce the binary
sum.

PIN DIAGRAM FOR IC 7483:

4-BIT BINARY ADDER

LOGIC DIAGRAM:

4-BIT BINARY SUBTRACTOR:

16
LOGIC DIAGRAM:

4-BIT BINARY ADDER/SUBTRACTOR

LOGIC DIAGRAM:

17
PROCEDURE:
(i) Connections were given as per circuit diagram.
(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.

RESULT:
Thus the 4-bit adder and subtractor using basic gates and MSI device IC 7483 is
designed and implemented.

18
EXPT NO.: 04
IMPLEMENTATION OF CODE CONVERTERS.
DATE :

AIM:
To design and implement 4-bit
(i) Binary to gray code
converter
(ii) Gray to binary code
converter
(iii) BCD to excess-3 code
converter
(iv) Excess-3 to BCD code
converter
APPARATUS REQUIRED:
Sl.No.
COMPONENT
SPECIFICATION
19
QTY.
1.
X-OR GATE
IC 7486
1
2.
AND GATE
IC 7408
1
3.
OR GATE
IC 7432
1
4.
NOT GATE
IC 7404
20
1
5.
IC TRAINER KIT
-
1
6.
PATCH CORDS
-
35
THEORY:
The availability of large
variety of codes for the
same discrete elements of
information results in the use
of different codes by different
systems. A conversion circuit
21
must be inserted between
the two systems if each
uses different codes for
same
information. Thus, code
converter is a circuit that
makes the two systems
compatible
even though each uses
different binary code.
The bit combination assigned
to binary code to gray code.
Since each code uses
four bits to represent a decimal
digit. There are four inputs and
four outputs. Gray code is
22
a non-weighted code.
The input variable are
designated as B3, B2, B1, B0
and the output variables are
designated as C3, C2, C1, Co.
from the truth table,
combinational circuit is
designed. The
Boolean functions are obtained
from K-Map for each output
variable.
A code converter is a circuit
that makes the two systems
compatible even though
each uses a different binary
code. To convert from
23
binary code to Excess-3
code, the
input lines must supply the
bit combination of elements
as specified by code and the
output lines generate the
corresponding bit
combination of code. Each
one of the four
AIM:
To design and implement 4-bit
(i) Binary to gray code
converter
(ii) Gray to binary code
converter

24
(iii) BCD to excess-3 code
converter
(iv) Excess-3 to BCD code
converter
APPARATUS REQUIRED:
Sl.No.
COMPONENT
SPECIFICATION
QTY.
1.
X-OR GATE
IC 7486
1
2.
AND GATE
IC 7408
25
1
3.
OR GATE
IC 7432
1
4.
NOT GATE
IC 7404
1
5.
IC TRAINER KIT
-
1
6.
PATCH CORDS
-
26
35
THEORY:
The availability of large
variety of codes for the
same discrete elements of
information results in the use
of different codes by different
systems. A conversion circuit
must be inserted between
the two systems if each
uses different codes for
same
information. Thus, code
converter is a circuit that
makes the two systems
compatible
27
even though each uses
different binary code.
The bit combination assigned
to binary code to gray code.
Since each code uses
four bits to represent a decimal
digit. There are four inputs and
four outputs. Gray code is
a non-weighted code.
The input variable are
designated as B3, B2, B1, B0
and the output variables are
designated as C3, C2, C1, Co.
from the truth table,
combinational circuit is
designed. The
28
Boolean functions are obtained
from K-Map for each output
variable.
A code converter is a circuit
that makes the two systems
compatible even though
each uses a different binary
code. To convert from
binary code to Excess-3
code, the
input lines must supply the
bit combination of elements
as specified by code and the
output lines generate the
corresponding bit

29
combination of code. Each
one of the four
AIM:
To design and implement 4-bit
(i) Binary to gray code
converter
(ii) Gray to binary code
converter
(iii) BCD to excess-3 code
converter
(iv) Excess-3 to BCD code
converter
AIM:
To design and implement 4-bit
(i) Binary to gray code
converter
30
(ii) Gray to binary code
converter
(iii) BCD to excess-3 code
converter
(iv) Excess-3 to BCD code
converter
AIM:
To design and implement 4-bit
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY.

1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35

THEORY:

The availability of large variety of codes for the same discrete elements of
information results in the use of different codes by different systems. A conversion circuit
must be inserted between the two systems if each uses different codes for same
information. Thus, code converter is a circuit that makes the two systems compatible even
though each uses different binary code.

The bit combination assigned to binary code to gray code. Since each code uses four
bits to represent a decimal digit. There are four inputs and four outputs. Gray code is a non-
weighted code.

31
 The input variable are designated as B3, B2, B1, B0 and the output variables are
designated as C3, C2, C1, Co. from the truth table, combinational circuit is designed. The
Boolean functions are obtained from K-Map for each output variable.

A code converter is a circuit that makes the two systems compatible even though
each uses a different binary code. To convert from binary code to Excess-3 code, the input
lines must supply the bit combination of elements as specified by code and the output lines
generate the corresponding bit combination of code. Each one of the four maps represents
one of the four outputs of the circuit as a function of the four input variables.
A two-level logic diagram may be obtained directly from the Boolean expressions derived by
the maps. These are various other possibilities for a logic diagram that implements this
circuit. Now the OR gate whose output is C+D has been used to implement partially each of
three outputs.

BINARY TO GRAY CODE CONVERTOR

TRUTH TABLE:

32
33
34
35
36
37
38
39
40
41
PROCEDURE:
(i) Connections were given as per circuit diagram.
(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.

42
RESULT:
Thus the following 4-bit converters are designed and constructed.
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter

43
 AIM:
To design and implement 4-bit
adder and subtractor using IC
7483.
EXPT NO.: 05
IMPLEMENTATION OF BCD ADDER, ENCODER AND DECODER
DATE : CIRCUITS

AIM:
To design and implement BCD adder IC 7483.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. IC IC 7483 2
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7408 1
4. IC TRAINER KIT - 1
5. PATCH CORDS - Adequate

THEORY:

BCD ADDER:
BCD adder is a circuit that performs the addition of two BCD numbers in
parallel. BCD additions are performed in 4-bit binary form so there is a possibility of
increasing binary number greater than 9 that results wrong output. To avoid this, in BCD
addition correction logic I included as described below,
1. If the binary sum is equal or less than 9 with carry 0, then that binary sum is
correct BCD sum.
2. I the binary sum is equal or less than 9 with carry 1, then that binary sum is an
incorrect BCD sum. To get the correct BCD sum add 0110 with least significant
binary sum digits.
3. If the binary number is greater than 9, then that binary sum is an incorrect BCD
sum. To get the correct BCD sum add 0110 with binary sum digits.

BCD adder can be constructed with three blocks such as two binary adders and the
correction logic circuit. Initially in the BCD adders, the four bit binary numbers are added

44
using parallel binary adder and then, the binary output is checked to correct as BCD
number. The correction logic generates the correction code based on the binary output
values. When we get the incorrect binary output as per the condition described above, the
correction code is added with the binary output to get the correct BCD number through
second binary adder.

PROCEDURE:
1. Connections are made as per the circuit diagram.
2. Apply the logical Input data and verify the corresponding output.

TRUTH TABLE:

45
 APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. 3 I/P NAND GATE IC 7410 2

2. OR GATE IC 7432 3

3. NOT GATE IC 7404 1

2. IC TRAINER KIT – 1

4. PATCH CORDS – 27

RESULT:
Thus the BCD adder IC 7483 is designed and implemented.

EXPT NO.: 06
IMPLEMENTATION OF FUNCTIONS USING MULTIPLEXERS.
DATE :

AIM:
To design and implement the multiplexer and demultiplexer using logic gates and
study of IC 74150 and IC 74154.

APPARATUS REQUIRED:

46
 SL.NO. COMPONENT SPECIFICATION QTY.
1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32

THEORY:

MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a smaller
number of channels or lines. A digital multiplexer is a combinational circuit that selects
binary information from one of many input lines and directs it to a single output line. The
selection of a particular input line is controlled by a set of selection lines. Normally there are
2n input line and n selection lines whose bit combination determine which input is selected.

DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes
information from one line and distributes it to a given number of output lines. For this
reason, the demultiplexer is also known as a data distributor. Decoder can also be used as
demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The data
select lines enable only one gate at a time and the data on the data input line will pass
through the selected gate to the associated data output line.

47
48
49
50
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:
Thus the multiplexer and demultiplexer using logic gates are designed and
implemented.

51
EXPT NO.: 07
IMPLEMENTATION OF THE SYNCHRONOUS COUNTERS
DATE :

AIM:
To design and implement synchronous and asynchronous counter.

APPARATUS REQUIRED:

S.NO. NAME OF THE RANGE QUANTITY

APPARATUS
1. Digital IC trainer kit - 1
2. JK Flip Flop IC 7473 2
3. D Flip Flop IC 7473 1
4. NAND gate IC 7400 1
5. Connecting wires - As required

THEORY:
Asynchronous decade counter is also called as ripple counter. In a ripple counter the
flip flop output transition serves as a source for triggering other flip flops. In other words the
clock pulse inputs of all the flip flops are triggered not by the incoming pulses but rather by
the transition that occurs in other flip flops. The term asynchronous refers to the events that
do not occur at the same time. With respect to the counter operation, asynchronous means
that the flip flop within the counter are not made to change states at exactly the same time,
they do not because the clock pulses are not connected directly to the clock input of each
flip flop in the counter.

A counter is a register capable of counting number of clock pulse arriving at its clock
input. Counter represents the number of clock pulses arrived. A specified sequence of states
appears as counter output. This is the main difference between a register and a counter.
There are two types of counter, synchronous and asynchronous. In synchronous common
clock is given to all flip flop and in asynchronous first flip flop is clocked by external pulse
and then each successive flip flop is clocked by Q or Q output of previous stage. A soon the
clock of second stage is triggered by output of first stage. Because of inherent propagation
delay time all flip flops are not activated at same time which results in asynchronous
operation.

52
53
54
55
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:
Thus the synchronous and asynchronous counter are designed and implemented.

56
EXPT NO.: 08
IMPLEMENTATION OF A UNIVERSAL SHIFT REGISTER.
DATE :

AIM:
To design and implement the following shift registers
(i) Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in serial out
(iv) Parallel in parallel out

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 2
2. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 35

THEORY:
A register is capable of shifting its binary information in one or both directions is
known as shift register. The logical configuration of shift register consist of a D-Flip flop
cascaded with output of one flip flop connected to input of next flip flop. All flip flops
receive common clock pulses which causes the shift in the output of the flip flop. The
simplest possible shift register is one that uses only flip flop. The output of a given flip flop is
connected to the input of next flip flop of the register. Each clock pulse shifts the content of
register one bit position to right.

57
58
59
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:
The Serial in serial out, Serial in parallel out, Parallel in serial out and Parallel in
parallel out shift registers are designed and implemented.

60
EXPT NO.: 09
SIMULATOR BASED STUDY OF COMPUTER ARCHITECTURE
DATE :

AIM:
To write a study of simulator on computer architecture.

THEORY:

1 Simulator

The simulators that are described in this section are classified into single-processor
performance simulators (SimpleScalar [6], [57]), full-system simulators (Simics [69], [120]),
single-processor power consumption simulators (Wattch [12]), multiprocessor performance
simulators (RSIM [46], [95], [26]), and modular simulators (Liberty [111], [112], [113]).

1.1 SimpleScalar:

A Single-Processor Performance Simulator The SimpleScalar toolkit was initially

released in 1995 [6], while the latest version of SimpleScalar, version 3.0, was released in
1998. Since then, SimpleScalar has become one of the most popular simulators, if not the
most popular.

SimpleScalar consists of simulators and the tools that support the simulators (e.g., a
gcc compiler, its libraries, an assembler, and a linker). The different simulators have a wide
range of speed versus detail trade-offs.

Due to its level of detail, sim-outorder is usually the simulator of choice for
architects. This simulator models a superscalar processor with a five-stage pipeline.
Userconfigurable parameters include: the type/size of the branch predictor, the number of
load-store queue entries, and the cache configuration. One unique structure in simoutorder
is the register-update unit, which is a combination of the reorder buffer (ROB) and the
functional units’ reservation stations.

Version 4.0 of sim-outorder—called MASE (Micro Architectural Simulation

Environment) [57]—is currently under development. Its notable features include: 1) splitting
the RUU into a ROB and separate reservation stations, 2) a “checker” unit that verifies the
correct execution of the program to support speculation, and 3) a more realistic memory
interface.

Downloads and more information about SimpleScalar can be found at

http://www.simplescalar.com.

1.2 Simics:

Full-System Simulation Although processor simulators like SimpleScalar model the

microarchitecture, they do not model the entire system or run an operating system (OS).

61
Cain et al. [14] show that omitting the OS can produce errors as high as 100 percent in the
simulation results for the SPEC CPU 2000 benchmarks. To address these problems,
architects use full-system simulators that model the entire system in sufficient depth to run
the OS.

Simics is a full-system simulator that is available from Virtutech AB [69], [120]. Simics
supports a wide range of instruction sets, including Alpha, PowerPC, UltraSparc, and x86-64,
and includes device models, such as graphics cards, ethernet cards, and bus controllers, that
are detailed enough to run the actual device drivers. Also, Simics can boot and run
unmodified operating systems such as Linux, Solaris, and Windows XP. Simics’ more
interesting features include breakpoint and replay capabilities, support for program
checkpoints, and using Simics Central to simulate multiple processors on different physical
machines.
Simics includes three processor models that have different levels of simulation detail
and speed [120]. The fastest simulator models an in-order processor with singlecycle
execution latencies. The slowest simulator is a detailed out-of-order processor. With this
processor model, the user specifies a detailed timing model and how instructions should be
executed (e.g., how many instructions can be executed out-of-order and speculatively
executed). The third simulator is a scaled back version of the fully specified processor that
bypasses the user-visible API and reduces the number of instruction execution options [120]
to improve the simulation speed.

Downloads and more information about Simics can be found at

http://www.virtutech.com.

To reduce the development time of full-system simulators, Mauer et al. [73]

proposed timing-first simulation. Compared to conventional simulators, timing-first
simulators have several advantages. First, they have a lower development time since they
do not fully model all aspects of the system. Although the system is not fully modeled, their
timing-first simulator still executed 99.99 percent of all instructions correctly while incurring
a maximum error of 4.8 percent only. Second, since the functional part of simulator
constantly checks for correct program execution, errors that would normally cause a
conventional simulator to crash are detected and repaired. Third, by focusing on the timing
part of the simulator first, speculative execution is modeled more precisely.

Other well-known full-system simulations include: SimOS from Stanford [93], [94],
[126], Mambo from IBM [98], [102], and SimOS-Alpha from DEC [101].

1.3 Wattch:

A Single-Processor Power Consumption Simulator One of the limiting factors for

future processors is their power dissipation. To estimate a processor’s power consumption,
architects use simulators such as Wattch [12]. Wattch was developed at Princeton and is
based on sim-outorder, version 3.0. To calculate the power consumption for a component,
Wattch uses the formula: P =¼ C V2 dd a f, where C is the capacitance along all paths within
the component, Vdd is the supply voltage, a is the component’s internal switching activity,
and f is the clock frequency. The energy consumed each cycle is simply the sum of the

62
energy that was consumed by each component. Wattch models Vdd and f as constants since
they depend on the process technology. Wattch uses template formulas to calculate the
capacitance for four types of components: array structures (e.g., caches, etc.), fully
associative content addressable memory structures (e.g., ROB, LSQ, etc.), combinational
logic (e.g., functional units, etc.), and the clock distribution network. The amount of
switching activity is determined by monitoring the actual bit transitions within the
component during simulation. The results in [12] show that the distribution of energy
consumption across all major processor components is very close to that of the Pentium Pro
and the Alpha 21264, two processor architectures that are similar to the base Wattch
architecture.

Wattch can be downloaded from http://www.eecs. harvard.edu/~dbrooks/wattch-

form.html.

Although Wattch is the most widely used power consumption simulator [15], several
other simulators estimate the processor’s power consumption, including PowerTimer [13]
from IBM, SimWattch [15] from the USC, PowerAnalyzer [90] from Michigan, PowerImpact
from UCLA [91], and SimplePower [119] from Penn State. Of these simulators, SimWattch is
particularly interesting since it integrates a full-system simulator (Simics) with Wattch. This
is important since omitting operating system effects leads to overestimation of the
performance results while underestimating the power consumption results [15].

1.4 RSIM:

A Multiprocessor Performance Simulator RSIM—the Rice Simulator for ILP

Multiprocessors—was developed at Rice and released to the public in 1997 [46], [95], [26].
Key RSIM features include out-of-order issue, register renaming, branch prediction,
nonblocking caches, multiple cache-coherence protocols, and user configurable parameters
such as instruction window size, cache sizes and latencies, and flit size and delay [46].
Modeling ILPlevel (i.e., intraprocessor) features is important even when simulating
multiprocessor systems since these features may interact with thread-level (i.e.,
interprocessor) features. To illustrate this problem, Hughes et al. [46] evaluated the
performance of read miss clustering using RSIM and with a multiprocessor simulator that
did not model the ILP-level features. Their simulation results show that disregarding the ILP-
level features overestimates the execution time by as much as 132 percent. Even when
execution times were similar, ignoring the ILP-level features still overestimated the number
of cycles due to memory access. Finally, and perhaps worst of all, the results show that not
modeling ILP-level features could distort the simulation results to such a degree that the
architect would conclude that read miss clustering enhancement yields very little
performance improvement when it, in actuality, yields significant performance benefits.

Downloads and more information about RSIM can be found at:

http://rsim.cs.uiuc.edu.

Other multiprocessor simulators include: Talisman [8], Tango [23], a multiprocessor

version of SimpleScalar [70], Wisconsin Wind Tunnel II [80], Augmint [82], MINT [118],
GEMS [37], [71], and M5 [68].

63
1.5 Modular Simulators:

Although processors and systems are highly parallel, the simulators that model their
behavior are typically written with sequential programming languages. The consequences of
this parallel-to-sequential mapping are that the implementation and debugging of the
simulator can be very timeconsuming, its accuracy may suffer due to insufficient detail, and
component reuse is unlikely.

To minimize the effects of these problems, architects have proposed using modular
simulators such as the Liberty Simulation Environment (LSE) [111], [85], [112], [113].
Developed at Princeton, Liberty maps each hardware component to a single software
function; by instantiating those components and specifying its connections, architects can
hierarchically build more complex processor components. Hierarchically building processor
components has at least two key advantages. First, by building and testing lower-level
components hierarchically, the architect can easily build large libraries of accurate
components. Second, the architect can quickly and easily build a wide range of models,
which allows for efficient design space exploration and/or the examination of more unusual
architectures. To ensure that future components will seamlessly interface with current
components, the LSE stipulates the control interface between LSE components; in particular,
enable and ack handshaking signals are used to synchronize the data transfer between
components.

More information and downloads about the LSE can be found at

http://liberty.princeton.edu.

In addition to the LSE, other recent modular simulators include: Asim [35],
EXPRESSION [76], LISA [84], and Microlib [87].

RESULT:
Thus the basics of simulator in computer architecture was studied.

64