SPI:
SPI is a widely used communication interface found in microcontroller systems.
SPI operates as an internal protocol, facilitating synchronous communication
between a master device and a slave device. This protocol enables the
simultaneous exchange of data in a serial fashion. Throughout an SPI
transaction, data is both transmitted and received at the same time. The process
is synchronized by a serial clock that coordinates the shifting and sampling of
information on the two data lines. Additionally, a slave select line allows for the
individual designation of a specific slave SPI device, establishing
communication with the master in a serial mode.
TOP MODULE:
BLOCK DIAGRAM:
FUNCTIONALITY:
The top module is a synchronous serial controller that complies with both SPI
and microwire standards. It is controlled by registers that can be accessed using
WISHBONE technology from the host side. Overall, the SPI top module serves
as a central control unit for SPI communication, managing clock generation,
data transfer, and control signals. It interfaces with external devices,
orchestrating data exchange between the master and slave devices in the SPI
network.
SUB-BLOCKS
CLOCK GENERATOR MODULE:
BLOCK DIAGRAM:
wb_clk_in
wb_rst sclk_out
tip
CLOCK cpol_0
go
GENERATOR
last_clk cpol_1
divider
FUNCTIONALITY:
A clock signal generator is a circuit that produces a timing signal to
synchronize the operation of a system. The Serial Peripheral Interface (SPI)
communication protocol uses a clock generator. SPI is a synchronous data bus
that utilizes separate lines for data and a clock. The clock generates an
oscillating signal that keeps both sides in sync. SPI has four modes (0, 1, 2, 3)
that correspond to the four possible clocking configurations. The clock
transitions are responsible for the shifting and sampling of data. The default
setting for the SPI clock is SPI_CLOCK_DIV4, which sets the SPI clock to
one-quarter of the system clock frequency. For instance, on boards with a 16
MHz frequency, the SPI clock is set to 4 MHz.
WAVEFORMS:
SHIFT REGISTER MODULE:
BLOCK DIAGRAM:
l
p_in
rx_negedge
tx_negedge p_out
wb_clk_in
tip
wb_rst
go mosi
miso last
lsb SHIFT
sclk REGISTER
cpol_0
cpol_1
byte_sel
latch
len
FUNCTIONALITY:
To put it simply, the process of SPI operates like this: The data that needs to be
sent is loaded into either the master shift register or the slave shift register,
depending on whether it's a write or read operation. Then, the SPI controller
generates enough clocks to shift all the data bits from one shift register to the
other. Usually, the most significant bit (MSB) is the first one to be shifted out.
Both master and slave SPI peripherals have a shift register of 8 bits each
WAVEFORMS:
WISHBONE MASTER INTERFACE:
BLOCK DIAGRAM:
clk_in adr_o
rst_in
cyc_o
ack_in
stb_o
err_in
dat_in
WISHBONE we_o
MASTER dat_o
sel_o
FUNCTIONALITY:
The SPI core has five 32-bit registers through the WISHBONE compatible
interface. All accesses to SPI registers must be 32-bit (wb sel[3:0] = 0xf).
SLAVE MODULE:
BLOCK DIAGRAM:
sclk
miso
mosi SLAVE
ss_pad_o
FUNCTIONALITY:
The module includes four always blocks, each sensitive to the rising edge of the
clock signal (sclk). These blocks define the behavior of the module during clock
transitions. In summary, this SPI slave module is designed to operate within an
SPI communication system. It efficiently handles data reception and
transmission based on the clock signal and slave select conditions. The module
ensures that data is processed accurately and efficiently within the context of the
SPI protocol.
SPI DESIGN OUTPUT:
Define files:
To meet specific system requirements and size constraints on behalf of
the core functionality, the SPI Master core can be configured by setting
the appropriate define directives in the spi_defines.v source file. The
directives are as follows:
SPI DIVIDER_BIT_NB
This parameter defines the maximum number of bits needed for the
divider. Set this parameter accordingly to the maximum system
frequency and lowest serial clock frequency:
SPI DIVIDER_BIT_NB
Default value is 16.
SPI_MAX_CHAR
This parameter defines the maximum number of bits that can be
received/transmitted in one transfer. The default value is 64.
SPI_SS_NB
This parameter defines the number of slave select lines. The default
value is 8.
