FDI signal information

04 March 2024 15:06

1) lclk : The clock at which FDI operates.

2) lp_irdy : this signal indicate that protocol layer has potentially send the data to adapter and eventually lp_valid signal asserted than lp_irdy must be asserted and
protocol
layer wants to adapter that sample the data.
If pl_state_sts in reset status than lp-irdy is asserted for few clock and deasserted eventually.

3) lp_valid : this signal indicate that data is valid on the corresponding on lp_data bytes.

4) lp_data[NBYTES-1:0][7:0] : indicate protocol layer to adapter layer data,NBYTES indicates data width of FDI instance.

5) lp_retimer_crd : each and every 256B mainband data(flit,hdr,crc) single credit return to the retimer reciever buffer(adapter).
Retimer isnt present than this signal is not assert.

On FDI,this is an optional signal.Its permitted to have reciever buffer in protocol layer for raw mode,
if this is not exposed to protocol layer than adapter must track credit at 256B granularity even for raw format and return credit to PHY layer.

These UCIe D2D credits must be for flow control across the two UCIe Retimers and any data transmitted to the UCIe Retimer must eventually
be consumed by the remote UCIe die without any other dependency. Every UCIe Retimer must implement a Receiver Buffer for Flits that it
receives from the UCIe die within its package. The Receiver buffer credits are advertised to the UCIe die during initial parameter exchanges for
the D2D Adapter, and the UCIe die must not send any data to the UCIe Retimer if it does not have a credit for it. One credit corresponds to
256B of data (including any FEC, CRC, etc.).

When this is exposed on FDI, the Adapter must have the initial credits knowledge through other implementation specific means in order to
advertise this to the remote Link partner during parameter exchanges.

6) lp_corrupt_crc :
only applicable for CXL.cachemem and 256B flit mode where used for latency optimization and enable detection and containment of
poison or viral using adapter to corrupt crc of out-going flit.
PROTOCOL TO ADAPTER LAYER
For Standard 256B Flits, Protocol Layer asserts this along with lp_valid for the last chunk of the Flit that needs containment. Adapter corrupts CRC
for both of the 128B halves of the Flit which had this set. It also must make sure to overwrite this flit (with the next flit sent by the Protocol Layer) in
the Tx Retry buffer.

Only support 256B flit-format.

Standerd 256B flit(source CXL specs) : Last 16 bytes is used for CRC,HDR & FEC
7) lp_dllp[NDLLP-1:0] :
Protocol Layer to Adapter transfer of DLLP bytes. This is not used for 68B Flit Mode,CXL.cachemem or Streaming Protocols. For a 64B data path on lp_data, it is
recommended to assign NDLLP >= 8, so that 1 DLLP per Flit can be transferred fromthe Protocol Layer to the Adapter on average. The Adapter is responsible for
inserting DLLP into DLP bytes 2:5 if the Flit packing rules permit it. See Section 8.2.4.1 foradditional rules.
This is only support with cxl.io with 256B standard and Latancy opt.

as per this format compare with ucie 256B flit format,in ucie specs 256B flit format have in first 128B data consist first 2 byte flit header information and 126B flit
data.
Another 128B data consist 110B remaining flit data 4B(2:5Bytes)DLP bytes and 4B CRC and 10B reserved.

The Adapter is also responsible for indicating Optimized_Update_FC format by setting pl_dllp_ofc = 1 for the corresponding transfer on FDI.

DLLP transfer rules for 256B flit format :

Support only PCIe and CXL.io 256B Flits.
Separate signal for DLLP transfers from the Protocol Layer to Adapter and vice-versa.
Flit comes from protocol than this separate signal have responibilities to insert DLLP's into flits
retry buffer for NOP flits.
For TX side :
protocol layer is responsible for sending DLLP's at define rate to avoid timeout for DLLP exchange.
If protocol layer has no TLP's to send than it must insert NOP flits and adapter gets opprtunities to DLLP bytes.
For RX side:
Adapter must extract DLLP's from received flits from protocol and forward them to protocol.
Pl_dllp must be wide enough to keep with the max rate of DLLP's that could received from the link.

8) lp_dllp_valid : Indicates valid DLLP transfer on lp_dllp. DLLP transfers are not subject to backpressure by pl_trdy (the Adapter must have storage for different types of
DLLP and this can be overwritten so that the latest DLLPs are sent to remote Link partner). DLLP transfers are subject to backpressure by pl_stallreq -
Protocol Layer must stop DLLP transfers at DLLP Flit aligned boundary before giving lp_stallack or requesting PM.

9) lp_dllp_ofc :
This consider as DLLP bytes od lp_dllp follow the Optimized_Update_FC format.This pin must assert during entire of DLLP transfer.
10) lp_stream[7:0] : As per stream ID,indicate the different stack and protocol
i.e 00h = reserved
01h = stack 0 : PCIe …….. 14h : Stack 1 : Streaming protocol

11) pl_trdy : adapter is ready to accept the data and data is accep by adapter when lp_irdy,lp_valid and pl_trdy are asserted on posedge of clk.

12) Pl_valid : From protocol to adapter layer that data is valid on pl_data.

13) pl_data[NBYTES-1:0][7:0] : indicate adapter to protocol layer data ,NBYTES indicates data width of FDI instance.

14) lp_retimer_crd : Protocol to Adapter layer,

each and every 256B mainband data(flit,hdr,crc) single credit return to the retimer reciever buffer(adapter).
Retimer isnt present than this signal is not assert.

On FDI,this is an optional signal.Its permitted to have reciever buffer in protocol layer for raw mode,
if this is not exposed to protocol layer than adapter must track credit at 256B granularity even for raw format and return credit to PHY layer.

These UCIe D2D credits must be for flow control across the two UCIe Retimers and any data transmitted to the UCIe Retimer must eventually
be consumed by the remote UCIe die without any other dependency. Every UCIe Retimer must implement a Receiver Buffer for Flits that it
receives from the UCIe die within its package. The Receiver buffer credits are advertised to the UCIe die during initial parameter exchanges for
the D2D Adapter, and the UCIe die must not send any data to the UCIe Retimer if it does not have a credit for it. One credit corresponds to
256B of data (including any FEC, CRC, etc.).

When this is exposed on FDI, the Adapter must have the initial credits knowledge through other implementation specific means in order to
advertise this to the remote Link partner during parameter exchanges.

15) pl_dllp[NDLLP-1:0] : CXL.cachemem or Streaming Protocols. For a 64B data path on pl_data, it is recommended to assign NDLLP >= 8, so that 1 DLLP per Flit can be
transferred from the Adapter to the Protocol Layer, on average. The Adapter is responsible for extracting DLLP from DLP bytes 2:5 if a Flit Marker
is not present. The Adapter is also responsible for indicating Optimized_Update_FC format by setting pl_dllp_ofc = 1 for the corresponding
transfer on FDI.

16) pl_dllp_valid : Indicates valid DLLP transfer on pl_dllp. DLLPs can be transferred to the Protocol Layer whenever valid Flits can be transferred on pl_data. There is
no backpressure and the Protocol Layer must always sink DLLPs.

17) pl_dllp_ofc : Indicates that the corresponding DLLP bytes on pl_dllp follow the Optimized_Update_FC format. It must stay asserted for the entire duration of
the DLLP transfer on pl_dllp.

18) pl_stream[7:0] : Adapter to Protocol Layer signal that indicates the stream ID to use with data. Each stream ID maps to a unique protocol.

00h : Reserved
01h : Stack 0 : PCIe
02h : Stack 0 : CXL.io …….. 14h : Stack 1 : Streaming protocol Other encodings are Reserved.

19) pl_flit_cancel : Adapter to protocol layer that indicate to dump a flit.

Enable latancy opt on reciever data path when CRC checking enable.
N/A for raw format.
For standrd 256B format : fix clockcycle delay between assertion of this signal and last chunk of flit transfer.
For latancy .opt 256B format : Fix clock cycle delay between assertion of this signal and last chunk of 128B half flit transfer.

20) lp_state_req[3:0] : Protocol layer request to adapter layer to request state change.
Some of encodings are : NOP,ACTIVE,L1,L2,LINK RESET,RETRAIN,DISABLED.

21) lp_linkerror : Potocol layer to adapter indicate that an error has occurred which required link need go down.
Adapter must propogate this request to RDI to move the adapter LSM is to link error state and it must stay there as long as lp_linkerror=1.

22) pl_state_sts[3:0] : indicate status of state of adapter to protocol layer on the interface.
Some encodings are: RESET,ACTIVE,ACTIVE(PMNAK) NOP,ACTIVE,L1,L2,LINK RESET,RETRAIN,DISABLED.

23) pl_inband_pres : This signal is indicate that D2D link has finished to negotiation of perameter with remote link partner and is ready for LSM status to ACTIVE.
Once it transition to 1b it must stay in 1b until FDI moves to ACTIVE or Link-error.This statys asserted while FDI is in Retrain,ACTIVE.PMNAK,L1 or
L2. This signal must be de-assert during link_error,disable or link_reset state.

24) pl_error : Indicate to protocol that framing related error In case,this signal must asssert when pl_error was asserted on RDI and for a flit which the adapter is
forwarding to protocol layer. If retry is enable from adapter than in protocol layer pl_error considered as log correctable error.
Adapter must Link_retein on RDI following this,if it was a framing error detected by adapter.
25) pl_cerror : Protocol layer that indicate that correctable error detected and it doesnot affect the data path and will not cause retain on link.
Protocol layer must pl_cerror and pl_error for correctable error logging.
Adapter must or any internal error detect and it indicate on Rdi and forward to protocol layer.

26) pl_nferror : This n denotes for non fatal error, c denotes for correctable error,adapter indicate to protocol layer that non-fatal error was detected.
Adapter must or any internal error detect and it indicate pl_nferror on RDI and forward it to FDI.

27) pl_trainerror : This signal indicate that fatal error getting from adapter and adapter must transition pl_statte_sts to link_error if not already in link_error state.

28) pl_rx_active_req : Adapter assert this signal and request to protocol layer to open its receiver data path and get ready to receive protocol data or flits.Signal must
be assert when pl_state-sts must be in reset,active or retrain state.

29) lp_rx_active_sts : protocol layer responds to adapter that it is ready to receive protocol data or flits.

30) pl_protocol[2:0] : adapter indicate to protocol layer that protocol was negotiated during ttraining .
encoding are: PCIe,CXL.1 [Single protocol, i.e., CXL.io],CXL.2,CXL.3,CXL.4,streaming protocol.

31) pl_protocol_flitfmt[3:0] : This indicates the negotiate format.

encodings are : Raw Format,68B Flit Format,Standard 256B End Header Flit Format,Standard 256B Start Header Flit Format,Latency-
Optimized 256B without Optional Bytes Flit Format,Latency-Optimized 256B with Optional Bytes Flit Format

32) pl_protocol_vld : Indicate that pl_protocol and pl_protocol_flitfmt have valid information
The adapter must ensure that pl_inband_pres = 1,pl_state_sts = reset, pl_protocol_vld = 1 above all condition satisfied than pl_protocol_flitfmt
and pl_protocol are the correct value that can be sample by the protocol layer.

33) pl_stallreq : Adapter request the protocol that flush all flit for state transition and not prepare any new flits.

34) lp_stallack : protocol to adapter indication that flits are alligned and stalled.
strongly recommended response logic be on global free running clock .
So the Protocol Layer can respond to pl_stallreq with lp_stallack even if other significant portions of the Protocol Layer are clock gated.

35) pl_phyinrecenter : indicate that link doing train or retrain.

RDI has pl_phyinrecenter asserted or adapter's LSM is not moved In active state.

36) pl_phyinl1 : adapter indicate to protocol layer that physical layer is in L1 power management state(RDI is in L1 state)

37) pl_phyinl2 : adapter indicate to protocol layer that physical layer is in L2 power management state(RDI is in L2 state)

38) pl_speedmode[2:0] : current link speed :

encodings are : 4 GT/s - 32 GT/s
all module must operate with the same speed.
39) pl_lnk_cfg[2:0] : current link configuration .
encodings are : X8 - X256
Total width across all active module for the FDI instance

40) pl_clk_req : Request from adapter to protocol that remove clock gating from internal logic in protocol.
Together with lp_clk_ack, it forms a four way to enable dynamic clock gating in protocol layer.
If dynamic clock gating supported than protocol must use this signal to exit clock gating before responding lp_clk_ack
If dynamic clock gating isnt supported than for adapter it must be tied this signal to 1b.

41) lp_clk_ack : resp from the protocol to adapter that clk have been ungated in response of pl_clk_req .
This signal only asserted when pl_clk_req is asserted

42) lp_wake_req : request from protocol to adapter,that he remove clock gating from internal logic in adapter.
Together with pl_wake_ack,it forms a four way to enable dynamic clock gating in protocol layer.
If dynamic clock gating supported than protocol must use this signal to exit clock gating before responding pl_wake_ack.

43) pl_wake_ack : Resp from adapter to protocol layer that clk have been ungated in response of lp_wake_req .
This signal only asserted when lp_wake_req is asserted same as deasserted when lp_wake_req is deasserted.

44) pl_cfg[NC-1:0] : this is the sideband interface from adapter to protocol layer NC is denoted the width of the interface.
supported value 8,16,32
45) pl_cfg_vld : when it asserted ,indicated that pl_cfg has valid information receive to the protocol.
46) pl_cfg_crd : credit return for sb packets from adapter to protocol layer for sideband packet.
Each credit corresponds 64bytes header and 64bytes data.
additional information on ch-6

47) lp_cfg[NC-1:0] : this is the sideband interface from protocol to adapter layer NC is denoted the width of the interface.
supported value 8,16,32
48) lp_cfg_vld : when it asserted ,indicated that lp_cfg has valid information receive to the protocol.
49) lp_cfg_crd : credit return for sb packets from adapter to protocol layer for sideband packet.
Each credit corresponds 64bytes header and 64bytes data.
additional information on ch-6