COA - Sheet1 Answers
COA - Sheet1 Answers
Sheet 1
a. True
b. False
a. True
b. False
a.True
b. False
5. At a top level, a computer consists of CPU, memory, and I/O components.
a. True
b. False
6. Data processing from/to storages requires interaction with data movement apparatus
a. True
b. False
7. Interrupts do not improve processing efficiency.
a. True
b. False
8. Computer systems contain a number of different buses that provide pathways between
components at various levels of the computer system hierarchy.
a. True
b. False
9. The method of using the same lines for multiple purposes is known as time multiplexing.
a. True
b. False
10. Data communication is when data are received from or delivered to a device that
is directly connected to the computer.
a. True
b. False
11. Program Counter (PC) holds address of next instruction to fetch.
a. True
b. False
12. A key requirement for PCIe is high capacity to support the needs of higher data
rate I/O devices such as Gigabit Ethernet.
a. True
b. False
1. When data are moved over longer distances, to or from a remote device, the
process is known as __________.
a. data communications
b. registering
c. structuring
d. data transport
1. The most common classes of interrupts are: program, timer, I/O and
________.hardware failure
2. A __________ is a communication pathway connecting two or more devices.
BUS
3. The __________ is a popular high-bandwidth, processor-independent bus
that can function as a mezzanine or peripheral bus. PCI
4. The four main structural components of the computer are: main memory, I/O,
system interconnection, and __________. CPU
5. The _________ controls the operation of the CPU and hence the computer.
Control unit
7. List and briefly define two approaches to dealing with multiple interrupts.
• (1)Disable all interrupts while an interrupt is being processed.
• (2)Define priorities for interrupts and to allow an interrupt of higher
priority to cause a lower-priority interrupt handler to be interrupted
8. Discuss the CPU procedures to handle Pending Interrupt.
If interrupt is pending:
Interrupts
Disabled
Check for
Fetch Next Execute
START Interrupt;
Instruction Instruction Interrupts Process Interrupt
Enabled
HALT
Figurehas
Q5. The hypothetical machine 3.9two
Instruction Cycle with Interrupts
I/O instructions:
0011 Load AC from I/O
0011 Store AC to I/O
12-bit address identifies a particular I/O device. Show the program execution for the
following program:
1. Load AC from device 5.
2. Add contents of memory location 940.
3. Store AC to device 6.
Assume that the next value retrieved from device 5 is 3 and that location 940 contains
a value of 2.
Q6. Suppose we have two implementations of the same instruction set architecture.
Computer A has a clock cycle time of 250 ps and a CPI of 2.0 for some program, and
computer B has a clock cycle time of 500 ps and a CPI of 1.2 for the same program.
Which computer is faster for this program and by how much?
First, find the number of processor clock cycles for each computer:
CPU clock cyclesA=I×2.0 CPU clock cyclesB=I×1.2
Now we can compute the CPU time for each computer: CPU timeA=CPU clock cyclesA×Clock
cycle time=I×2.0×250ps=500×Ips
Likewise, for B: CPU timeB=I×1.2×500ps=600×Ips
Clearly, computer A is faster. The amount faster is given by the ratio of the execution times:
CPU performanceA/ CPU performanceB=Execution timeB /Execution timeA
=600×Ips500×Ips=1.2
We can conclude that computer A is 1.2 times as fast as computer B for this program.