1.

The Intel Microprocessors 8086 Architecture

Que. List Salient Features of 8086 microprocessor

1. It supports pipelined architecture and has two parallel processors i.e. the Bus interface unit
and the Execution unit.
2. Provides 20 bit address lines, so 1MB memory can be addressed.
3. Multiplexed 16 bit address and data bus AD0 –AD19 to minimize numbers of pin on IC.
4. Operating Clock frequencies are 5 MHz, 8 MHz, 10 MHz
5. Capable of executing about 0.33MIPS(Million Instruction per seconds)
6. Arithmetic operation can be performed on 8 bit or 16 bit signed and unsigned data including
division and multiplication.
7. Can operate in single processor and multiprocessor configuration i.e. operating modes.
8. Needs single +5v supply.
9. The instruction set is powerful, flexible and can be programmed in high level language like C
language.
10. Provides 256 types of vectored software interrupts.
11. Generate 8 bit of 16 bit I/0 addresses so it can access maximum 64 K devices.
12. Operate in maximum and minimum mode to achieve high performance level.
13. Supports 24 operands addressing modes.
14. It supports multiprogramming and floating point operation.
15. Provides separate instructions for string manipulation.
16. 8086 operates in two modes: a) Minimum Mode: A system with only one microprocessor.
b) Maximum Mode:-A system with multiprocessor.

Que. Draw and Describe the internal Architecture of 8086 microprocessor

Figure: Block diagram of 8086 architecture

The Internal Architecture of 8086 is divided in two parts: -
1. Bus interface unit (BIU)
2. Execution unit (EU)
Thus the works is divided between two functional units which speeds up processing
Bus interface unit: The main function of bus interface unit is to handle all bus related external
operations such as
1. Sends out address to I/O ports and memories.
2. Fetching instructions from memory.
3. Perform read/write operations from memory and I/O.
4. Supports pipelining.
i.e. it handles all address and data transactions for execution unit.
Execution unit: Execution unit carries out all the internal operations of decoding and executing. Both
BIU and EU work independent. Bus interface unit fetches the instruction in advance and stores them
in instruction queue. Execution unit takes the instructions from instruction queue and executes them.
Whenever execution unit needs communication with memory or I/O device, it requests to Bus
interface unit.
BIU consists of the following function units: -
1) Instruction Queue
2) Address calculation unit
3) Segment registers
4) Instruction pointer
Que. Describe the Concept of pipelining
Fetching the next instruction while the recent instruction executes is
known as pipelining. To speed up program execution, the Bus Interface
Unit fetches as many as 6 instruction bytes ahead of time from the
memory and these are held for execution unit in the (FIFO) group of
registers called QUEUE.
The BIU can be fetching instruction bytes while EU is decoding or
executing an instruction which does not require the use of buses. When
the EU is ready for the next instruction, it simply reads the instruction
from the QUEUE in the BIU. This is much faster than sending out
addresses to system memory and waiting for the memory to send back
the next instruction byte.
Fetching of next instruction while current instruction is executed is called as pipelining. This is there
to increase the operational speed.
Que. List the Segment registers and there use in 8086
Ans. BIU consists of four sixteen bit segment registers those are: -
1. Code segment register (CS)
2. Stack segment register (SS)
3. Extra segment register (ES)
4. Data segment register (DS)
The segment registers are used to store the upper 16-bit of starting address of four memory segments.
8086 BIU sends 20-bit address, so that it can address any of 1MB memory. However, at any given
time 8086/88 can work with 64KB segment within 1MB range.
1. Code segment register is used to store the 16-bit starting address for the program memory i.e
where code is stored.
2. The stack segment register SS is used to hold upper 16 – bit of the starting address for the program
stack.
3. The Extra segment register ES and data segment register DS are used to hold upper 16 – bit of two
memory segments used for data storage in memory.
Que. Describe the function and components of Execution unit
It consists of following functional parts: -
1. ALU, control circuitry and instruction decoder.
2. Flag registers
3. General purpose register
4. Pointer and indexing register
5. Scratch pad register (Temporary register)
ALU, control circuitry and instruction decoder: -The main function of ALU is to perform arithmetic
and logical operations like ADD, SUB, INR DCR, AND, OR, NOT. Instruction decoder decodes the
instruction and on basis of decoded instruction execution unit carries series of operations. To direct
control of operations of EU control circuitry is used.
Que. List and describe the general purpose Registers of 8086
Execution unit consists of four general purpose registers of 16-bit each, named as AX, BX, CX and
DX. These registers are also called as
AX – Accumulator
BX – Base registers
CX – Count Register
DX – Data Register (address register)
These registers can be used as: -
1. 8- 8 bits registers AH, AL, BH, BL, CH, CL, DH and DL. These registers can be used to store
both operands and results.
2. 4-16 bit register as AX, BX, CX and DX. These registers can be used to store address and data.
AX is called as accumulator. In addition to serving as arithmetic registers. It is used in I/O operation,
String operation, rotate and shift operation.
BX is can be used as base register for address calculation.
CX is used as counter. It is used as count register in string loop, rotate and shift instruction.
DX is used for storing I/O address during I/O operation.
When these registers are used as 8 bits register MSB is stored in AH and LSB is stored in AL register.
Same is the case with other registers.
Que. List and Describe Flag register in 8086
8086-processor status word consists of 16 bits, out of which 7 are not used. Each bit in processor
status word is called as flag. A flag is a flip-flop, which indicates some conditions generated by
execution of an instruction or to control certain operations of the execution unit. EU contains 9 active
flags. 8086 flags are grouped in two groups: -
(1) 6 - Status /Conditional flags
 (2) 3 -Control flags
Status/conditional flags are used to register the status of the latest arithmetic or logical operation
performed these flags are

Conditional Flags
Conditional flags represent result of last arithmetic or logical instruction executed. Conditional flags
are as follows:
1. CF (Carry Flag): - This flag indicates an overflow condition for unsigned integer arithmetic.
It is also used in multiple-precision arithmetic.
2. AF (Auxiliary Flag): - If an operation performed in ALU generates a carry/barrow from
lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AF flag is set i.e. carry given by
D3 bit to D4 is AF flag. This is not a general-purpose flag; it is used internally by the
processor to perform Binary to BCD conversion.
3. PF (Parity Flag): - This flag is used to indicate the parity of result. If lower order 8-bits of
the result contains even number of 1’s, the Parity Flag is set and for odd number of 1’s, the
Parity Flag is reset.
4. ZF (Zero Flag): - It is set; if the result of arithmetic or logical operation is zero else it is reset.
5. SF (Sign Flag): - In sign magnitude format the sign of number is indicated by MSB bit. If the
result of operation is negative, sign flag is set.
6. OF (Overflow Flag): - This stands for over flow flag. It occurs when signed numbers are
added or subtracted. An OF indicates that the result has exceeded the capacity of machine. It
becomes set if the sign result cannot express within the number of bites.
Control Flags
Control flags are set or reset deliberately to control the operations of the execution unit. Control flags
are as follows:
1. TF (Trap Flag): - It is used for single step control. It allows user to execute one instruction of
a program at a time for debugging. When trap flag is set, program can be run in single step
mode.
2. IF (Interrupt Flag): - It is an interrupt enable/disable flag. This stands for interrupt flag. This
flag is used to enable or disable the interrupt in a program. If it is set, the maskable interrupt
of 8086 is enabled and if it is reset, the interrupt is disabled. It can be set by executing
instruction sit and can be cleared by executing CLI instruction.
3. DF (Direction Flag): - This flag stands for direction flag and is used for the direction of
strings. If it is set, string bytes are accessed from higher memory address to lower memory
 address. When it is reset, the string bytes are accessed from lower memory address to higher
memory address.
Que. Describe the special purpose, index other Scratch pad registers of 8086 or Draw and
Describe Register Organization of 8086
The processor for storing temporary data and intermediate results uses these registers. These are not
accessible by instructions.
Pointers and index registers: -
1. Instruction pointer (IP)
2. Stack pointer (SP)
3. Base pointer (BP)
4. Source index registers (SI) and
5. Destination index register (DI)

Instruction Pointer: It is used to hold the 16 bits offset address of the next byte of the code to be
fetched from the memory. This offset is also called as displacement. This offset value is added to the
code segment register after shifting it by 4- bit.
Stack Pointer Register: The stack pointer register contains a 16-bit offset which when added to the
Stack Segment register indicates the address of the memory location where a word was most recently
stored. It holds the address of the stack in LIFO (Last in First Out) mode.
Base Pointer: Base pointer register is used for accessing the stack and may be used with other
registers. It holds the address of the stack in Random mode. The source index register, destination
register and base pointer register used for accessing or storing temporary data. Although SI and DI
can be used as individual registers but they are used with BX or BP.
The 20-bit physical Stack address can then be obtained by shifting the contents of the Stack
Segment register by 4 bits and adding the contents of BP to it.
Source Index Register: The source index register SI is used to load the 16-bit offset of a data word in
the Data Segment. The physical address of the data word can then be obtained shifting left the
contents of DS register by 4 bits and adding the contents of SI to it. It holds the offset address of
memory in indexed addressing mode. But it holds the offset address of source string in string.
Destination Index Register (DI): The Destination index register DI is used to hold the 16-bit offset
of a data word in the Extra Segment while executing string instructions. The 20-bit physical address
is then calculated from DS and DI. It holds the offset address of memory in indexed addressing mode.
But it holds the offset address of destination string in string. The above registers can also be used for
temporary storage of data just as other general-purpose registers.
Que. Describe the Physical Address is generated by Address generator in 8086

Fig. 20 bits physical address generator

1. Code segment register stores upper 16-bit address of program memory from where BIU will fetch
the current instruction.
2. BIU always inserts 0’s at lower nibble of code segment to make it 20 bits. Let CS = 384FH, then
the starting address of code segment will be 384F0H.
3. Then content of IP is added by address generator to the content CS to generate physical address
for the next instruction to be fetch from memory
4. The part of the segment starting address stored in a segment register is called as segment base
Example: CS = 1234, IP = 0120
12340 segment base address
0120 offset
12460 Physical address

Figure: segmented memory Figure: Physical Address Generation

Instruction pointer’s use to generate 20 bits physical address

Instruction pointer register holds 16-bit address of the next instruction to be fetched within code
segment. The value stored in IP is called as ‘offset’ or the ‘effective value’ because this 16-bit
value of the instruction pointer is added as an offset to code segment register in order to generate
20-bit physical address.
For example: -
If IP = 0123H & CS = 3000H, then
physical address will be calculated as: -
Base address: CS: 3 0 0 0 0 H
Effective address: IP: + 0 1 2 3 H
Physical address: 3 0 1 2 3 H
Therefore, Physical Address = CS +IP and
it is represented as CS: IP.
Similarly using DS, SS and ES address of
different segments are generated.

Que. Describe the Stack pointer’s use to generate 20 bits physical address
The 8086 allows us to set aside an entire 64 Kbytes segment as a stack. The upper 16-bit of the
starting address of this segment is loaded in the stack segment SS register. The stack pointer SP
register gives the 16-bit offset from the starting address of the segment where the word was most
recently stored on the stack. The memory location where a word was most recently stored in stack
segment is called as ‘top of stack’.
The physical address of the stack while reading or writing
the word is produced by adding the contents of the stack
pointer to the stack segment base register.
The content of SS stack base segment register is shifted
left by four bits. For example, assume SS contains 6000 H
and SP contains FFE0 H. The SS is shifted left four bits
position to give 60000 H. After adding SP i.e. offset in to
it, the resultant physical address for the top of the stack
will be 6FFEO H as shown in Figure. This can be
represented as SS:SP.
 Que. Draw the Pin diagram of 8086 and describe them in details.

The 8086 Microprocessor- Internal Architecture shows the details of internal architecture. Above
figure shows the logical pin diagram of 8086 microprocessor.
All the signals can be classified into six groups:
1. Power supply and frequency signals.
2. Clock signal
3. Address bus.
4. Data bus.
5. Mode selection.
6. Control and status signals.
7. Externally initiated signals, including interrupts.
1. Power supply and frequency signals: Vcc is on pin 40 supplies +5V power supply. Pin 1 and 20 for
ground reference.
2. Clock signal: Pin 19 for clock input (CLK): an 8086 requires a clock signal from some external,
crystal-controlled clock generator to synchronize internal operations in the processor with maximum
frequencies ranging from 5 MHZ to 10 MHZ.
3. Multiplexed address/data Bus: AD0 through AD15 are used at the start of machine cycle to send out
addresses and later in the machine cycle they are used to send or receive data. (This is also known as
multiplexing the bus.) However, the-low order address bus can be separated from these signals by
using a latch.
4. Multiplexed address bus: The 8086 has 4 signal lines A16/S3 through A19/S6. The double
mnemonic on these pins indicates that address bits A16 through A19 are sent out on these lines during
the first part of a machine cycle and the status information, which identifies the type of operation to
be done in that cycle, is sent out on these lines S3 through S6 during a later part of the cycle.
5. Mode selection: The operating mode of the 8086 is determined by the logic level applied to the
MN/MX input on pin 33. If pin 33 is asserted high, then the 8086 will function in minimum mode,
and pins 24 through 31 will have the functions shown in parentheses next to the pins i.e. INTA, ALE,
DEN, DT/R, M/IO, WR, HLDA, and HOLD. If the 8086 is in minimum mode in systems, it works as
a single microprocessor on the system buses.
If the MN/MX pin is asserted low, then the 8086 is in maximum mode. In this mode pins 24
through 31 will have the functions described by the mnemonics next to the pins i.e. QS1, QS0, S0,
S1, S2, LOCK, RQ/GT1, and RQ/GT0.
If the 8086 is in maximum mode in systems, it has two or more microprocessors sharing the same
buses and this mode is called multiprocessor mode.
6. Control and status signal: This group of signals is to identify the nature of the operations. These
signals are as follows.
a. ALE- Address Latch Enable (pin 25): this is a positive going pulse generated every time the
8086 begins an operation (machine cycle).This output signal indicates the availability of the
valid address is on the address/data lines.
b. RD (pin 32) Read: This is read control signal (active low). This signal indicates that the
selected I/O or memory device is to be read and data are available on the data bus.
c. WR (pin 29) Write: This is a write control signal (active low). This signal indicates that the
data on the data bus are to be written into a selected memory or I/O location.
d. M/IO (Pin 28): when it is high, reading from and writing to a memory location, and if it is
low, reading from and writing to a port.
e. S0, S1, S2 (pins 26, 27 and 28): These control bus signals are sent out encoded form of data
and an external bus controller device decodes these signals to produce the control bus signals
required for a system which has two or more microprocessors sharing the same buses.
f. DEN (pin 26) Data Enable signal: it is used to enable bidirectional buffers on the data bus,
when DEN is low. i.e. it send data out on the data bus and read the data in on the data bus.
g. DTR (pin 27) Data transmit/receive signal: when DTR is high, the 8086 is used to decide the
direction in which the buffers are enabled through the DEN the 8086 transmit the data to
ROM, RAM, or ports. When DTR is low, the buffers will allow data to come in from ROM,
RAM, and ports.
h. BHE/S7 (pin 34) Bus high enable: The bus high enable is used to indicate the transfer of
data over the higher order data bus if it goes low, the address that it will be writing to on AD0
- A19.
7. Interrupts and externally initiated signals:
a. NMI (Nonmaskable interrupt pin 17) and INTR (interrupt pin 18) input: A signal can be
applied to one of these inputs to cause the 8086 to interrupt the program it is executing and
go execute a specified procedure.
 b. HOLD input (pin 31): when the HOLD line is high, this signal indicates that a peripheral
such as a DMA (DMA Direct memory Access) controller is requesting the use of the address
and data buses.
c. HLDA (pin 30) Hold Acknowledge: This signal acknowledges the HOLD request.
d. READY input (pin 22): This signal is used to delay the microprocessor Read or Write cycles
until a slow responding peripheral is ready to send or accept data. When this signal goes low,
the microprocessor waits for an integral number of clock cycles until it goes high.
e. RESET (pin 21): This signal indicates that the MPU (microprocessor) is being reset. The
signal can be used to reset other devices.

What is the advantage of Memory Banking in 8086 processor? Justify with example.
The 8086 processor provides a 16-bit data bus. So It is capable of transferring 16 bits in one cycle
but each memory location is only of a byte (8 bits), therefore we need two cycles to access 16 bits
(8 bit each) from two different memory locations. The solution to this problem is Memory Banking.
Through Memory banking, our goal is to access two consecutive memory locations in one cycle
(transfer 16 bits).
The memory chip is equally divided into two parts(banks). One of the banks contains even
addresses called Even bank and the other contains odd addresses called Odd bank. Even bank
always gives lower byte So Even bank is also called Lower bank (LB) and Odd bank is also
called Higher bank (HB).
This banking scheme allows to access two aligned memory locations from both banks
simultaneously and process 16-bit data transfer. Memory banking doesn’t make it compulsory to
transfer 16 bits, it facilitates the 16-bit data transfer.
The choice between 8 bit and 16-bit transfer depends on the instructions given by the programmer.

Example:

The Least Significant bit of address (A 0 is not used for byte selection) is reserved for bank
selection. Therefore A 0=0 will select Even bank. The BHE signal is used for the selection of odd
banks. The processor will use a combination of these two signals to decide the type of data
transfer.

BH
E A0 types of Transfer
0 0 16-0bit data transfer from both HB and LB
 0 1 8-bit data transfer from HB
1 0 8-bit data transfer from LB
1 1 None (Idle)
In this case, the first machine cycle generates an odd address (A 0=1) transfer lower order 8 data bits
on a higher-order data bus. In the second machine cycle, the higher-order data bus will be
transferred to the lower-order data bus.
Advantages:
1. Improved Performance: Memory banking allows the microprocessor to access multiple
banks of memory simultaneously. This can improve the performance of memory-intensive
applications by reducing memory access times and increasing overall memory bandwidth.
2. Flexibility: Memory banking provides a flexible way to allocate and manage memory
resources. It allows the processor to allocate memory as needed, which can help reduce
memory wastage and improve overall system efficiency.
3. Cost-Effective: Memory banking can be a cost-effective way to increase the memory
capacity of a microprocessor. Instead of using expensive, high-density memory modules,
memory banking allows the use of multiple, smaller memory modules.
Disadvantages:
1. Increased Complexity: Memory banking adds complexity to the microprocessor design,
which can make it more difficult to implement and debug. Memory banking requires
additional hardware components, such as memory address decoders and control logic, which
can increase the cost and complexity of the microprocessor.
2. Latency: Although memory banking can improve memory performance, it can also
introduce latency. Memory banking requires additional memory address decoding and
control logic, which can increase memory access times and reduce overall system
performance.
3. Limited Applications: Memory banking is not suitable for all types of microprocessor
applications. It is primarily used in systems that require large amounts of memory, such as
high-performance computing and data center applications. In other applications, the added
complexity and cost of memory banking may not be worth the benefits.

Explain the minimum mode and maximum mode of 8086 microprocessor

 The 8086 microprocessor operates in minimum mode when MN/MX’ = 1.
 In minimum mode,8086 is the only processor in the system which provides all the control
signals which are needed for memory operations and I/O interfacing.
 Here the circuit is simple but it does not support multiprocessing.
 The other components which are transceivers, latches, 8284 clock generator, 74138 decoder,
memory and i/o devices are also present in the system.
 The address bus of 8086 is 20 bits long. By this we can access 2 20 byte memory i.e. 1MB .
Out of 20 bits, 16 bits A 0 to A15(or 16 lines) are multiplexed with a data bus.
  By multiplexing, it means they will act as address lines during the first T state of the
machine cycle and in the rest, they act as data lines. A 16 to A19 are multiplexed S3 to S6 and
BHE’ is multiplexed with S 7.

Control signals provided by 8086 for memory operations and i/o interfacing :
They are used to identifying whether the bus is carrying a valid address or not , in which direction
data is needed to be transferred over the bus, when there is valid write data on the data bus and
when to put read data on the system bus. Therefore, their sequence pattern makes all the operations
successful in a particular machine cycle.

Min mode circuit

8282 (8 bits) latch :

The latches are buffered D FF. They are used to separate the valid address from the multiplexed
Address/data bus by using the control signal ALE, which is connected to strobe (STB) of 8282. The
ALE is active high signal. Here three such latches are required because the address is 20 bits.
8286 (8 bits) transceivers:
They are bidirectional buffers and also known as data amplifiers. They are used to separate the
valid data from multiplexed add/data bus. Two such transceivers are needed because the data bus is
16 bits long. 8286 is connected to DT/R’ and DEN’ signals. They are enabled through the DEN
signal. The direction of data on the data bus is controlled by the DT/R’ signal. DT/R’ is connected
to T and DEN’ is connected to OE’.
 Direction of data flow

 8284 clock generator is used to provide the clock.

 M/IO’= 1,then I/O transfer is performed over the bus. and when M/IO’ = 0, then I/O
operation is performed.
 The signals RD’ and write WR’ are used to identify whether a read bus cycle or a write bus
cycle is performing. When WR’ = 0, then it indicates that valid output data on the data bus.
 RD’ indicates that the 8086 is performing a read data or instruction fetch process is
occurring. during read operations, one other control signal is also used, which is DEN (data
enable) and it indicates the external devices when they should put data on the bus.
 Control signals for all operations are generated by decoding M/IO’, RD’, WR’. They are
decoded by 74138 3:8 decoder.

 INTR and INTA:

When INTR = 1, then there is an interrupt to 8086 by other devices for their service. When
INTA’= 0, then it indicates that the processor is ready to service them.
 The bus request is made by other devices using the HOLD signal and the processor
acknowledges them using the HLDA output signal.
Timing diagram:
The working of min mode can be easily understood by timing diagrams.
 All processors bus cycle is of at least 4 T-states (T 1, T2, T3, T4). The address is given by
processor in the T1 state. It is available on the bus for one T-state.
 In T2, the bus is tristate for changing the direction of the bus (in the case of a data read cycle.)
 The data transfer takes place between T 3 and T4.
 If the addressed device is slower, then the wait state is inserted between T 3 and T4.

The working of minimum mode Opcode fetch or read timing diagram

 Opcode fetch or read timing diagram

 At T1 state ALE =1, this indicates that a valid address is latched on the address bus and also
M / IO’= 1, which indicates the memory operation is in progress.
 In T2, the address is removed from the local bus and is sent to the addressed device. Then the
bus is tristate.
 When RD’ = 0, the valid data is present on the data bus.
 During T2 DEN’ =0, which enables transceivers and DT/R’ = 0, which indicates that the data
is received.
 During T3, data is put on the data bus and the processor reads it.
 The output device makes the READY line high. This means the output device has performed
the data transfer process. When the processor makes the read signal to 1, then the output
device will again tristate its bus drivers.

The working of minimum mode Opcode fetch or read timing diagram

Write memory cycle

 At T1 state ALE =1, this indicates that a valid address is latched on the address bus and also
M / IO’= 1, which indicates the memory operation is in progress.
 In T2, the processor sends the data to be written to the addressed location.
 The data is buffered on the bus until the middle of T 4 state.
 The WR’=0 becomes at the beginning of T 2.
  The BHE’ and A0 signals are used to select the byte or bytes of memory or I/O word.
 During T2 DEN’ =0, which enables, transceivers and DT/R’ = 1, which indicates that the
data is transferred by the processor to the addressed device.

Explain the working of maximum mode.

 In this we can connect more processors to 8086 (8087/8089).
 8086 max mode is basically for implementation of allocation of global resources and passing
bus control to other coprocessor (i.e. second processor in the system), because two
processors cannot access system bus at same instant.
 All processors execute their own program.
 The resources which are common to all processors are known as global resources.
 The resources which are allocated to a particular processor are known as local or private
resources.

Maximum mode circuit

 When MN/ MX’ = 0, 8086 works in max mode.

 Clock is provided by 8284 clock generators.
 8288 bus controller- Address form the address bus is latched into 8282 8-bit latch. Three
such latches are required because address bus is 20 bits. The ALE (Address latch enable) is
connected to STB(Strobe) of the latch. The ALE for latch is given by 8288 bus
controllers.
 The data bus is operated through 8286 8-bit transceiver. Two such transceivers are required,
because data bus is 16-bit. The transceivers are enabled the DEN signal, while the direction
 of data is controlled by the DT/R signal. DEN is connected to OE’ and DT/ R’ is connected
to T. Both DEN and DT/ R’ are given by 8288 bus controllers.

Control signals for all operations are generated by decoding S’ 2, S’1 and S’0 using 8288 bus
controllers.

 Bus request is done using RQ’ / GT’ lines interfaced with 8086. RQ 0/GT0 has more priority
than RQ1/GT1.
 INTA’ is given by 8288, in response to an interrupt on INTR line of 8086.

 In max mode, the advanced write signals get enabled one T-state in advance as compared to
normal write signals.
Compare between minimum mode and maximum mode
Sr. Minimum mode Maximum mode
No.
1 MN/MX pin is connected to vcc. MN/MX pin is grounded.
2 Control signals M/IO, RD, WR are Control signals M/IO, WR, RD are not available
available on 8086 directly. on 8086 directly but status of the control signals
are available on status pins S0, S1, S2
3 Control signal such as IOR, IOW, Control signals such as MRDC, MWTC,
MEMW, MEMR can be generated AMWC, IORC, IOWC and AIOWC are
using control signals M/IO, RD, WR generated by bus controller 8288 using status
are available on 8086 directly. signals S0, S1 and S2.
4 No separate bus controller is required. Separate bus controller (8288) is required.
5 ALE, DEN, DT/R and INTA signals ALE, DEN, DT/R and INTA signals are not
are directly available. directly available and are generated by bus
controller 8288.
6 HOLD and HLDA signals are RQ/GT0 and RQ/GT1 signals are available to
available to interface another master interface another master in system such as DMA
in system such as DMA controller. controller and Co-processor 8087.
7 Status of the instruction is not a Status of the instruction queue is available on
available pins QS0 and QS1

Explain the interrupt structure of 8086 processor. [10]

An Interrupt Structure of 8086 can come from any one the three sources:

 External signal
 Special Instruction in the program
 Condition produced by instruction
External Signal (Hardware Interrupt):
An 8086 can get interrupt from an external signal applied to the nonmaskable interrupt (NMI) input
pin; or the interrupt (INTR) input pin.

Special Instruction:
Interrupt Structure of 8086 supports a special instruction, INT to execute special program. At the end
of the interrupt service routine, execution is usually returned to the interrupted program.

Condition Produced by Instruction:

An 8086 is interrupted by some condition produced in the 8086 by the execution of an instruction.
For example divide by zero: Program execution will automatically be interrupted if you attempt to
divide an operand by zero.

At the end of each instruction cycle 8086 Interrupts checks to see if there is any interrupt request. If
so, 8086 responds to the interrupt by performing series of actions (Refer Fig. 9.1).

1. It decrements stack pointer by 2 and pushes the flag register on the stack..
2. It disables the INTR interrupt input by clearing the interrupt flag in the flag
3. It resets the trap flag in the flag register.
4. It decrements stack pointer by 2 and pushes the current code segment register contents on the
stack.
5. It decrements stack pointer by 2 and pushes the current instruction pointer contents on the
stack.
6. It does an indirect far jump at the start of the procedure by loading the CS and IP values for the
start of the interrupt service routine (ISR).
An IRET instruction at the end of the interrupt service procedure returns execution to the main
program.