جامعة نينوى
كلية هندسة اإللكترونيات
HDL Programming
-VHDL- 2
Textbook: Volnei A. Pedroni, “Circuit Design with
VHDL”, MIT Press London, England, 2004.
Submitted By: Hussein M. H. Aideen
VHDL> Concurrent & sequential Code
Concurrent Code:
WHEN,
GENERATE,
Assignments using only operators (AND, NOT, +, *, sll,
etc.),
A special kind of assignment, called BLOCK.
Sequential Code:
PROCESSES, FUNCTIONS, PROCEDURES.
IF, WAIT, CASE, and LOOP.
VARIABLES.
VHDL>Combinational vs Sequential Logic
Combinational Logic: output depends solely on the
current inputs.
sequential logic: output depend on previous
inputs.
VHDL> Concurrent versus Sequential
VHDL code is inherently concurrent (parallel).
Only statements placed inside a PROCESS,
FUNCTION, or PROCEDURE are sequential.
the block, as a whole, is concurrent with any other
(external) statements.
Concurrent code is also called dataflow code.
Concurrent: The order does not matter.
VHDL> Concurrent Code
In summary, in concurrent code the following can be
used:
Operators;
The WHEN statement (WHEN/ELSE or
WITH/SELECT/WHEN);
The GENERATE statement;
The BLOCK statement.
VHDL> Concurrent Code
Operators: Operators are type of Concurrent code.
VHDL> Concurrent Code Examples
Multiplexer #1
VHDL> Concurrent Code
WHEN (Simple and Selected)
VHDL> Concurrent Code
Whenever WITH / SELECT / WHEN is used:
all permutations must be tested,
keyword OTHERS is often useful.
keyword UNAFFECTED,
which should be used when no action is to take place.
„„WHEN value‟‟ can indeed take up three forms:
VHDL> Concurrent Code
Examples:
VHDL> Concurrent Code
Multiplexer #2: when/else
VHDL> Concurrent Code
Multiplexer #2: with/select/when
VHDL> Concurrent Code
Tri-state Buffer:
VHDL> Concurrent Code
Home Works: Encoder: page 73:
VHDL> Concurrent Code
Home Works: ALU: page 75
VHDL> Concurrent Code
The GENERATE statement:
allows a section of code to be repeated a number of
times (loop).
GENERATE must be labeled.
limits of the range must be static.
VHDL> Concurrent Code
IF/GENERATE: (ELSE is not allowed).
IF/GENERATE can be nested inside FOR/GENERATE,
the opposite can also be done.
VHDL> Concurrent Code
Example:
VHDL> Concurrent Code
Vector Shifter:
the output vector must be a shifted version of the input
vector, with twice its width and an amount of shift
specified by another input.
VHDL> Concurrent Code
Vector Shifter:
VHDL> Concurrent Code
Vector Shifter:
VHDL> Concurrent Code
BLOCK:
Simple BLOCK
locally partitioning the code.
turning the overall code more readable (long
codes).
can be nested inside another BLOCK.
VHDL> Concurrent Code
Simple BLOCK:
VHDL> Concurrent Code
Nested BLOCK:
VHDL> Concurrent Code
Guarded BLOCK:
includes an additional expression, called
guard expression.
A guarded statement executed only when
the guard expression is TRUE.
sequential circuits can be constructed.
VHDL> Concurrent Code Example
DFF with Guarded BLOCK:
VHDL> Concurrent Code Example
Problem 5.2: Priority Encoder
din dout
First Binary
Second
Third 110
Fourth
Fifth
Sixth
Seventh
VHDL> Concurrent Code
Problem 5.2: Priority Encoder
VHDL> Concurrent Code
Problem 5.2: Priority Encoder
VHDL> Sequential Code
VHDL> Sequential Code
PROCESSES, FUNCTIONS, and PROCEDURES
are executed sequentially.
any of these blocks is still concurrent with any other
statements placed outside it.
with it we can build sequential circuits as well as
combinational circuits.
VHDL> Sequential Code
IF, WAIT, CASE, and LOOP.
VARIABLES restricted to be used in sequential code.
VHDL> PROCESS
A PROCESS must be installed in the main code.
executed every time a signal in the sensitivity list
changes.
VHDL> PROCESS
initial value is not synthesizable.
monitoring a signal (clock, for example) is necessary.
A common way of detecting a signal change is by
means of the EVENT attribute.
For instance, if clk is a signal to be monitored, then
clk‟EVENT returns TRUE when a change on clk
occurs (rising or falling edge).
VHDL> PROCESS
IF statement:
VHDL> IF statement
One-digit Counter #1
1-digit decimal counter (0 9 0).
VHDL> IF statement
One-digit Counter #1
1-digit decimal counter (0 9 0).
VHDL> IF statement
4 bit Shift Register:
VHDL> IF statement
4 bit Shift Register:
VHDL> WAIT statement
WAIT statement:
the PROCESS cannot have a sensitivity list when
WAIT is employed.
VHDL> WAIT statement
WAIT statement:
the PROCESS cannot have a sensitivity list when
WAIT is employed.
VHDL> WAIT statement
WAIT ON:
WAIT FOR is intended for simulation only (waveform
generation for testbenches). Example: WAIT FOR 5ns;
VHDL> WAIT statement
Home Works:
DFF with Asynchronous Reset #2, P99.
One-digit Counter #2, P99-100.
VHDL> CASE statement
CASE statement:
VHDL> CASE statement
CASE statement:
CASE statement (sequential) is very similar to WHEN
(combinational)
keyword OTHERS is often helpful.
Another important keyword is NULL (the counterpart
of UNAFFECTED), which should be used when no
action is to take place.
CASE allows multiple assignments for each test
condition.
VHDL> CASE statement
Two-digit Counter with SSD Output:
VHDL> Two-digit Counter with SSD
VHDL> Two-digit Counter with SSD
VHDL> Two-digit Counter with SSD
VHDL> Two-digit Counter with SSD
