‫جامعة نينوى‬

‫كلية هندسة اإللكترونيات‬

HDL Programming
-VHDL-
Textbook: Volnei A. Pedroni, “Circuit Design with
VHDL”, MIT Press London, England, 2004.

Submitted By: Hussein M. H. Aideen

VHDL> Introduction
 VHDL stands for VHSIC Hardware Description
Language.

 VHSIC is itself an abbreviation for Very High Speed

Integrated Circuits.

 Describes the behavior of an electronic circuit or

system, from which the physical circuit or system
can then be implemented.

 first HDL standardized, IEEE 1076 standard.

VHDL> Introduction
 Once the VHDL code has been written:
 used either to implement the circuit in a
programmable device (from Altera, Xilinx, Atmel, etc.)
 or can be submitted to a foundry for fabrication of an
ASIC chip.

 Currently, many complex commercial chips

(microcontrollers, for example) are designed using
such an approach.

 its statements are concurrent (parallel).

VHDL> Design Flow
VHDL> Design Flow
VHDL> Design Flow
VHDL> Code Structure
VHDL> Code Structure
LIBRARY declarations:
A LIBRARY is a collection of commonly used pieces of code.
Placing such pieces inside a library allows them to be reused
or shared by other designs.
VHDL> Code Structure
VHDL> Code Structure
An ENTITY is a list with specifications of all input and output
pins (PORTS) of the circuit. Its syntax is shown below.
 VHDL> Code Structure

 The mode of the signal can be:

 IN, OUT, INOUT, or BUFFER.
 IN and OUT are truly unidirectional pins,
 INOUT is bidirectional.
 BUFFER, output signal must read internally.

 The type of the signal can be BIT, STD_LOGIC,

INTEGER, etc. (discussed later).
 Finally, the name any name, except VHDL reserved
words
 VHDL> Code Structure
 The ARCHITECTURE is a description of how the circuit
should behave (function). Its syntax is the following:

 declarative part (optional), where signals and

constants are declared.

 the code part (from BEGIN down)

 VHDL> Introductory Examples
 DFF with Asynchronous Reset
 Exam: Q1) Write a VHDL code to synthesis the
following circuit (DFF with Asynchronous Reset)
shown in figure below:
 VHDL> Introductory Examples
 DFF with Asynchronous Reset
 VHDL is inherently concurrent (contrary to regular
computer programs, which are sequential),
 so to implement any clocked circuit (flip-flops, for
example) we have to „„force‟‟ VHDL to be sequential.
VHDL> Introductory Examples
 VHDL> Introductory Examples
 DFF plus NAND Gate
 Exam: Q2) Write a VHDL code to synthesis the
following circuit (DFF plus NAND Gate) shown in
figure below:
VHDL> Introductory Examples
 VHDL> Introductory Examples
 Home work 1
 Q3) Write a VHDL code for the circuit of figure P2.2.
Notice that it is purely combinational, so a PROCESS is
not necessary. Write an expression for d using only
logical operators (AND, OR, NAND, NOT, etc.).
Counter Test Bench
 Any digital circuit, no matter how complex, needs
to be tested. For the counter logic, we need to
provide a clock and reset logic. Once the counter
is out of reset, we toggle the enable input to the
counter, and check the waveform to see if the
counter is counting correctly. The same is done in
VHDL
Counter Test Bench
Testbench file
VHDL> Data Types
 Pre-Defined Data Types:
◦ BIT (and BIT_VECTOR): 2-level logic („0‟, „1‟).
VHDL> Data Types
VHDL> Data Types
 STD_LOGIC (and STD_LOGIC_VECTOR):
8-valued logic system introduced in the IEEE
1164 standard.
◦ „X‟ Forcing Unknown (synthesizable unknown)
◦ „0‟ Forcing Low (synthesizable logic „1‟)
◦ „1‟ Forcing High (synthesizable logic „0‟)
◦ „Z‟ High impedance (synthesizable tri-state buffer)
◦ „W‟ Weak unknown
◦ „L‟ Weak low
◦ „H‟ Weak high
◦ „–‟ Don‟t care
VHDL> Data Types
VHDL> Data Types
 BOOLEAN: True, False.

 INTEGER: 32-bit integers

(from -2,147,483,648 to +2,147,483,647).

 NATURAL: Non-negative integers

(from 0 to +2,147,483,647).
 SIGNED and UNSIGNED: data types defined in the
std_logic_arith package of the ieee library. They have the
appearance of STD_LOGIC_VECTOR, but accept
arithmetic operations, which are typical of INTEGER data
types.
 REAL: Real numbers ranging
from -1.0E38 to +1.0E38. Not synthesizable.

 Physical literals: Used to inform physical quantities, like

time, voltage, etc. Useful in simulations. Not synthesizable.
VHDL> Data Types
 Examples:
VHDL> Data Types
 Examples:
VHDL> Data Types
Ex: Write VHDL code to design 8-3 encoder (use if statement)
VHDL> Data Types
 User-Defined Data Types:
 VHDL also allows the user to define his/her
own data types.
VHDL> Data Types
VHDL> Data Types
 Sub-Types:
 The main reason for using a subtype rather than specifying a new type is
that, though operations between data of different types are not allowed,
they are allowed between a subtype and its corresponding base type.
VHDL> Data Types
 Signed and Unsigned Data Types:
◦ defined in the std_logic_arith package of the ieee library.
VHDL> Data Types
 VHDL> Data Conversion
 VHDL does not allow direct operations between data of
different types.
 it is necessary to convert data from one type to another.

 If the data are closely related: std_logic_1164 of the

ieee library provides straightforward conversion
functions.
 VHDL> Data Conversion
 Data conversion functions: std_logic_arith package of
the ieee library.
keyword Input data type Output data type

conv_integer(p) INTEGER, UNSIGNED, INTEGER

SIGNED, or
STD_ULOGIC
conv_unsigned(p, b) INTEGER, UNSIGNED, UNSIGNED
SIGNED, or * Where b is number of bits.
STD_ULOGIC

conv_signed(p, b): INTEGER, UNSIGNED, SIGNED

SIGNED, or
STD_ULOGIC

conv_std_logic_vector(p, b) INTEGER, UNSIGNED, STD_LOGIC_VECTOR

SIGNED, or
STD_ULOGIC
 VHDL> Data Conversion
 Data conversion functions: std_logic_signed or
std_logic_unsigned package of the ieee library.
keyword Input data type Output data type

unsigned(p) STD_LOGIC_VECTOR UNSIGNED

signed(p): STD_LOGIC_VECTOR SIGNED

VHDL> Data Conversion
 Example:
 VHDL> Examples:
 A 4-bit adder:
 VHDL> Examples:
 A 4-bit adder:
VHDL>Static and non-static data
 CONSTANT:
 establish default values
 can be declared in a PACKAGE, ENTITY, or
ARCHITECTURE.
VHDL>Static and non-static data

 GENERIC:
 specifying a generic parameter (that is, a static
parameter ).
 code more flexibility and reusability.
 must be declared in the ENTITY.
VHDL>Static and non-static data

 SIGNAL:
 pass values in and out the circuit, as well as between its
internal units.
 circuit interconnects (wires).
VHDL>Static and non-static data

 VARIABLE:
 represents only local information.
 It can only be used inside a sequential code (PROCESS
for example).
VHDL>Static and non-static data
VHDL> Operators

 VHDL provides several kinds of pre-defined

operators:
 Assignment operators
 Logical operators
 Arithmetic operators
 Relational operators
 Shift operators
 Concatenation operators
VHDL> Operators

 Assignment operators

Operator using

<= SIGNAL.

:= VARIABLE, CONSTANT,
GENERIC,
initial values.
=> vector elements or with
OTHERS.
VHDL> Operators

 Assignment operators
VHDL> Operators
 Logical operators:
 perform logical operations.
 Data types: BIT, STD_LOGIC, STD_ULOGIC,
BIT_VECTOR, STD_LOGIC_VECTOR, or
STD_ULOGIC_VECTOR

 NOT
 AND
 OR
 NAND
 NOR
 XOR
 XNOR
VHDL> Operators

 Arithmetic Operators:
 perform arithmetic operations
 data types: INTEGER, SIGNED, UNSIGNED, or
REAL
 With std_logic_signed or std_logic_unsigned
package: STD_LOGIC_VECTOR.
VHDL> Operators
 N bit adder circuit:
VHDL> Operators
 N bit adder circuit:
VHDL> Operators

 Comparison Operators:
 Used for making comparisons.
 Data types: any.
VHDL> Operators
N bit comparator:
VHDL> Operators
VHDL> Operators

 Shift Operators:

 Syntax:
VHDL> Data Attributes
 The pre-defined, synthesizable data attributes are the
following:
 d‟LOW: Returns lower array index
 d‟HIGH: Returns upper array index
 d‟LEFT: Returns leftmost array index
 d‟RIGHT: Returns rightmost array index
 d‟LENGTH: Returns vector size
 d‟RANGE: Returns vector range
 d‟REVERSE_RANGE: Returns vector range in
reverse order
VHDL> Data Attributes
VHDL> Signal Attributes
 Let us consider a signal s. Then:
 s‟EVENT: Returns true when an event occurs on s.
 s‟STABLE: Returns true if no event has occurred on s.
VHDL> User-Defined Attributes
 VHDL also allows the construction of user defined
attributes.
VHDL> Examples
 Generic Parity Detector:
 The circuit must provide output = „0‟ when the number
of „1‟s in the input vector is odd, or output = „1‟
otherwise.
VHDL> Examples
 Generic Parity Detector:
temp input
0 1
0
1
1
XOR 0
1 1
1
0
VHDL> Examples
 Generic Parity Generator:
 The circuit must add one bit to the input vector (on its
left).
 Such bit must be a „0‟ if the number of „1‟s in the input
vector is even, or a „1‟ if it is odd, such that the resulting
vector will always contain an even number of „1‟s (even
parity).
VHDL> Examples
 Generic Parity Generator:

input temp2
1 1
0 0
1 1
1 1
0 0
1 1
1 1
0
temp1
0
VHDL> Examples
 Generic Decoder:
 If ena = „0‟, then all bits of x should be high; otherwise,
the output bit selected by sel should be low.
VHDL> Examples
 Generic Decoder: