ASIC design LAB

Assignment-4 (23MVD0024)
Objective:
To perform floor planning, placement and clock tree synthesis on given design

Aim:
 Perform floor planning on synthesised netlist using icc2 tool
 Perform placement
 Perform clock tree synthesis

Server:
Synopsys server (10.10.5.29)
Tool:
ICC2

Steps:
 Here for floor planning “ndm” (new data model) libraries are used
 Write script file for data preparation
 Source data preparation script to icc2 using GUI mode console window or by
command prompt
 Save the block
 Write script file for floor planning and run command to put macros into the design
 Define the boundaries and shape of die and place macros inside block
 Write macros file and close icc2 editor
 Source created TCL file, now we will have only macros inside die
 Run commands for placement of I/O pins
 Run commands for placement of power rails
 Then place standard cells inside die
 Write script for legalized placement and source it
 Write script for clock tree synthesis and source it

1) Data preparation:
Script:

####### Setting Up Target & Link Libraries #############

source ./1_common_setup.tcl

####### Creating library of the block ########

set link_library $LINK_LIBRARY_FILES

set target_library $TARGET_LIBRARY_FILES

create_lib -ref_libs $NDM_REFERENCE_LIB_DIRS -technology $TECH_FILE ./lib1

 ASIC design LAB

#read netlist
read_verilog ../rtl1/report1/ChipTop1_netlist.v

#set current design -top level module name

current_design ChipTop1

#linking library + netlist

link

save_lib -as post_import_design

#defining attributes for metal layers -- HVH (preferable) or VHV

define_user_attribute -type string -name routing_direction -classes routing_rule

#for horizontal
set_attribute -objects [get_layers {M1 M3 M5 M7 M9}] -name routing_direction -value
horizontal

#for vertical
set_attribute -objects [get_layers {M2 M4 M6 M8 MRDL}] -name routing_direction -value
vertical

#reading TLU+ file ---max file

#read_parasitic_tech -tlup
/home/synopsys/SAED14nm_EDK/tech/star_rc/max/saed14nm_1p9m_Cmax.tluplus -
layermap /home/synopsys/#SAED14nm_EDK/tech/star_rc/saed14nm_tf_itf_tluplus.map -
name worst_para

#reading TLU+ file ---max file

read_parasitic_tech -tlup "${DESIGN_REF_PATH}/tech/saed32nm_1p9m_Cmax.lv.tluplus"
-layermap "${DESIGN_REF_PATH}/tech/saed32nm_tf_itf_tluplus.map" -name worst_para

#reading TLU+ file ---min file

read_parasitic_tech -tlup "${DESIGN_REF_PATH}/tech/saed32nm_1p9m_Cmin.lv.tluplus"
-layermap "${DESIGN_REF_PATH}/tech/saed32nm_tf_itf_tluplus.map" -name best_para

#min file
#read_parasitic_tech -tlup
/home/synopsys/SAED14nm_EDK/tech/star_rc/min/saed14nm_1p9m_Cmin.tluplus -
layermap /home/synopsys/#SAED14nm_EDK/tech/star_rc/saed14nm_tf_itf_tluplus.map -
name best_para

source -e -v ./3_mcmm.tcl
save_block -as import_done
save_lib
 ASIC design LAB
GUI mode snapshot:

2) Floor plan:
Script:
# SANITY CHECK
#
check_netlist
check_timing
report_design_mismatch -verbose

#########################

initialize_floorplan -side_ratio {1 1} -core_offset {1}

# PLACE PINS
set_block_pin_constraints -self -allowed_layers {M3 M4} -sides 2
place_pins -ports [get_ports -filter direction==out]
set_block_pin_constraints -self -allowed_layers {M3 M4} -sides 4
place_pins -ports [get_ports -filter direction==in]

#placing macros
create_placement -floorplan

set_app_option -name time.disable_recovery_removal_checks -value false

set_app_option -name time.disable_case_analysis -value false

# fix the ports

set_attribute [get_ports *] physical_status fixed
get_attribute [get_ports *] is_fixed
 ASIC design LAB
#ADD END CAP cells
set_boundary_cell_rules -top_boundary_cells saed14rvt_tt0p8v125c/SAEDRVT14_CAPT2
-bottom_boundary_cells saed14rvt_tt0p8v125c/SAEDRVT14_CAPB2 -right_boundary_cell
saed14rvt_tt0p8v125c/SAEDRVT14_CAPBIN13 -left_boundary_cell
saed14rvt_tt0p8v125c/SAEDRVT14_CAPBTAP6 -prefix endcap

compile_targeted_boundary_cells -target_objects [get_voltage_areas]

check_legality -cells [get_cells bound*]

#check_legality -cells [get_cells tap*]

save_block -as floorplan_done

#
# ---------Power Plan script starts------------

## create the PG nets

create_net -power VDD
create_net -ground VSS

## Making Logical Connections

connect_pg_net -net VDD [get_pins -hierarchical "*/VDD"]
connect_pg_net -net VSS [get_pins -hierarchical "*/VSS"]

## Setting up the attribute for TIE cells

set_attribute [get_lib_cells */*TIE*] dont_touch false
set_lib_cell_purpose -include optimization [get_lib_cells */*TIE*]

### creating PG Rails

create_pg_mesh_pattern P_top_two -layers { { {horizontal_layer: M9} {width: 0.12}
{spacing: interleaving} {pitch: 4.8} {offset: 1.6} {trim : true} } { {vertical_layer: M8}
{width: 0.12} {spacing: interleaving} {pitch: 4.8} {offset: 1.6} {trim : true} } }

set_pg_strategy S_default_vddvss -core -pattern { {name: P_top_two} {nets:{VSS VDD}}

} -extension { {{stop:design_boundary_and_generate_pin}} }

compile_pg -strategies {S_default_vddvss}

#### Creating Standard cell rails

create_pg_std_cell_conn_pattern std_rail_conn1 -rail_width 0.094 -layers M1

set_pg_strategy std_rail_1 -pattern {{name : std_rail_conn1} {nets: "VDD VSS"}} -core

compile_pg -strategies std_rail_1

#### Creation of Vias b/w rails and PG straps

#create_pg_vias -nets {VDD VSS} -from_layers M1 -to_layers M9 -drc no_check

# Check physical Connectivity of PG nets

 ASIC design LAB
check_pg_connectivity

#Check for DRC errors in the design,

check_pg_drc

### saving block

save_block -as powerplan_done

GUI mode snapshots:

After establishing boundary for die:

After inserting I/O pins:

 ASIC design LAB
After adding standard cells:

After adding power rails:

 ASIC design LAB

3) Placement:
Script:
check_design -checks pre_placement_stage

set_app_options -name place.coarse.continue_on_missing_scandef -value true

##placement density setting

set_app_options -name place.coarse.max_density -value 0.6

#Specify a maximum utilization that controls how densely the tool can place cells in less
congested areas that surround highly congested areas, so
#that the cells in the congested areas can be spread out to reduce the congestion
set_app_options -name place.coarse.congestion_driven_max_util -value 0.6

#to analyze all cells have proper or legal location

analyze_lib_cell_placement -lib_cells *
#for placement of cells
create_placement -floorplan

#set RC delay for timings which were set during "DATA PREPARATION"
set_parasitic_parameters -early_spec best_para
set_parasitic_parameters -late_spec worst_para

check_legality -verbose

legalize_placement

#TIMING REPORT
report_qor -summary

### setting VTH percentage

 ASIC design LAB

analyze_design_violations
#for OPTIMIZATION
place_opt -to final_opto
save_block -as placement_done
#TIMING REPORT
report_qor -summary > ./qor.rpt
report_timing > ./timing.rpt

Legalized placement:

4) Clock tree synthesis:

Script:
#Before performing CTS, execute the following command and analyze the report
check_design -checks pre_clock_tree_stage
# set NDR
create_routing_rule clk_rule -widths {M6 0.112 M7 0.112 } -spacings {M6 0.112 M7
0.112 }

#check_clock_tree

# specify clock tree cell list

set_lib_cell_purpose -exclude cts [get_lib_cells]
#set_lib_cell_purpose -include cts [get_lib_cells
"saed14rvt_tt0p8v125c/SAEDRVT14_BUF_S_4
saed14rvt_tt0p8v125c/SAEDRVT14_BUF_S_6
saed14rvt_tt0p8v125c/SAEDRVT14_BUF_S_8"]

set_lib_cell_purpose -include cts [get_lib_cells

"saed32_rvt|saed32_rvt_std/NBUFFX2_RVT saed32_rvt|saed32_rvt_std/NBUFFX4_RVT
saed32_rvt|saed32_rvt_std/NBUFFX8_RVT saed32_rvt|saed32_rvt_std/NBUFFX16_RVT"]
 ASIC design LAB

#Specify Max fanout

set_app_options -name cts.common.max_fanout -value 30

# set clock target skew and latency

set_clock_tree_options -clocks [all_clocks] -target_latency 0.050 -target_skew 0.030
#set_clock_tree_options -clocks [get_clocks -filter "is_virtual==false"] -target_latency 0.25
-target_skew 0.03

set_clock_routing_rules -clocks [all_clocks ] -net_type {internal} -rules clk_rule -

min_routing_layer M6 -max_routing_layer M7
set_clock_routing_rules -clocks [all_clocks ] -net_type {root} -rules clk_rule -
min_routing_layer M6 -max_routing_layer M7

clock_opt

# Make the logical connection of PG nets for all the standard cells

connect_pg_net -net VDD [get_pins -hier * -filter "name == VDD"]

connect_pg_net -net VSS [get_pins -hier * -filter "name == VSS"]

save_block -as cts_done

report_constraints -all_violators
report_clock_tree_options
report_clock_qor
report_qor -summary
report_timing -delay_type min
report_timing -delay_type max

Post CTS GUI snapshot:

 ASIC design LAB

Final inside view of die:

Timing report:
 ASIC design LAB
qor report:

Inference:
In this assignment whole backend flow is carried out on given Chiptop design using icc2 tool.
This flow includes data preparation, floor planning, placement and clock tree synthesis
processes. In this report output of running the script at individual steps are included. After
performing clock tree synthesis there are some violations present in the design which will be
removed later.