STUDY MATERIAL

ON
MICROPROCESSORS AND
MICROCONTROLLERS
 UNIT-1
Introduction to 8 bit microprocessor
Fundamentals for Microprocessor
Computer is of two types based on processing of information.

➢ Analog computer
➢ Digital computer

What is an analog computer?

An analog computer is a programmable machine which makes processing of information in
terms of analog signals.

What is a digital computer?

➢ A digital computer is a programmable machine which makes processing of information in
terms of digital numbers.

Block diagram of a digital computer

➢ The main components of a digital computer are

CPU (Central processing Unit)
Input device
 Memory
Output Device
CPU (Central processing Unit): A central processing unit (CPU) is an important part of
every computer and is used for execution of program.
Input device: The input device is used to provide programs and data to the computer.

Examples: Keyboard, Mouse, Scanner, Microphone, Bar Code Reader, Optical Mark Reader
(OMR) etc

Memory: Memory is a storage device which is used to store programs, datas and results.
Output Device: Output devices are used to display the results according to the
instruction given to the computers.
Examples- Monitors, projectors, speakers, headphones and printers etc.

What is a microcomputer?
A digital computer in which one microprocessor has been provided to act as a CPU is called as
microcomputer.

Block diagram of a digital computer

Examples: Desktop computers

Laptops
Notebook
What is a multiprocessor computer system?
A computer whose CPU contains more than one microprocessor is called a
multiprocessor computer system.
Example: High-end powerful server, supercomputers

What is a microprocessor?
➢ When the central processing unit is fabricated on a single IC is called as microprocessor.
➢ Micro means very small, as the processor is very small in size so it is called as
microprocessor.
Examples: 4004µP, 8085µP, 8086µP, 80286µP, 80386µP, 80486µP, Pentium etc.

Word length of a computer or microprocessor

➢ A word length refers to the basic data size or bit size that can be processed by the
processor.
➢ The word length of a computer or microprocessor is represented as n-bit. Where n may be
4, 8,16,32,64 etc.
➢ A processor of longer word length is more powerful and can process data at faster speed
as compared to a processor of shorter word length.

Units of memory
➢ The smallest unit of memory is bit which can store the binary digits 0 or 1.
➢ The combination of 4 bits is called as 1 nibble.
➢ The combination of 8 bits is called as 1 Byte=2 nibble.
➢ 1 KB=210Bytes=1024 bits
➢ 1MB=220 Bytes=210KB=1024 KB
➢ 1GB=230Bytes=210MB=220KB
➢ 1TB=240Bytes=210GB=220MB=230KB

Evolution of microprocessors

➢ The first microprocessor was developed by Intel corporation in the year of 1971 and its
name is Intel 4004
➢ It is a 4bit microprocessor i.e the word length/word size is 4 bit.
➢ It is fabricated using p-MOS technology.
Opcodes and operands:
➢ Each instruction has two parts i.e operation code (opcode) and operands.
➢ Opcode specifies the task to be performed
➢ Operand is the data in which the operation is performed.
➢ Operand can be of 8-bit or 16 bit data, 8bit or 16 bit address, resisters etc.

Example:

1. MVI A, 45H->45H data immediately move to the accumulator.

Here MVI is the opcode and A and 45H are the operands.

2. MOV A,B->The content of register B will move to the register A.

Here MOV is the opcode and A and B are the operands.

3. STA 4500H->Store the content of register A in 4500H address.

Here STA is opcode and 4500H is the operand.

 8085 microprocessor
Features of 8085 microprocessor:-
It has the following features:
➢ It is a 8-bit microprocessor because the length of its data bus is 8-bit i.e. it can
perform the operation on datas whose maximum size is 8-bit.

➢ The length of address bus is 16-bit

So the maximum address memory capacity of the processor is

216=65536Bytes=64KB

➢ The range of address memory of 8085 microprocessor is 0000H to FFFFH.

➢ It has 40 pins and fabricated using n-MOS technology.

➢ It has a program counter (PC) whose length is 16 bit.

➢ It has a stack pointer(SP) whose length is 16 bit

➢ Six 8-bit registers arranged in pairs: BC, DE, HL

➢ It requires +5V DC supply voltage for its operation.

➢ Its clock frequency is 3 MHZ.
➢ It has 80 basic instructions and 246 opcodes(Operation code).

Applications of 8085 microprocessor

It is used in Washing machines, Microwave ovens Mobile phones, etc.

Bus organization of 8085 microprocessor

What is a Bus?
➢ Bus is a group of conducting wires which carries information.
➢ All the peripherals are connected to microprocessor through Bus.

Types of Bus
There are three buses in a microprocessor as shown in the figure.
(i)Address Bus
(ii)Data Bus
(iii)Control Bus
Address Bus:-
➢ It is a group of conducting wires which carries address only.
➢ Address bus is unidirectional because data flow in one direction, from microprocessor to
memory or from microprocessor to Input/output devices.
➢ Length of Address Bus of 8085 microprocessor is 16 Bit (That is, Four Hexadecimal Digits),
ranging from 0000 H to FFFF H, (H denotes Hexadecimal). The microprocessor 8085 can transfer
maximum 16 bit address which means it can address 65, 536 different memory location.

Data Bus:-

➢ It is a group of conducting wires which carries Data only.

➢ Data bus is bidirectional because data flow in both directions, from microprocessor to
memory or Input/output devices and from memory or Input/output devices to
microprocessor.
➢ Length of Data Bus of 8085 microprocessor is 8 Bit (That is, two Hexadecimal Digits),
ranging from 00 H to FF H. (H denotes Hexadecimal).

Control Bus:-
➢ It is a group of conducting wires, which is used to generate timing and control signals to
control all the associated peripherals,
➢ Some control signals are:
 • Memory read
• Memory write
• I/O read
• I/O Write
• Opcode fetch

Architecture of 8085 microprocessor

8085 microprocessor consists of the following main functional units

(a)Arithmetic and logic Unit (ALU):

(b)Timing and control unit

(c)Registers
(d)Serial Input Output Control unit

(e)Interrupt Control Unit-

(f)Address bus and data bus

(a)Arithmetic and logic Unit (ALU):

As the name suggests, it performs arithmetic and logical operations like Addition, Subtraction, logical
AND, logical OR, etc. on 8-bit data.

(b)Timing and control unit

It generates timing and control signals which are necessary for the microprocessor to perform
operations. Following are the timing and control signals, which control external and internal
circuits.

• Control Signals: READY, RD’, WR’, ALE

• Status Signals: S0, S1, IO/M’
• DMA Signals: HOLD, HLDA
• RESET Signals: RESET IN, RESET OUT

(c)Registers:

Registers are used by the microprocessor to store datas and instructions temporarily. So it is a
temporarily storage device.

General purpose register

➢ There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each
register can hold 8-bit data.
➢ The combination of two 8-bit registers is known as register pair. The valid register pairs
are B-C, D-E & H-L.The register pairs can hold 16 bit data.
➢ The H-L register pair is called as memory pointer.

Program counter

➢ It is a 16-bit special-purpose register

➢ It is used to store the memory address location of the next instruction to be executed.
➢ Microprocessor increments the content program counter during the execution of an
instruction so that the program counter points to the memory address of the next
instruction that is going to be executed.

Temporary register

It is an 8-bit register which is not available to the programmer, but It is used by the
microprocessor internally for execution of some operations.

Instruction register and decoder

It is an 8-bit register. When an instruction is fetched from memory then it is stored in the
Instruction register. Instruction decoder decodes the information present in the Instruction
register.
Flag register/Program Status word (PSW):

➢ It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending
upon the result stored in the accumulator.
➢ These are the set of 5 status flags.

1. Sign (S)

2. Zero (Z)

3. Auxiliary Carry (AC)

4. Parity (P)

5. Carry (C)

➢ The status flags are shown as in the figure.

All of the status flags are set or reset according to the stored result in the accumulator or register A.

1. Sign(S)-This flag is used to know whether the number is positive or negative after the ALU
operation.
➢ If B7 of the result is 1 then sign flag is set, So the number is negative.
➢ If B7 of the result is 0 then sign flag is reset, So the number is positive.

Example:

2. Zeros (Z)-If the result after the ALU operation is zero then this flag is set otherwise it is reset.
Example:
3. Auxiliary carry(AC)-During the ALU operation if a carry is generated from B3 to B4 bit then this
flag is set otherwise reset.
Example:

4. Parity (P)-
➢ If the result stored in the accumulator after the ALU operation contains even number of
1’s then this flag is set
➢ If the result stored in the accumulator after the ALU operation contains odd number of
1’s then this flag is reset

Example:

5. Carry(C)-

During the ALU operation if a carry is generated from B7 to B8 bit then this flag is set otherwise
reset.
Example:

(d)Serial Input Output Control-

There are two pins in this unit. This unit is used for serial data communication.

SID-Serial input datas

SOD-Serial output datas

(e)Interrupt Control Unit-

➢ As the name suggests it controls the interrupts during a process.

➢ When a microprocessor is executing a main program and whenever an interrupt occurs,
the microprocessor shifts the control from the main program to process the incoming
request. After the request is completed, the control goes back to the main program.
 ➢ There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5, RST 5.5,
and TRAP.
➢ Generally INTA is used for acknowledgement.

(f)Address bus and data bus

➢ Data bus carries the data to be stored. It is bidirectional and length is 8 bit.
➢ Address bus carries the location to where it should be stored. It is unidirectional and
length is 16 bit
Instruction word Size
The computer or microprocessor is able to understand the instructions which are written in the
binary form or machine code form. But the length of all the instructions is not same. According
to the length, the instructions are divided in 3 types

(a) 1 Byte instructions

(b) 2 Byte instructions
(c) 3 Byte instructions

1 Byte instructions

In the 1 Byte instructions, only the instruction code or opcode is present which specifies that
the operation performed by the microprocessesor as well as the register present.

Example: (i) MOV A, B

(ii) ADD B
(iii) HLT

2 Byte instructions

In the 2 Byte instructions, the 8 bit data is present in the instruction itself.

Example: (i) MVI B,95

(ii) ADI 32

3 Byte instructions

In the 3 Byte instructions, the 16 bit address is present in the instruction itself.

Example: (i) STA 4602

(iii) LDA 4602

 Addressing Modes of 8085 microprocessor.

What is addressing mode?

➢ The process of specifying the datas in to an instruction is called as addressing modes.

➢ The 8085 has the following five types of addressing mode:
I. Immediate addressing mode
II. Direct addressing mode
III. Register addressing mode
IV. Register Indirect addressing mode
V. Implicit addressing mode

Immediate Addressing:
In this mode, the operand given in the instruction - a byte or word – transfers to the destination
register or memory location.
Ex: MVI A, 9AH
➢ The operand is a part of the instruction.
➢ The operand is stored in the register mentioned in the instruction.

Direct Addressing:
Memory direct addressing moves a byte or word between a memory location and register. The
memory location address is given in the instruction.
Ex: LDA 850FH
➢ This instruction is used to load the content of memory address 850FH in the accumulator.
Register Direct Addressing:
Register direct addressing transfer a copy of a byte or word from source register to destination
register.
Ex: MOV B, C
It copies the content of register C to register B.
Register Indirect Addressing:
Indirect addressing transfers a byte or word between a register and a memory location.
Ex: MOV A, M
➢ Here the data is in the memory location pointed to by the contents of HL pair. The data is
moved to the accumulator.
Implicit Addressing
Implicit Addressing In this addressing mode the data itself specifies the data to be operated upon.
Ex: CMA
➢ The instruction complements the content of the accumulator. No specific data or operand
is mentioned in the instruction.
 SIGNAL DESCRIPTIONS/PIN CONFIGURATION OF 8085 MICROPROCESSOR

➢ 8085 is a 40 pin IC, The signals from the pins can be grouped as follows

1. Power supply and Clock frequency signals

2. Address Bus
3. Data bus
4. Control signals
5. Status Signals
6. Interrupts and Externally initiated operations
7. Reset Signals
8. Direct Memory Access (DMA) Signals.
9. Single Bit Serial I/O ports

1. Power supply and Clock frequency signals

Vcc:+5voltpowersupply
Vss:Ground
X1,X2 : It is used to set the frequency of internal clock generator. Since the basic operating
timing frequency is 3 MHz.
 CLK (output)-Clock Output is used as the system clock for peripheral and devices interfaced
with the microprocessor.

2. Address Bus

A8 - A15:
It carries the most significant 8 bits(higher 8 bit ) of the memory address or the 8 bits of the
I/O address.

3. Data bus

AD0 - AD7

➢ These are called as multiplexed address and data lines

➢ These multiplexed set of lines used to carry the lower order 8 bit address as well as data
bus.
➢ The CPU may read or write out data through these lines.

4. Control Signals

ALE (Address Latch Enable)

➢ It is an output signal used to give information of AD0-AD7 contents..

➢ When this signal goes high it indicates that AD0-AD7 are address.
➢ When this signal goes low it indicates that AD0-AD7 are data.

RD (READ)

➢ Read memory or IO device.

➢ This indicates that the selected memory location or I/O device is to be read and
that the data bus is ready for accepting data from the memory or I/O device

WR (WRITE)
➢ Write memory or IO device.
➢ This indicates that the data on the data bus is to be written into the selected
memory location or I/O device.

IO/M (Select memory or an IO device).

➢ This signal indicates that the read / write operation relates to whether the memory
or I/O device.
➢ If this signal goes HIGH then the operation is an I/O operation.
➢ If this signal goes LOW then the operation is an I/O operation.
5. Status Signals:

➢ It is used to know the type of current operation of the microprocessor.

➢ The status signal S1 & S0 indicate the type of operation as shown in the table

SL NO S1 S0 OPERATION
1 0 0 HLT
2 0 1 WRITE
3 1 0 READ
4 1 1 FETCH

6. Interrupts and externally initiated operations:

Interrupt signals

➢ There are five hardware interrupts called

TRAP
RST 7.5
RST 6.5
RST 5.5
INTA

➢ They are the signals initiated by an external device to request the microprocessor to do a
particular task or work.
➢ On receipt of an interrupt, the microprocessor acknowledges the interrupt by the INTA
(Interrupt Acknowledge) signal.

7. Reset Signals:

Reset In
➢ This signal is used to reset the microprocessor.
➢ The program counter inside the microprocessor is set to zero.
Reset Out
➢ It indicates CPU is being reset.
➢ Used to reset all the connected devices when the microprocessor is reset.

8. Direct Memory Access (DMA) signals:

➢ When two or more devices are connected to a common bus, to prevent the devices from
interfering with each other, the tristate gates are used to disconnect all devices except the one
that is communicating at a given instant.
➢ Direct Memory Access(DMA) operation is used for large volume data transfer between memory
and an I/O device directly.
 HOLD

➢ HOLD signal is generated by the DMA controller circuit. It indicates that another device is
requesting to use the address and data bus

HLDA

➢ It is a signal which indicates that the hold request has been received.

READY

➢ This signal indicates that the device is ready to send or receive data.

9. Single Bit Serial I/O ports:

These signals are used for serial communication.

SID - Serial input data line

SOD - Serial output data line
 Interrupts in 8085
What is an Interrupt?
➢ Interrupts are the signals that are sent by the external devices to the microprocessor to
perform a particular task or work in request format.
➢ There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.

Types of Interrupts
Interrupt are classified into following groups based on their parameter −

• Vector interrupt − In this type of interrupt, the interrupt address is known to the
processor.

For example: RST7.5, RST6.5, RST5.5, TRAP.

• Non-Vector interrupt − In this type of interrupt, the interrupt address is not known to
the processor so, the interrupt address require to send externally by the device to perform
interrupts.

For example: INTR.

• Maskableinterrupt − In this type of interrupt, you can neglect the interrupt by giving
some instructions to the program.

For example:RST7.5, RST6.5

• Non-Maskable interrupt − In this type of interrupt, interrupts cannot be disabled by

writing some instructions into the program.

For example: TRAP.

• Softwareinterrupt−

➢ The software interrupts can be treated as CALL instructions with default call
locations.
➢ Software interrupt is special kind of interrupt which programmer can use as an
instruction.
➢ There are 8 software interrupts in 8085.
 • Hardware interrupt –

➢ In 8085 microprocessor have five hardware interrupts.

➢ Now for unlike software interrupt hardware interrupt has own priority level.

Note − INTA is not an interrupt, it is used by the microprocessor for sending acknowledgement.
TRAP has the highest priority, then RST7.5 and so on.

TRAP

It is called as a non-maskable interrupt, which has the highest priority among all interrupts. It is
subroutine calls which are forced by the microprocessor when it identifies any interruption in the
instructions. Bydefault, it is enabled until it gets acknowledged. So, when the power failure
occurs, it executes as ISR and sends the data to backup memory. This interrupt transfers the
control to the location 0024H.
RST7.5

It is called as maskable interrupt, which has the second highest priority among all interrupts.
When this interrupt is executed, the processor saves the content of the PC register into the stack
and branches to 003CH address.

RST 6.5

It is a maskable interrupt, having the third highest priority among all interrupts. When this
interrupt is executed, the processor saves the content of the PC register into the stack and
branches to 0034H address.

RST 5.5

It is a maskable interrupt. When this interrupt is executed, the processor saves the content of the
PC register into the stack and branches to 002CH address.

INTR

It is a maskable interrupt, having the lowest priority among all interrupts. It can be deleted by
resetting the microprocessor.

When INTR signal goes high, the following events can occur −

• The status of INTR signal is being checked by the microprocessor during the execution of
each instruction.
• When the INTR signal is high, then the microprocessor finishes its current instruction and
sends active low interrupt acknowledge signal.
• When instructions are received, then the microprocessor saves the address of the next
instruction on stack and the received instruction is executed.

What is Interrupt Service Routine (ISR)?

(CONTROL FLOW OF ISR)
 STACK AND SUBROUTINES
What is a stack?
➢ A stack is a group of memory locations in the memory that is used for temporary storage
of information during the execution of a program.

➢ The stack is a Last in Fast out (LIFO) structure i.e the element which will be inserted last
in to the stack will be removed first.
➢ The stack normally grows backwards into memory.i.e the programmer defines the bottom
of the stack and the stack grows up into reducing address range
➢ The starting memory location (Stack top) of the stack is defined in the main program.
➢ The stack pointer is defined by the following instruction
LXI SP, 4700H
Here: 4700H is the stack top address.
Instructions related to stack:
The programmer can perform the operation on the stack using the following two instructions.
PUSH: It is used to put data on to the stack
POP: It is used to get data from stack
Syntax of PUSH Instruction:
PUSH rp
Here rp:is the register pair
Comments: The content of specified register pair is inserted or pushed on to the stack.
Example:

LXI SP 4799H
LXI H 4257H
PUSH H

Line-1: LXI SP 4799H

Instillation of stack top address as 4799H.

Line-2: LXI H 4257H

Loaded the value 4257H in to H-L register Pair.
 Line-3: PUSH H

When instruction PUSH H is executed, the following sequence of data transfer takes
place.
1. The stack pointer is decremented by one to 4798H and the content of the higher byte of
register pair (H) is copied in to the stack memory location 4798H.
2. The stack pointer register is again decremented by one to 4797H and the content of the
lower byte of register pair is copied in to the stack memory location 4797H.

Syntax of PUSH Instruction:

POP rp
Here rp:is the register pair
Comments: The content of stack is retrieved in to the specified register pair.
Example:
LXI SP 4700H
LXI H 4257H
PUSH H
POP H

Timing Diagram

Timing Diagram is a graphical representation. It represents the execution

time taken by each instruction in a graphical format. The execution time is
represented in T-states.

Instruction Cycle:

The time required to execute an instruction is called instruction cycle.

Machine Cycle:

The time required to access the memory or input/output devices is called

machine cycle.

T-State:

✓ The machine cycle and instruction cycle takes multiple clock periods.
✓ A portion of an operation carried out in one system clock period is called as
T-state.


1 Machine cycles of 8085

The 8085 microprocessor has 5 (seven) basic machine cycles. They are

✓ Opcode fetch cycle (4T)

✓ Memory read cycle (3 T)
✓ Memory write cycle (3 T)
✓ I/O read cycle (3 T)
✓ I/O write cycle (3 T)
Signal 1.Opcode fetch machine cycle of 8085 :
 ✓ Each instruction of the processor has one byte opcode.
✓ The opcodes are stored in memory. So, the processor executes the opcode
fetch machine cycle to fetch the opcode from memory.
✓ Hence, every instruction starts with opcode fetch machine cycle.
✓ The time taken by the processor to execute the opcode fetch cycle is 4T.
✓ In this time, the first, 3 T-states are used for fetching the opcode from
memory and the remaining T-states are used for internal operations by the
processor.

2. Memory Read Machine Cycle of 8085:

✓ The memory read machine cycle is executed by the processor to read a data
byte from memory.
✓ The processor takes 3T states to execute this cycle.

The instructions which have more than one byte word size will use the machine
cycle after the opcode fetch machine cycle.
Cycle 3. Memory Write Machine Cycle of 8085

✓ The memory write machine cycle is executed by the processor to write a data
byte in a memory location.
✓ The processor takes, 3T states to execute this machine cycle.

4. I/O Read Cycle of 8085

✓ The I/O Read cycle is executed by the processor to read a data byte from I/O
port or from the peripheral, which is I/O, mapped in the system.

✓ The processor takes 3T states to execute this machine cycle.
✓ The IN instruction uses this machine cycle during the execution.

Cycle 1.4.2 Timing diagram for STA 526AH

 ✓ STA means Store Accumulator -The contents of the accumulator is stored in
the specified address (526A).

 ✓ The opcode of the STA instruction is said to be 32H. It is fetched from the
memory 41FFH (see fig). - OF machine cycle

✓ Then the lower order memory address is read (6A). - Memory Read Machine
Cycle
✓ Read the higher order memory address (52).- Memory Read Machine Cycle

✓ The combination of both the addresses are considered and the content from
accumulator is written in 526A. - Memory Write Machine Cycle

✓ Assume the memory address for the instruction and let the content of
accumulator is C7H. So, C7H from accumulator is now stored in 526A.


3 Timing diagram for INR M

✓ Fetching the Opcode 34H from the memory 4105H. (OF cycle)
✓ Let the memory address (M) be 4250H. (MR cycle -To read Memory address
and data)
✓ Let the content of that memory is 12H.
✓ Increment the memory content from 12H to 13H. (MW machine cycle)
 UNIT-2
Advanced Microprocessor

Introduction to 8086 microprocessor

Features of 8086
 8086 Microprocessor is an enhanced version of 8085Microprocessor that was
designed by Intel in 1976.
 It is a 16-bit Microprocessor i.e it is having 16 number of data lines.
 It has 20 address lines So the maximum memory capacity is 1MB.
 It consists of powerful instruction set, which provides operations like multiplication
and division easily.
 It supports two modes of operation, i.e. Maximum mode and Minimum mode.
Maximum mode is suitable for system having multiple processors and Minimum
mode is suitable for system having a single processor.
 It has an instruction queue, which is capable of storing six instruction bytes from
the memory resulting in faster processing.

 It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which improves
performance.
 Fetch stage can prefetch up to 6 bytes of instructions and stores them in the queue
and Execute stage executes these instructions.
 It has 256 vectored interrupts.
 It consists of 29,000 transistors.

8086 Architecture

 8086 Microprocessor is divided into two functional units.

EU (Execution Unit)

BIU (Bus Interface Unit).

EU (Execution Unit)
 Execution unit gives instructions to BIU regarding from where to fetch the datas.
 Its function is to control operations on data using the instruction decoder & ALU.
 EU has no direct connection with system buses and it performs operations over data
through BIU.

BIU (Bus Interface Unit)

 BIU takes care of all data and addresses transfers on the buses for the EU like

 Sending addresses,
 Fetching instructions from the memory,
 Reading data from the ports and the memory as well as writing data
to the ports and the memory.

 EU has no direction connection with System Buses so this is possible with the BIU.
EU and BIU are connected with the Internal Bus.
Register Organization of 8086
General purpose register

 There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL.
These registers can be used individually to store 8-bit data .
 Two 8-bit registers are used to make a register pair which can store 16-bit data.
 The valid register pairs in 8086 microprocessor are AX, BX, CX, and DX
respectively.

AX register –

 It is also known as accumulator register.

 It is of 16 bits and is divided into two 8-bit registers AH and AL
 It generally is used to store the result for any arithmetical and logical
instructions but in 8086 microprocessor it is not mandatory to have
accumulator as the destination operand

BX register

 This is the base register.

 It is of 16 bits and is divided into two 8-bit registers BH and BL
 It is used to store the value of the offset address.

CX register –

 It is referred to as counter.
 It is of 16 bits and is divided into two 8-bit registers CH and CL
 It is used in loop instruction to store the loop counter.

DX register –

 This is the data register.

 It is of 16 bits and is divided into two 8-bit registers DH and DL.
  It is used in input/output port addressing.

Stack pointer register (SP)

 It is a 16-bit register.
 It is used to hold the address of the stack top.

Base Pointer (BP).

 It is a 16-bit register
 It is primary used in accessing parameters passed by the stack

Source Index Register (SI)

 It is a 16-bit register
 It is used in the pointer addressing of data and as a source in some string related
operations.

Destination Index Register (DI)

 It is a 16-bit register
 It is used in the pointer addressing of data and as a destination in some string
related operations.

Flag Register

 It is a 16-bit register.
 This register is used to store the status of the result after any arithmetic operations.
  It has 9 flags and they are divided into 2 groups − Conditional Flags and Control
Flags.

Conditional Flags

It represents the result of the last arithmetic or logical instruction executed. Following is
the list of conditional flags −

 Carry flag − This flag indicates an overflow condition for arithmetic operations.
 Auxiliary flag − When an operation is performed at ALU, it results in a
carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), then
this flag is set, i.e. carry given by D3 bit to D4 is AF flag. The processor uses this flag
to perform binary to BCD conversion.
 Parity flag − This flag is used to indicate the parity of the result, i.e. when the lower
order 8-bits of the result contains even number of 1’s, then the Parity Flag is set. For
odd number of 1’s, the Parity Flag is reset.
 Zero flag − This flag is set to 1 when the result of arithmetic or logical operation is
zero else it is set to 0.
 Sign flag − This flag holds the sign of the result, i.e. when the result of the operation
is negative, then the sign flag is set to 1 else set to 0.
 Overflow flag – T his flag represents the result when the system
capacity is exceeded.

Control Flags

Control flags controls the operations of the execution unit. Following is the list of control
flags −

 Trap flag − It is used for single step control and allows the user to execute one
instruction at a time for debugging. If it is set, then the program can be run in a
single step mode.
 Interrupt flag − It is an interrupt enable/disable flag, i.e. used to allow/prohibit the
interruption of a program. It is set to 1 for interrupt enabled condition and set to 0
for interrupt disabled condition.
 Direction flag − It is used in string operation. As the name suggests when it is set
then string bytes are accessed from the higher memory address to the lower
memory address and vice-a-versa.
Memory Segmentation and Physical memory organization in
8086 microprocessor
What is memory segmentation?

 Memory Segmentation is the process in which the main memory of the computer is logically
divided into different segments and each segment has its own base address.
 It is basically used to enhance the speed of execution of the computer system.
 Due to segmentation the processor is able to fetch and execute the data from the memory
easily and fast.

Need for Segmentation:

 8086 microprocessor has a 20-bit address bus so it can address a maximum of 1MB
of memory.
 8086 can work with only four 64 KB segments at a time within this 1MB range.
 These four memory segments are called as code segment, data segment, and Extra
segment and stack segment.
 The Bus Interface Unit (BIU) contains four 16 bit special purpose registers called as
Segment registers .The segment registers are named as
Code segment register
Data segment register
Extra Segment Register
Stack Segment Register
 The segment registers are used to hold the upper 16 bits from the 20-bit physical
address in the respective segments.
Calculation of Physical address:

 The 16-bit content of one of the four segment registers (CS, DS, ES, SS) is known as
the base segment address
 The offset address is the distance or displacement from the base segment address to
the next address within the segments. The offset address is also called as logical
address
 Generally offset address is contained in the registers IP, BP, SP, BX, SI or DI
depending on the segments used.

 Offset and base segment address are combined to form a 20-bit physical address
(also called real address) that is used to access the memory.

 The content of the segment register is internally appended with 0H (0000B) on its
right most end to form a 20-bit memory address—this 20-bit address points to the
start of the segment. The offset is then added to the above to get the physical
address.
  The formula to calculate the 20-bit physical address is

Physical Address =Segment Address*10H + Offset Address

Example-1
If the DS is 4247 H and offset is A95C H then calculate the
(i) Starting address of the segment
(ii) End address of the segment
(iii) Operands 20-bit physical address.

[Refer the notes]

Types of Segmentation:

1. Overlapping Segment – A segment starts at a particular address and its maximum

size can go up to 64kilobytes. But if another segment starts along with this
64kilobytes location of the first segment, then the two are said to be Overlapping
Segment.

2. Non-Overlapped Segment – A segment starts at a particular address and its

maximum size can go up to 64kilobytes. But if another segment starts before this
64kilobytes location of the first segment, then the two segments are said to be Non-
Overlapped Segment.

Advantages of the Segmentation:

 It provides a powerful memory management mechanism.

 It allows to extend the address ability of the processor, i.e. segmentation
allows the use of 16 bit registers to give an addressing capability of 1
Megabytes. Without segmentation, it would require 20 bit registers.
 Data related or stack related or code related operations can be performed in
different a segment which increases the information security.
Addressing modes of 8086 microprocessor
Addressing modes of 8086 are as follows:

1. Immediate addressing mode-

In this mode, the operand is specified in the instruction itself.

Example:

MOV CL, 12H This instruction moves the data 12H to CL register

MOV AH, 37H This instruction moves the data 37H to AH register

MOV AX, 4567H This instruction moves the data 4567H to AX register

2. Register addressing mode-

In this mode, operands are specified using registers. Registers are used for both
source and destination operands .

Example:

MOV AX, BX This instruction moves the content of BX register to AX

register.

MOV CX, DX This instruction moves the content of CX register to DX

register

MOV AX, SP This instruction moves the content of SP register to AX

register

MOV AH, BL This instruction moves the content of BL register to AH

register

3. Direct addressing mode:

In this mode, the offset address of the operand is directly specified in the instruction
itself. The 20-bit physical address for the operand can be calculated adding the
offset address with the default segment DS or ES.

Example:

MOV AL, [5358H]

This instruction moves data from the offset address 5358H into register AL
 The physical address is calculated as

DS * 10H + 5358H

Assume DS = 5000H

PA = 50000 + 5358H = 55358H

So AL ← [55358H]

4. Register indirect addressing mode:

In this addressing mode the operands offset address is hold by the registers. The 20-
bit physical address for the operand can be calculated adding the offset address with
the default segment DS or ES.

Example:

MOV AL, [BX]

This instruction moves the data from the address pointed by BX into register.

Physical address can be calculated as DS * 10H + BX.

5. Register relative addressing mode:

In this mode, the operands 20-bit physical address is calculated by adding the 8 bit
or a 16 bit displacement along with the offset address within the default segments
DS or ES .

Example:

MOV AL, [BX] 25H

This instruction moves one byte data from the address pointed by BX + 25H in data
segment to AL.

CL ← DS: [BX + 25H]

Physical address =DS * 10H + BX + 25H.

6. I ndexed addressing mode:

In this addressing mode, the index registers are used to hold the offset address. The
Source index (SI) register and Destination Index(DI) registers are used in this
addressing mode.
 Examples:

MOV AX, [SI]

Physical address =DS * 10H + [SI]

MOV AX, [DI]

Physical address =DS * 10H + [DI]

7. Base indexed addressing mode:

In this addressing mode the base registers (BX or BP) and the indexed registers(SI
or DI) are used to hold the offset address.

Example:

MOV AX, [BX][ SI]

Physical address = DS * 10H + [BX] + [SI].

8. Relative based indexed addressing mode:

In this addressing mode the base registers (BX or BP) and the indexed registers (SI
or DI) along with a 8 bit or a 16 bit displacement are used to hold the offset address.

Example:

MOV AX. [BX] [SI] 37H

Physical address =DS * 10H + BX + DI + 37H.

9. Implied addressing mode:

In this mode, the operands are not specified in the instruction .

Example:

STC

This instruction is used set the carry flag.

Signal Descriptions/PIN Configurations of 8086
Microprocessor.

 8086 was the first 16-bit microprocessor available in 40-pin DIP (Dual Inline
Package) chip
Power supply and frequency signals

 It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its
operation.

Clock signal

 Clock signal is provided through Pin-19. It provides timing to the processor for
operations. Its frequency is different for different versions, i.e. 5MHz, 8MHz and
10MHz.

Address/data bus

 AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte data
and AD8-AD15 carries higher order byte data. During the first clock cycle, it carries
16-bit address and after that it carries 16-bit data.

Address/status bus

 A16-A19/S3-S6. These are the 4 address/status buses. During the first clock cycle, it
carries 4-bit address and later it carries status signals.

S7/BHE

 BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the
transfer of data using data bus D8-D15. This signal is low during the first clock
cycle, thereafter it is active.

Read

 It is available at pin 32 and is used to read signal for Read operation.

Ready

 It is available at pin 22. It is an acknowledgement signal from I/O devices that data
is transferred. It is an active high signal. When it is high, it indicates that the device
is ready to transfer data. When it is low, it indicates wait state

RESET

 It is available at pin 21 and is used to restart the execution. It causes the processor to
immediately terminate its present activity. This signal is active high for the first 4
clock cycles to RESET the microprocessor.
INTR

 It is available at pin 18. It is an interrupt request signal, which is sampled during

the last clock cycle of each instruction to determine if the processor considered this
as an interrupt or not.

NMI

 It stands for non-maskable interrupt and is available at pin 17. It is an edge

triggered input, which causes an interrupt request to the microprocessor.

INTA

 It is an interrupt acknowledgement signal and id available at pin 24. When the

microprocessor receives this signal, it acknowledges the interrupt.

ALE

 It stands for address enable latch and is available at pin 25. A positive pulse is
generated each time the processor begins any operation. This signal indicates the
availability of a valid address on the address/data lines.

HLDA

 It stands for Hold Acknowledgement signal and is available at pin 30. This signal
acknowledges the HOLD signal.

HOLD

 This signal indicates to the processor that external devices are requesting to access
the address/data buses. It is available at pin 31.
LOCK

When this signal is active, it indicates to the other processors not to ask the CPU to leave
the system bus. It is activated using the LOCK prefix on any instruction and is available at
pin 29.
Instruction set and Assembly language
programming of 8086 microprocessor:
The instructions of 8086 microprocessor are classified in the following category

1.Data Transfer instructions

2.Arithmetic and logical Instructions

3.Branch/Loop instructions

4.Machine control instructions

5.Shift and Rotate Instructions

6. Interrupt Instructions

1. Data Transfer instructions

These instructions are used to transfer the data from the source to the destination.

Examples:

MOV AX, BX : The content of BX register is transferred in to AX register.

MOV CX, 037AH : The data 037AH is loaded in to CX register.

PUSH AX

 This instruction is used to push the data in to the stack.

 First the higher byte of data (content of AH register) is transferred to stack.
 Second the lower byte of data (content of AL register) is transferred to stack.
 The stack pointer will be decremented by 2 after the execution of PUSH instruction.
POP AX

 This instruction is used to transfer the data from the stack.

 First the lower byte of data transferred from the stack.
 Second the higher byte of data is transferred from the stack
 The stack pointer will be incremented by 2 after the execution of POP instruction.

XCHG AX, BX

This instruction is used to exchange the data between BX and AX register.

IN accumulator, port address

Comments:It transfer the operand from the port address to the accumulator.
Examples:
IN AX,0028H
OUT port address, accumulator

Comments:It transfer the operand from the accumulator to the port address.
Examples:
OUT 0028H,AX

2. Arithmetic and logical Instructions

ADD Destination Source

Comment: These instructions add a number from some source to a number in some
destination and put the result in the specified destination.
Example:
ADD AX, BX: Add content of BX to content of AX and result in AX
ADD AL, 74H: Add immediate number 74H to content of AL and Result is stored in AL

SUB Destination Source

Comments: These instructions subtract the number in some source from the number in
some destination and put the result in the destination
Examples:
SUB CX, BX Subtract BX from CX and result stored in CX
SUB AX, 3427H Subtract immediate number 3427H from AX and result stored in AX

MUL source
Comments: This instruction is used for multiplication.

DIV source
Comments: This instruction is used for division.

3.Branch/Loop instructions

 It is also called program execution transfer instruction.

 Instructions of this group transfer program execution from the normal sequence of
instructions to the specified destination or target.
 The following instructions come under this category:

These instructions are used to transfer the control during an execution with some conditions
4.Machine/Processor Control Instructions

5.Shift and Rotate Instructions

6. Interrupt Instructions

MINIMUM AND MAXIMUM MODE OPERATIONS OF 8086

MICROPROCESSOR AND THEIR BUS CYCLE

What is minimum mode of operation in 8086 microprocessor?

8086 minimum mode system configuration
 The typical Minimum Mode Configuration of 8086 is shown in
the figure
 AD0-AD15, A16/S3-A19/S6, and BHE/S7 signals are multiplexed.
These signals are demultiplexed by external latches and ALE
signal generated by the processor.
 If a system includes several interfaces then to increase
transmission capacities it is necessary to use drivers and receivers
which is called as transceiver.
 DT/R’ signal is connected to the T input, which controls the
direction of the data flow. When this signal is low, receivers are
enabled, so that 8086 can read data from memory or input device.
To write data into memory or output device, the 8086’s
DT/R’ signal goes high.
 HOLD and HLDA signals are used to interface other bus masters
like DMA controller.
 Interrupt request (INTR) and interrupt acknowledge (INTA) are
used to extend the interrupt handling capacity of the 8086 with the
help of interrupt controller.
 he status on the M/IO’, RD’, and WR’ lines decides the type of
data transfer, as listed
What is maximum mode of operation in 8086 microprocessor ?
8086 maximum mode system configuration
 The typical maximum Mode Configuration of 8086 is shown in the figure

 In the maximum mode additional circuitry is required to translate the

control signals.

 The additional circuitry converts the status signals (S 2-S0) into the I/O and
memory transfer signals. It also generates the control signals required to
direct the data flow and for controlling 8282 latches and 8286 transceivers.

 the 8288 is able to originate the address latch enable signal to the 8282’s,
the enable and direction signals to the 8286 transceivers, and the interrupt
acknowledge signal to the interrupt controller.
 UNIT-3
Programmable Peripheral Interface (8255)

The 8255A is a general purpose programmable I/O device designed to transfer the
data from I/O to interrupt I/O under certain conditions as required. It can be used with
almost any microprocessor.
It consists of three 8-bit bidirectional I/O ports (24I/O lines) which can be configured as
per the requirement.

Ports of 8255A
8255A has three ports, i.e., PORT A, PORT B, and PORT C.
 Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.
 Port B is similar to PORT A.
 Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C
upper (PC7-PC4) by the control word.
These three ports are further divided into two groups, i.e. Group A includes PORT A
and upper PORT C. Group B includes PORT B and lower PORT C. These two groups
can be programmed in three different modes, i.e. the first mode is named as mode 0,
the second mode is named as Mode 1 and the third mode is named as Mode 2.

Operating Modes
8255A has three different operating modes −
 Mode 0 − In this mode, Port A and B is used as two 8-bit ports and Port C as
two 4-bit ports. Each port can be programmed in either input mode or output
mode where outputs are latched and inputs are not latched. Ports do not have
interrupt capability.
 Mode 1 − In this mode, Port A and B is used as 8-bit I/O ports. They can be
configured as either input or output ports. Each port uses three lines from port C
as handshake signals. Inputs and outputs are latched.
 Mode 2 − In this mode, Port A can be configured as the bidirectional port and
Port B either in Mode 0 or Mode 1. Port A uses five signals from Port C as
handshake signals for data transfer. The remaining three signals from Port C
can be used either as simple I/O or as handshake for port B.

Features of 8255A
The prominent features of 8255A are as follows −
 It consists of 3 8-bit IO ports i.e. PA, PB, and PC.
 Address/data bus must be externally demux'd.
 It is TTL compatible.
 It has improved DC driving capability.

8255 Architecture
The following figure shows the architecture of 8255A −
Let us first take a look at the pin diagram of Intel 8255A −

Now let us discuss the functional description of the pins in 8255A.

Data Bus Buffer

It is a tri-state 8-bit buffer, which is used to interface the microprocessor to the system
data bus. Data is transmitted or received by the buffer as per the instructions by the
CPU. Control words and status information is also transferred using this bus.

Read/Write Control Logic

This block is responsible for controlling the internal/external transfer of
data/control/status word. It accepts the input from the CPU address and control buses,
and in turn issues command to both the control groups.

CS
It stands for Chip Select. A LOW on this input selects the chip and enables the
communication between the 8255A and the CPU. It is connected to the decoded
address, and A0 & A1 are connected to the microprocessor address lines.
Their result depends on the following conditions −

CS A1 A0 Result

0 0 0 PORT A

0 0 1 PORT B
 0 1 0 PORT C

0 1 1 Control Register

1 X X No Selection

WR
It stands for write. This control signal enables the write operation. When this signal
goes low, the microprocessor writes into a selected I/O port or control register.

RESET
This is an active high signal. It clears the control register and sets all ports in the input
mode.

RD
It stands for Read. This control signal enables the Read operation. When the signal is
low, the microprocessor reads the data from the selected I/O port of the 8255.

A0 and A1
These input signals work with RD, WR, and one of the control signal. Following is the
table showing their various signals with their result.

A1 A0 RD WR CS Result

0 0 0 1 0 Input Operation
PORT A → Data Bus

0 1 0 1 0 PORT B → Data Bus

1 0 0 1 0 PORT C → Data Bus

Output Operation
0 0 1 0 0
Data Bus → PORT A
 0 1 1 0 0 Data Bus → PORT A

1 0 1 0 0 Data Bus → PORT B

1 1 1 0 0 Data Bus → PORT D

Programmable Interval Timer (8254)

Features of 8253 / 54
The most prominent features of 8253/54 are as follows −
 It has three independent 16-bit down counters.
 It can handle inputs from DC to 10 MHz.
 These three counters can be programmed for either binary or BCD count.
 It is compatible with almost all microprocessors.
 8254 has a powerful command called READ BACK command, which allows the
user to check the count value, the programmed mode, the current mode, and
the current status of the counter.

8254 Architecture
The architecture of 8254 looks as follows −
8254 Pin Description
Here is the pin diagram of 8254 −

In the above figure, there are three counters, a data bus buffer, Read/Write control
logic, and a control register. Each counter has two input signals - CLOCK & GATE, and
one output signal - OUT.
Data Bus Buffer
It is a tri-state, bi-directional, 8-bit buffer, which is used to interface the 8253/54 to the
system data bus. It has three basic functions −

 Programming the modes of 8253/54.

 Loading the count registers.
 Reading the count values.

Read/Write Logic
It includes 5 signals, i.e. RD, WR, CS, and the address lines A 0 & A1. In the peripheral
I/O mode, the RD and WR signals are connected to IOR and IOW, respectively. In the
memorymapped I/O mode, these are connected to MEMR and MEMW.
Address lines A0 & A1 of the CPU are connected to lines A0 and A1 of the 8253/54, and
CS is tied to a decoded address. The control word register and counters are selected
according to the signals on lines A0 & A1.

A1 A0 Result
 0 0 Counter 0

0 1 Counter 1

1 0 Counter 2

1 1 Control Word Register

X X No Selection

Control Word Register

This register is accessed when lines A0 & A1 are at logic 1. It is used to write a
command word, which specifies the counter to be used, its mode, and either a read or
write operation. Following table shows the result for various control inputs.

A1 A0 RD WR CS Result

0 0 1 0 0 Write Counter 0

0 1 1 0 0 Write Counter 1

1 0 1 0 0 Write Counter 2

1 1 1 0 0 Write Control Word

0 0 0 1 0 Read Counter 0

0 1 0 1 0 Read Counter 1

1 0 0 1 0 Read Counter 2
 1 1 0 1 0 No operation

X X 1 1 0 No operation

X X X X 1 No operation

Counters
Each counter consists of a single, 16 bit-down counter, which can be operated in either
binary or BCD. Its input and output is configured by the selection of modes stored in
the control word register. The programmer can read the contents of any of the three
counters without disturbing the actual count in process.

Programmable Interrupt Controller (8259A)

The 8259 is known as the Programmable Interrupt Controller (PIC) microprocessor. In
8085 and 8086 there are five hardware interrupts and two hardware interrupts
respectively. Bu adding 8259, we can increase the interrupt handling capability. This
chip combines the multi-interrupt input source to single interrupt output. This provides 8-
interrupts from IR0 to IR7. Let us see some features of this microprocessor.
 This chip is designed for 8085 and 8086.
 It can be programmed either in edge triggered, or in level triggered mode
 We can mask individual bits of Interrupt Request Register.
 By cascading 8259 chips, we can increase interrupts up to 64 interrupt lines
 Clock cycle is not needed.
The pin level diagram and functional pin diagram is like below -
The block diagram is like below -
 Block Description

Data Bus Buffer This block is used to communicate between 8259 and 8085/8086
by acting as buffer. It takes the control word from 8085/8086 and
send it to the 8259. It transfers the opcode of the selected
interrupts and address of ISR to the other connected
microprocessor. It can send maximum 8-bit at a time.

R/W Control Logic This block works when the value of pin CS is 0. This block is used
to flow the data depending upon the inputs of RD and WR. These
are active low pins for read and write.
 Block Description

Control Logic It controls the functionality of each block. It has pin called INTR.
This is connected to other microprocessors for taking the interrupt
request. The INT pin is used to give the output. If 8259 is enabled,
and also the interrupt flags of other microprocessors are high then
this causes the value of the output INT pin high, and in this way
this chip can responds requests made by other microprocessors.

Interrupt Request It stores all interrupt level that are requesting for interrupt service.
Register

Interrupt Service It stores interrupt level that are currently being execute.
Register

Interrupt Mask It stores interrupt level that will be masked, by storing the masking
Register bits of interrupt level.

Priority Resolver It checks all three registers, and set the priority of the interrupts.
Interrupt with the highest priority is set in the ISR register. It also
reset the interrupt level which is already been serviced in the IRR.

Cascade Buffer To increase number of interrupt pin, we can cascade more

number of pins, by using cascade buffer. When we are going to
increase the interrupt capability, CSA lines are used to control
multiple interrupts.

Programmable DMA Controller (8257)

DMA stands for Direct Memory Access. It is designed by Intel to transfer data at the
fastest rate. It allows the device to transfer the data directly to/from memory without
any interference of the CPU.
Using a DMA controller, the device requests the CPU to hold its data, address and
control bus, so the device is free to transfer data directly to/from the memory. The DMA
data transfer is initiated only after receiving HLDA signal from the CPU.
How DMA Operations are Performed?
Following is the sequence of operations performed by a DMA −
 Initially, when any device has to send data between the device and the memory,
the device has to send DMA request (DRQ) to DMA controller.
 The DMA controller sends Hold request (HRQ) to the CPU and waits for the
CPU to assert the HLDA.
 Then the microprocessor tri-states all the data bus, address bus, and control
bus. The CPU leaves the control over bus and acknowledges the HOLD request
through HLDA signal.
 Now the CPU is in HOLD state and the DMA controller has to manage the
operations over buses between the CPU, memory, and I/O devices.

Features of 8257
Here is a list of some of the prominent features of 8257 −
 It has four channels which can be used over four I/O devices.
 Each channel has 16-bit address and 14-bit counter.
 Each channel can transfer data up to 64kb.
 Each channel can be programmed independently.
 Each channel can perform read transfer, write transfer and verify transfer
operations.
 It generates MARK signal to the peripheral device that 128 bytes have been
transferred.
 It requires a single phase clock.
 Its frequency ranges from 250Hz to 3MHz.
 It operates in 2 modes, i.e., Master mode and Slave mode.

8257 Architecture
The following image shows the architecture of 8257 −
8257 Pin Description
The following image shows the pin diagram of a 8257 DMA controller −
DRQ0−DRQ3
These are the four individual channel DMA request inputs, which are used by the
peripheral devices for using DMA services. When the fixed priority mode is selected,
then DRQ0 has the highest priority and DRQ3 has the lowest priority among them.
DACKo − DACK3
These are the active-low DMA acknowledge lines, which updates the requesting
peripheral about the status of their request by the CPU. These lines can also act as
strobe lines for the requesting devices.
Do − D7
These are bidirectional, data lines which are used to interface the system bus with the
internal data bus of DMA controller. In the Slave mode, it carries command words to
8257 and status word from 8257. In the master mode, these lines are used to send
higher byte of the generated address to the latch. This address is further latched using
ADSTB signal.
IOR
It is an active-low bidirectional tri-state input line, which is used by the CPU to read
internal registers of 8257 in the Slave mode. In the master mode, it is used to read data
from the peripheral devices during a memory write cycle.
IOW
It is an active low bi-direction tri-state line, which is used to load the contents of the
data bus to the 8-bit mode register or upper/lower byte of a 16-bit DMA address
register or terminal count register. In the master mode, it is used to load the data to the
peripheral devices during DMA memory read cycle.
CLK
It is a clock frequency signal which is required for the internal operation of 8257.
RESET
This signal is used to RESET the DMA controller by disabling all the DMA channels.
Ao - A 3
These are the four least significant address lines. In the slave mode, they act as an
input, which selects one of the registers to be read or written. In the master mode, they
are the four least significant memory address output lines generated by 8257.
CS
It is an active-low chip select line. In the Slave mode, it enables the read/write
operations to/from 8257. In the master mode, it disables the read/write operations
to/from 8257.
A4 - A 7
These are the higher nibble of the lower byte address generated by DMA in the master
mode.
READY
It is an active-high asynchronous input signal, which makes DMA ready by inserting
wait states.
HRQ
This signal is used to receive the hold request signal from the output device. In the
slave mode, it is connected with a DRQ input line 8257. In Master mode, it is
connected with HOLD input of the CPU.
HLDA
It is the hold acknowledgement signal which indicates the DMA controller that the bus
has been granted to the requesting peripheral by the CPU when it is set to 1.
MEMR
It is the low memory read signal, which is used to read the data from the addressed
memory locations during DMA read cycles.
MEMW
It is the active-low three state signal which is used to write the data to the addressed
memory location during DMA write operation.
ADST
This signal is used to convert the higher byte of the memory address generated by the
DMA controller into the latches.
AEN
This signal is used to disable the address bus/data bus.
TC
It stands for ‘Terminal Count’, which indicates the present DMA cycle to the present
peripheral devices.
MARK
The mark will be activated after each 128 cycles or integral multiples of it from the
beginning. It indicates the current DMA cycle is the 128th cycle since the previous
MARK output to the selected peripheral device.
Vcc
It is the power signal which is required for the operation of the circuit.

Programmable Communication Interface (8251A)

8251 universal synchronous asynchronous receiver transmitter (USART) acts as a
mediator between microprocessor and peripheral to transmit serial data into parallel
form and vice versa.
1. It takes data serially from peripheral (outside devices) and converts into parallel
data.
2. After converting the data into parallel form, it transmits it to the CPU.
3. Similarly, it receives parallel data from microprocessor and converts it into serial
form.
4. After converting data into serial form, it transmits it to outside device (peripheral).
Block Diagram of 8251 USART –

It contains the following blocks:

1. Data bus buffer –
This block helps in interfacing the internal data bus of 8251 to the system data bus.
The data transmission is possible between 8251 and CPU by the data bus buffer
block.

2. Read/Write control logic –

It is a control block for overall device. It controls the overall working by selecting
the operation to be done. The operation selection depends upon input signals as:
 In this way, this unit selects one of the three registers- data buffer register, control
register, status register.
3. Modem control (modulator/demodulator) –
A device converts analog signals to digital signals and vice-versa and helps the
computers to communicate over telephone lines or cable wires. The following are
active-low pins of Modem.
 DSR: Data Set Ready signal is an input signal.
 DTR: Data terminal Ready is an output signal.
 CTS: It is an input signal which controls the data transmit circuit.
RTS: It is an output signal which is used to set the status RTS.
4. Transmit buffer –
This block is used for parallel to serial converter that receives a parallel byte for
conversion into serial signal and further transmission onto the common channel.
 TXD: It is an output signal, if its value is one, means transmitter will transmit
the data.
5. Transmit control –
This block is used to control the data transmission with the help of following pins:
 TXRDY: It means transmitter is ready to transmit data character.
 TXEMPTY: An output signal which indicates that TXEMPTY pin has
transmitted all the data characters and transmitter is empty now.
 TXC: An active-low input pin which controls the data transmission rate of
transmitted data.
6. Receive buffer –
This block acts as a buffer for the received data.
 RXD: An input signal which receives the data.
7. Receive control –
This block controls the receiving data.
  RXRDY: An input signal indicates that it is ready to receive the data.
 RXC: An active-low input signal which controls the data transmission rate of
received data.
 SYNDET/BD: An input or output terminal. External synchronous mode-input
terminal and asynchronous mode-output terminal.
Programmable Keyboard and Display Controller (8279)
8279 programmable keyboard/display controller is designed by Intel that
interfaces a keyboard with the CPU. The keyboard first scans the keyboard and
identifies if any key has been pressed. It then sends their relative response of the
pressed key to the CPU and vice-a-versa.

How Many Ways the Keyboard is Interfaced with the CPU?

The Keyboard can be interfaced either in the interrupt or the polled mode. In
the Interrupt mode, the processor is requested service only if any key is pressed,
otherwise the CPU will continue with its main task.

In the Polled mode, the CPU periodically reads an internal flag of 8279 to check
whether any key is pressed or not with key pressure.

How Does 8279 Keyboard Work?

The keyboard consists of maximum 64 keys, which are interfaced with the CPU
by using the key-codes. These key-codes are de-bounced and stored in an 8-byte
FIFORAM, which can be accessed by the CPU. If more than 8 characters are
entered in the FIFO, then it means more than eight keys are pressed at a time. This
is when the overrun status is set.

If a FIFO contains a valid key entry, then the CPU is interrupted in an interrupt
mode else the CPU checks the status in polling to read the entry. Once the CPU
reads a key entry, then FIFO is updated, and the key entry is pushed out of the
FIFO to generate space for new entries.
Architecture and Description

I/O Control and Data Buffer

This unit controls the flow of data through the microprocessor. It is enabled only when
D is low. Its data buffer interfaces the external bus of the system with the internal bus
of the microprocessor. The pins A0, RD, and WR are used for command, status or data
read/write operations.
Control and Timing Register and Timing Control
This unit contains registers to store the keyboard, display modes, and other operations
as programmed by the CPU. The timing and control unit handles the timings for the
operation of the circuit.
Scan Counter
It has two modes i.e. Encoded mode and Decoded mode. In the encoded mode, the
counter provides the binary count that is to be externally decoded to provide the scan
lines for the keyboard and display.
In the decoded scan mode, the counter internally decodes the least significant 2 bits
and provides a decoded 1 out of 4 scan on SL0-SL3.
Return Buffers, Keyboard Debounce, and Control
This unit first scans the key closure row-wise, if found then the keyboard debounce unit
debounces the key entry. In case, the same key is detected, then the code of that key
is directly transferred to the sensor RAM along with SHIFT & CONTROL key status.
FIFO/Sensor RAM and Status Logic
This unit acts as 8-byte first-in-first-out (FIFO) RAM where the key code of every
pressed key is entered into the RAM as per their sequence. The status logic generates
an interrupt request after each FIFO read operation till the FIFO gets empty.
In the scanned sensor matrix mode, this unit acts as sensor RAM where its each row is
loaded with the status of their corresponding row of sensors into the matrix. When the
sensor changes its state, the IRQ line changes to high and interrupts the CPU.
Display Address Registers and Display RAM
This unit consists of display address registers which holds the addresses of the word
currently read/written by the CPU to/from the display RAM.
8279 − Pin Description
The following figure shows the pin diagram of 8279 −

Data Bus Lines, DB0 - DB7

These are 8 bidirectional data bus lines used to transfer the data to/from the CPU.
CLK
The clock input is used to generate internal timings required by the microprocessor.
RESET
As the name suggests this pin is used to reset the microprocessor.
CS Chip Select
When this pin is set to low, it allows read/write operations, else this pin should be set to
high.
A0
This pin indicates the transfer of command/status information. When it is low, it
indicates the transfer of data.
RD, WR
This Read/Write pin enables the data buffer to send/receive data over the data bus.
IRQ
This interrupt output line goes high when there is data in the FIFO sensor RAM. The
interrupt line goes low with each FIFO RAM read operation. However, if the FIFO RAM
further contains any key-code entry to be read by the CPU, this pin again goes high to
generate an interrupt to the CPU.
Vss, Vcc
These are the ground and power supply lines of the microprocessor.
SL0 − SL3
These are the scan lines used to scan the keyboard matrix and display the digits.
These lines can be programmed as encoded or decoded, using the mode control
register.
RL0 − RL7
These are the Return Lines which are connected to one terminal of keys, while the
other terminal of the keys is connected to the decoded scan lines. These lines are set
to 0 when any key is pressed.
SHIFT
The Shift input line status is stored along with every key code in FIFO in the scanned
keyboard mode. Till it is pulled low with a key closure, it is pulled up internally to keep it
high
CNTL/STB - CONTROL/STROBED I/P Mode
In the keyboard mode, this line is used as a control input and stored in FIFO on a key
closure. The line is a strobe line that enters the data into FIFO RAM, in the strobed
input mode. It has an internal pull up. The line is pulled down with a key closure.
BD
It stands for blank display. It is used to blank the display during digit switching.
OUTA0 – OUTA3 and OUTB0 – OUTB3
These are the output ports for two 16x4 or one 16x8 internal display refresh registers.
The data from these lines is synchronized with the scan lines to scan the display and
the keyboard.

Operational Modes of 8279

There are two modes of operation on 8279 − Input Mode and Output Mode.
Input Mode
This mode deals with the input given by the keyboard and this mode is further
classified into 3 modes.
 Scanned Keyboard Mode − In this mode, the key matrix can be interfaced
using either encoded or decoded scans. In the encoded scan, an 8×8 keyboard
or in the decoded scan, a 4×8 keyboard can be interfaced. The code of key
pressed with SHIFT and CONTROL status is stored into the FIFO RAM.
 Scanned Sensor Matrix − In this mode, a sensor array can be interfaced with
the processor using either encoder or decoder scans. In the encoder scan, 8×8
sensor matrix or with decoder scan 4×8 sensor matrix can be interfaced.
 Strobed Input − In this mode, when the control line is set to 0, the data on the
return lines is stored in the FIFO byte by byte.
Output Mode
This mode deals with display-related operations. This mode is further classified into
two output modes.
 Display Scan − This mode allows 8/16 character multiplexed displays to be
organized as dual 4-bit/single 8-bit display units.
 Display Entry − This mode allows the data to be entered for display either from
the right side/left side.
 UNIT-4
8051
MICROCONTROLLER
 Overview of 8051 microcontroller
Features:
 8051 microcontroller is designed
by Intel in 1981
 It is an 8-bit microcontroller
 It is built with 40 pins DIP (dual
inline package).
 It has 4KB of internal ROM .
 It has 128 bytes of internal
RAM .
 It has two 16-bit
timers/counters
 It has four 8-bit input/output
ports(P0-P3)
 It has an serial interface.
Architecture of 8051 microcontroller
CPU :
CPU is called as central processing unit. It
synchronizes and manages all processes that are
carried out in microcontroller.
Interrupts:
Interrupts provide a method to postpone or delay
the current process, performs a sub-routine task
and then restart the standard program again.
Memory:
This is used to store the informations.8051
microcontroller has 4KB of internal ROM and 128
bytes of internal RAM
Bus:
It is a group of connecting lines or wires
which are used to transfer informations
between different components of the
system.
8051 microcontroller consists of 16-bit
address bus and 8-bit data bus.
Oscillator:
It is a circuit which generates the clock signal
of 12MHz for the operation of
timers/counters.
PIN DIAGRAM OF 8051 MICROCONTROLLER
 I/O PORTS
 One of the most useful features of the 8051 is
that it contains four I/O ports.
 The ports are called as
Port 0(P0)
Port 1(P1)
Port 2(P2)
Port 3(P3)

 Each port can be used as input or output so the

nature of each port is bidirectional.
Port 0 （pins 32-39）：P0（P0.0～P0.7）
 8-bit R/W -General Purpose I/O
 acts as a multiplexed low byte address and data bus for external
memory design

Port 1 （pins 1-8）：P1（P1.0～P1.7）

 Only8-bit R/W -General Purpose I/O

Port 2 （pins 21-28）：P2（P2.0～P2.7）

 8-bit R/W -General Purpose I/O
 High byte of the address bus for external memory design

Port 3 （pins 10-17）：P3（P3.0～P3.7）

 General Purpose I/O
 It is also used for any of the internal peripherals (timers) or
external interrupts.
 Addressing Modes of 8051
microcontroller
The addressing modes of 8051 microcontroller
are of following types.
Immediate Addressing Mode
Register Addressing Mode
Direct Addressing Mode
Register Indirect Addressing Mode
Indexed Addressing Mode
Implied Addressing Mode
 1.Immediate Addressing Mode

In Immediate Addressing Mode, the data is

provided in the instruction itself. The data is
provided immediately after the opcode.
The immediate data must be preceded by the
sign(#).
MOV A, #25H Load 25H into register A
MOV R3, #45 Load the decimal value 45 into R3 register.
MOV DPTR, #4521H Load DPTR with value 4521H
 2.Register Addressing Mode

 In this addressing mode registers are used to hold

the source and destination operands.
Examples:
MOV A,R0
MOV R2,A
MOV A,R5
ADD A,R7
Note:
Movement of data between Rn (n=0 to 7)registers
are not allowed.
 3.Direct Addressing Mode

In the Direct Addressing Mode, the source or

destination address is specified by using 8-bit
address in the instruction.
MOV 80H, R6
Comments:
send the content of register R6 to port P0 (Address of Port 0 is 80H)

MOV 90H, R7;

Comments:
send the content of register R6 to port P1 (Address of Port 1 is 90H)
 4.Register Indirect Addressing Mode
 In this addressing mode a register is used as a pointer
which indicates the address of the source or
destination operand.
 Here register is preceded by @ sign to indicate this
addressing mode.
MOV A,@R0
Move the content from memory(RAM) whose address
is specified through R0 register into accumulator
MOV @R1,B
Move the content of register B into memory(RAM)
whose address is specified through R1 register.
 5.Indexed Addressing Mode

In this addressing mode used in accessing data

elements of look-up table entries located in
the program ROM space of the 8051.
MOV A,@A+DPTR
The 16-bit register DPTR and register A are used
to form the address of the data element
stored in on-chip ROM.
 6.Implied Addressing Mode

 in the implied addressing mode, there will be a

single operand.
 These types of instruction can work on specific
registers only.
 These types of instructions are also known as
register specific instruction.
ExampleS: RL –Rotate left without carry
RR- Rotate right without carry
RLC- Rotate left with carry
RRC- Rotate right with carry
 Memory organization of 8051
microcontroller
 The 8051 microcontroller's memory is
divided into Program Memory(ROM)and Data
Memory.
Program Memory (ROM) size is 4KB which is
used to store program permanently.
Data Memory (RAM) size is 128 bytes which is
used for temporarily storing and keeping
intermediate results and variables.
RAM memory space allocation in the 8051 is as
follows

RAM size of 8051 microcontroller size is 128

bytes.
RAM size address range 00 to 7FH.
These 128 bytes are divided into three
different groups as follows.
A total of 32 bytes from locations 00 to 1FH
are set aside for register group and the stack.
A total of 16 bytes from locations 20H to 2FH
are set aside for bit addressable read/write
memory.
 A total of 80 bytes from locations 30H to 7FH
are used for read and write storage , or what
is called as a scratch pad.
These 80 locations of RAM are widely used for
the purpose of storing data and parameters by
8051 programmers.
8051 PSW/ FLAG REGISTER
 INSTRUCTION SET OF 8051
MICROCONTROLLER
The instructions of 8051 Microcontroller can
be classified into following groups.
1.Data Transfer Instructions
2.Arithmetic Instructions
3.Logical Instructions
4.Branching Instructions
5.Bit addressable Instructions
 1.Data Transfer Instructions
The Data Transfer Instructions are associated
with transfer with data between registers or
external program memory or external data
memory.
The Mnemonics associated with Data Transfer
are given below.
 2.Arithmetic Instructions
Using Arithmetic Instructions, we can perform
addition, subtraction, multiplication and
division.
The arithmetic instructions also include
increment by one, decrement by one and a
special instruction called Decimal Adjust
Accumulator.
Mnemonics associated with Logical
Instructions are as follows:
 3.Logical Instructions
The next group of instructions are the Logical
Instructions, which perform logical operations
like AND, OR, XOR, NOT, Rotate, Clear and
Swap.
Logical Instruction are performed on Bytes of
data on a bit-by-bit basis.
Mnemonics associated with Logical
Instructions are as follows:
 4.Branching Instructions
Branching instructions refer to the act of
switching execution to a different instruction
sequence as a result of executing a branch
instruction.
The three types of branching instructions are:
Jump (unconditional and conditional)
Call (unconditional and conditional)
Return (unconditional and conditional)
 5.Bit addressable Instructions
As the name suggests, Boolean or Bit
addressable Instructions will deal with bit
variables.
We know that there is a special bit-
addressable area in the RAM and some of the
Special Function Registers (SFRs) are also bit
addressable.
The Mnemonics corresponding to the Boolean
or Bit Manipulation instructions are:
• SETB bit
• CLR bit
• CPL bit (1’s complement)
 Interrupts in 8051 Microcontroller
 The 8051 microcontroller can recognize six
different events that cause the main program to
interrupt from the normal execution.
 These six sources of interrupts in 8051are:
1.Reset Interrupt -RST
2.Timer 0 overflow interrupt- TF0
3.Timer 1 overflow interrupt- TF1
4. External hardware interrupt- INT0
5. External hardware interrupt- INT1
6.Serial communication interrupt- RI/TI
 The Timer and Serial interrupts are internally
generated by the microcontroller.
 The external interrupts are generated by
additional interfacing devices or switches that are
externally connected to the microcontroller.
 When an interrupt occurs, the microcontroller
executes the interrupt service routine so that
memory location corresponds to the interrupt
that enables it.
 The Interrupt corresponding to the memory
location is given in the interrupt vector table
below.
 DIFFERENCE BETWEEN
MICROPROCESSOR & MICROCONTROLLER
8051 ASSEMBLY
LANGUAGE
PROGRAMMING
Q.1
Q.2
Q.3
Q.4