8086

Features of 8086
1) It is a 16 bit microprocessor
2) It has 20 address lines(A0-A19) and 16 data lines(D0-15)
3) Operated in Two modes – Minimum mode and maximum mode –(Math
Coprocessor)

4) Uses Pipelining method of instruction execution

5) Operating frequency is between 5MHz -10MHz
6) Operating voltage 5V
I1, I2,I3
8085- sequential
Pin Diagram
AD0 – AD15, A16, A17,A18, A19
Status Signals S3 and S4
A17/S4 A16/S3 Segment Identifier
0 0 Extra Segment Memory Access
0 1 Stack Segment
1 0 Code Segment
1 1 Data Segment

A18/ S5 – Interrupt Enable Flag

A19/ S6 – Low
BHE’ / S7 – Bus High Enable
S7 – Interrupt Acknowledge Signal
BHE A0 Function
0 0 Whole word
0 1 Upper byte from / to address
1 0 Lower byte from / to address
1 1 none

Ready: Peripheral ready to transfer data

INTR: Interrupt request
TEST: CPU execute WAIT instruction it will be LOW
CPU is in idle state it will be HIGH
NMI: Non Maskable Interrupt
CLK: Clock Generator (8284)
MN/MX ’: High- Minimum mode
Low- Maximum mode
Minimum Mode Signals
HOLD: Requisition to CPU, to release CPU buses for DMA transfer
HLDA: Hold acknowledgement
WR’: Write
M/IO’: High – Memory operations
Low – I/O operations
DT/R ’: Data Transmit and Receive
DEN ’: Data Enable
ALE:
INTA:
Maximum Mode Signals
QS1, QS0 – Queue Status
QS1 QS0 functions
0 0 No operation
0 1 First byte of opcode from queue
1 0 Empty the queue
1 1 Subsequent byte from queue

S0’, S1’, S2’

S2’ S1’ S0’ functions
0 0 0 Interrupt Acknowledgement
0 0 1 Read data from I/O port
0 1 0 Write data to I/O port
0 1 1 Halt
1 0 0 Code Access
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive

LOCK’: Other bus master can’t access/gain the CPU buses.

RQ’/GT0’ and RQ’/GT1’: Request / Grant
In Multiprocessor environment, other processors use these signals to
release the system bus.
Architecture of 8086
Architecture of 8086 consists of
BIU – Bus Interface Unit
EU – Execute Unit
BIU – Bus Interface Unit
BIU takes care of all data and addresses transfers on the buses for the EU like
sending addresses, fetching instructions from the memory, reading data from the
ports and the memory as well as writing data to the ports and the memory. EU
has no direction connection with System Buses so this is possible with the BIU.
EU and BIU are connected with the Internal Bus.
It has the following functional parts −
 Instruction queue − BIU contains the instruction queue. BIU gets upto 6
bytes of next instructions and stores them in the instruction queue. When
EU executes instructions and is ready for its next instruction, then it simply
 reads the instruction from this instruction queue resulting in increased
execution speed.
 Fetching the next instruction while the current instruction executes is
called pipelining.
 Segment register − BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds
the addresses of instructions and data in memory, which are used by the
processor to access memory locations. It also contains 1 pointer register
IP, which holds the address of the next instruction to executed by the EU.
o CS − It stands for Code Segment. It is used for addressing a memory
location in the code segment of the memory, where the executable
program is stored.
o DS − It stands for Data Segment. It consists of data used by the
program andis accessed in the data segment by an offset address or
the content of other register that holds the offset address.
o SS − It stands for Stack Segment. It handles memory to store data
and addresses during execution.
o ES − It stands for Extra Segment. ES is additional data segment,
which is used by the string to hold the extra destination data.
 Instruction pointer − It is a 16-bit register used to hold the address of the
next instruction to be executed.

EU (Execution Unit)

Execution unit gives instructions to BIU stating from where to fetch the data and
then decode and execute those instructions. Its function is to control operations
on data using the instruction decoder & ALU. EU has no direct connection with
system buses as shown in the above figure, it performs operations over data
through BIU.
Let us now discuss the functional parts of 8086 microprocessors.

ALU

It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT
operations.

Flag Register
It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status
according to the result stored in the accumulator. It has 9 flags and they are
divided into 2 groups − Conditional Flags and Control Flags.

Conditional Flags

It represents the result of the last arithmetic or logical instruction executed.

Following is the list of conditional flags −
 Carry flag − This flag indicates an overflow condition for arithmetic
operations.
 Auxiliary flag − When an operation is performed at ALU, it results in a
carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 –
D7), then this flag is set, i.e. carry given by D3 bit to D4 is AF flag. The
processor uses this flag to perform binary to BCD conversion.
 Parity flag − This flag is used to indicate the parity of the result, i.e. when
the lower order 8-bits of the result contains even number of 1’s, then the
Parity Flag is set. For odd number of 1’s, the Parity Flag is reset.
 Zero flag − This flag is set to 1 when the result of arithmetic or logical
operation is zero else it is set to 0.
 Sign flag − This flag holds the sign of the result, i.e. when the result of the
operation is negative, then the sign flag is set to 1 else set to 0.
 Overflow flag − This flag represents the result when the system capacity is
exceeded.

Control Flags

Control flags controls the operations of the execution unit. Following is the list of
control flags −
 Trap flag − It is used for single step control and allows the user to execute
one instruction at a time for debugging. If it is set, then the program can
be run in a single step mode.
 Interrupt flag − It is an interrupt enable/disable flag, i.e. used to
allow/prohibit the interruption of a program. It is set to 1 for interrupt
enabled condition and set to 0 for interrupt disabled condition.
  Direction flag − It is used in string operation. As the name suggests when it
is set then string bytes are accessed from the higher memory address to
the lower memory address and vice-a-versa.

General purpose register

There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL.
These registers can be used individually to store 8-bit data and can be used in
pairs to store 16bit data. The valid register pairs are AH and AL, BH and BL, CH
and CL, and DH and DL. It is referred to the AX, BX, CX, and DX respectively.
 AX register − It is also known as accumulator register. It is used to store
operands for arithmetic operations. AH,AL
 BX register − It is used as a base register. It is used to store the starting
base address of the memory area within the data segment. BH, BL
 CX register − It is referred to as counter. It is used in loop instruction to
store the loop counter.
 DX register − This register is used to hold I/O port address for I/O
instruction.

Stack pointer register

It is a 16-bit register, which holds the address from the start of the segment to
the memory location, where a word was most recently stored on the stack.
Flag Register (PSW- Program Status Word)
D15 D1 D0

- - - - O D I T S Z - AC - P - C

16 bit registers 65536= -32768 to + 32768 Signed Operation

AX
BX
FFFFF -> 00000
CX
DX
AH – High byte, AL – Low byte
BH, BL
T- Trap flag : Single step execution
I- Interrupt flag: sets when any interrupt occurs
D- Direction flag: String manipulation instructions, sets – auto decrement mode
O- Overflow flag : sets if results is beyond the representation.

How to calculate 20bit physical address?

Physical address = segment register X 10 + Contents of pointer/index register
Segment register and their pointer/index register
CS: IP
DS: BX, SI, DI, 8 or 16 bit displacement/ offset , BP
ES: DI for string manipulations
SS: SP, BP

CS = 1000 H ; IP = 2FFF H
Then PA= CSx10 + IP
1000x10 + 2FFF= 12FFF H
10000+2FFF= 12FFF H

Addressing modes of 8086

The way for which an operand is specified for an instruction in the accumulator, in
a general purpose register or in memory location, is called addressing mode.

Addressing modes supported by 8086 are:

Immediate, Register, Direct, Register Indirect, Based Addressing, Indexed

Addressing, Based Indexed Addressing, Based Indexed with Displacement

Register Addressing: In register addressing, the operand is placed in one of the

16-bit or 8-bit general purpose registers.

Example

o MOV AX, CX
o ADD AL, BL
o ADD CX, DX

Immediate Addressing: In immediate addressing, the operand is specified in the

instruction itself.

Example

o MOV AL, 35H

o MOV BX, 0301H
o MOV [0401], 3598H
o ADD AX, 4836H

Direct Addressing: In direct addressing mode, the operand offset is given in the
instruction as an 8-bit or 16-bit displacement element.

Example

MOV CL, [4000] ; 4000- Memory location,

o ADD AL, [0301]

The instruction adds the content of the offset address 0301 to AL. the operand is
placed at the given offset (0301) within the data segment DS.
Register Indirect Addressing: The operand's offset/ displacement is placed in any
one of the registers BX, BP, SI or DI as specified in the instruction.

Example

o MOV AX, [BX] ; MOV AX, BX

It moves the contents of memory locations addressed by the register BX to the

register AX.

Based Addressing: The operand's offset is the sum of an 8-bit or 16-bit

displacement and the contents of the base register BX or BP. BX is used as base
register for data segment, and the BP is used as a base register for stack segment.

Effective address (Offset) = [BX + 8-bit or 16-bit displacement].

Example

o MOV AX, [BX+05]; an example of 8-bit displacement. [5000+05]

o MOV DL, [BP + 1346H]; example of 16-bit displacement. [5005+1346]=

Indexed Addressing: The offset of an operand is the sum of the content of an

index register SI or DI and an 8-bit or 16-bit displacement.

Offset (Effective Address) = [SI or DI + 8-bit or 16-bit displacement]

Example

o MOV AX, [SI + 05]; 8-bit displacement.

o MOV AX, [DI + 1528H]; 16-bit displacement.

Based Indexed Addressing: The offset of operand is the sum of the content of a
base register BX or BP and an index register SI or DI.

Effective Address (Offset) = [BX or BP] + [SI or DI]

Here, BX is used for a base register for data segment, and BP is used as a base
register for stack segment.

Example
 o ADD AX, [BX + SI]; [BP+SI]
o MOV CX, [BP + DI] [BX+DI]

Based Indexed with Displacement: In this mode of addressing, the operand's

offset is given by:

Effective Address (Offset) = [BX or BP] + [SI or DI] + 8-bit or 16-bit displacement

Example

o MOV AX, [BX + SI + 05]; 8-bit displacement

o MOV AX, [BP + DI + 1235H]; 16-bit displacement

DS= 3100H, BX=4900H

3200X10= 31000= 0011 0010 0000 0000 0000
4900 0100 1001 0000 0000
35900
Compute 20 bit physical address
DS: 3000, ES: 5000, BP:4202, BX=9600, SI: 6002 DI: 8003
1) MOV CX, [BP+2010] = 3000x10 + (4202+2010)= 36212H
2) MOV AX, [BX+SI]= 3000x10+(9600+6002)
3) MOV DX, ES: [SI+2009]
4) MOV AX, [BP+DI+1010]

Instruction Set of 8086

Data transfer, arithmetical, logical, branching, processor control and string
manipulations
Data transfer instructions
 I) MOV Destination, Source
Source: 8 bit or 16 bit immediate, register, memory locations
Destination: register, memory locations
MOV AX, 2233H; 33-> AL, 22-> AH
MOV AL,2233H
MOV AX, CX
MOV AX, [2345] ; 2345-> AL, 2346-> AH
MOV AL, [2345]
MOV AX, [SI]
MOV [4345], DL
MOV [BP], DX
MOV [3336], [DI]
Invalid: MOV DS, 2266
MOV AX, 2266
MOV DS, AX
II) PUSH Source
Source: all registers, memory locations
PUSH DX
PUSH [BP]
III) PUSHF
IV) POP Destination
POP BX
POP DS
 POP [SI]
V) XCHG destination, source
Source: registers, memory locations
Destination: registers, memory locations
XCHG [4505], AX
XCHG AX, CX
VI) LAHF (load the lower byte of flag register to AH)
VII) SAHF (save AH to lower byte of flag register)
IX) IN destination, source (input data from I/O devices)
Destination: AL/AX,
Source: 8bit port address/ DX
IN AL, 08H
IN AX, DX
X) OUT destination, source (output the data to I/O devices)
Destination: 8bit port address/DX
Source: AL/AX
OUT 98H, AL
OUT DX, AX
XI) LEA destination, Source
Destination: pointer/index registers [SI/DI/BX/BP]
Source: offset address
LEA DI, 8900H
LEA BX, [SI]+[DI]
XII) LDS reg16, memory address
 LDS SI, [2400]
XIII) LES reg 16, memory address
LES DI, [3500]

Compute 20 bit physical address

DS: 3000, ES: 5000, BP:4202, BX=9600, SI: 6002 DI: 8003
1) MOV CX, [BP+2010]
(3000X10) + 4202+2010= 30000+6212= 36212
2) MOV AX, [BX+SI]
9600+6002= F602+30000=3F602
3) MOV DX, ES: [SI+2009]
6002+2009= 800B+ 50000= 5800B
4) MOV AX, [BP+DI+1010]
30000 +4202+8003+1010= D 215+30000
3D215
Arithmetical Instructions
Addition, subtraction, multiplication, division, increment, decrement.
I) ADD destination, source
Source: immediate, register, memory locations
Destination: register, memory locations
ADD AL, 9FH; AL  (AL)+9F
ADD BX, 1230H; BX(BX)+1230
ADD AX, CX
ADD CX, [3300]
ADD [SI], DX
II) ADC destination, source
Source: immediate, register, memory locations
Destination: register, memory locations
ADC AH, 9FH; AH  (AH ) + 9F + (CY)
ADC BX, 1230H; BX(BX)+1230+ (CY)
ADC AX, CX
ADC CX, [3300]
ADC [SI], DX
III) SUB destination, source
Source: immediate, register, memory locations
Destination: register, memory locations
SUB BL, 9FH; BL  (BL) - 9F
SUB BX, 1230H; BX(BX) - 1230
SUB AX, DX
SUB CX, [3300]
SUB [SI], DX
IV) SBB destination, source
Source: immediate, register, memory locations
Destination: register, memory locations
SBB BH, 9FH; BH  (BH) - 9F – (CY)
SBB BX, 1230H; BX(BX) – 1230 – (CY)
SBB AX, DX
 SBB CX, [3300]
SBB [SI], DX
V) INC source
Source: register, memory locations
INC CL
INC AX
INC [BP]
VI) DEC source
Source: register, memory locations
DEC DH
DEC BX
DEC [SI]
VII) NEG Source Negate
Source: register, memory locations
NEG AH
NEG [DI]
IX) MUL Source
Source: register, memory locations
Destination: AX, DX
MUL CH ; ( AX AL x CH)
MUL CX; (DX: AX AX x CX)
X) IMUL Source
Source: register, memory locations
 IMUL BH ; ( AX AL x BH)
IMUL CX; (DX: AX AX x CX)
XI) DIV Source
Source: register, memory locations (divisor)
AX (16bits), DX-AX(32bits)
Q: AL R: AH (16/8)bits
Q: AX R: DX (32/16)bits
DIV CL ; AX/CL; Q-AL, R-AH
XII) IDIV Source
Source: register, memory locations (divisor)
AX (16bits), DX-AX(32bits)
Q: AL R: AH (16/8)bits
Q: AX R: DX (32/16)bits
XIII) DAA ( Decimal Adjust After Addition) [packed BCD] 69
XIV) DAS (Decimal Adjust After Subtraction)
XV) AAA ( ASCII Adjust After Addition) [unpacked BCD]-69-> 06 09
XVI) AAS
XVII)AAD
XVIII) AAM
Write a program to add two 16 bit numbers present in offset address: 3000 and
4000. Store the sum 5000.
Write a program to divide 16bit (dividend) number present in 5000 and 8bit
divisor in 6000. Store quotient in 6200 and remainder in 6021.
Logical Instructions
AND, OR, XOR, NOT, TEST, Shift and rotate
I) AND Destination, Source
Source: immediate, register, memory locations
Destination: register, memory locations
AND AL, 9FH; AL  (AL) ᴧ 9F
AND BX, 1230H; BX(BX) ᴧ 1230
AND AX, CX; AX (AX) ᴧ (CX)
AND CX, [3300]; CX (CX) ᴧ (3300)
AND [SI], DX; (SI) ((SI) ᴧ (DX)
II) OR Destination, Source
Source: immediate, register, memory locations
Destination: register, memory locations
III) XOR Destination, Source
Source: immediate, register, memory locations
Destination: register, memory locations
IV) NOT Source/destination
Source: register, memory locations
NOT AL
NOT BX
NOT [SI]
V) TEST Destination, Source
Source: immediate, register, memory locations
Destination: register, memory locations
 TEST AL, 80H ; AL ᴧ 80H
Shift instructions
VI) SAL/SHL Source/destination, count (Arithmetic shift left, Logical shift left)
Source: register, memory locations
SAL AL, 2 7F= 0111 1111 ; SAL = 1111 1110= FE
SHL [2303], 2 1111 1100
VII) SAR Source/destination, count [Arithmetic shift Right]
Source: register, memory locations
SAR AL, 1 ; 8F= 1000 1111= SAR= 1100 0111 = C7 ;
SAR CL, 2
MSB bit is placed in the vacant bit position.
VII) SHR Source/destination, count [Logical shift Right]
Source: register, memory locations
SHR AL, 1; F0 1111 0000 ; SHR- 0111 1000- 78
SHR CL, 2
MSB bit is placed with 0
VIII) ROR Source/destination, count [Rotate right]
Source: register, memory locations
ROR BL, 1 MSB - LSB--- 1111 0000- ROR- 0111 1000 cy-0
ROR DX, 2
IX) RCR Source/destination, count [Rotate right with carry]
Source: register, memory locations ; LSB-> CY, CY-> MSB
RCR BL, 1
 RCR DX, 2
X) ROL Source/destination, count [Rotate left]
Source: register, memory locations
ROL BL, 1
ROL DX, 2
XI) RCL Source/destination, count [Rotate left with carry]
RCL AH, 1
RCL DH, 2
Branching Instructions
UnConditional
JMP Target address JMP 7080H ( IP-7080)= 6000-7080=D080h
Target address : 8 bit – [-128 to 127] Short jump
16 bit – [-32KB to + 32KB] Near jump
JMP 2000:588F Far jump
Conditional
I) JZ / JE Target address (short) [ZF=1]
ii) JNZ /JNE Target address (short) [ZF=0]
iii) JC / JNAE Target address (short) [CF=1]
iv) JNC / JNB Target address (short) [CF=0]
v) JS Target address (short) [SF=1]
vi) JNS Target address (short) [SF=0]
vii) JO Target address (short) [OF=1]
viii) JNO Target address (short) [OF=0]
ix) JP /JPE Target address (short) [PF=1]
x) JNP/JPO Target address (short) [PF=0]
xi) JCXZ Target address (short) [CX=0]
xii) JNL Target address (short) [SF=OF]
xiii) JGE Target address (short) [CF=OF, ZF=1]
xiv) JG Target address (short) [ZF=0 and CF=OF]
xv) JA Target address (short) [CF =0 and ZF=0]
xvi) JNA Target address (short) [CF=1 and ZF=1]

Program 1
MOV AX, [3000] ( Invalid = ADD [3000], [4000] )
ADD AX, [4000]
MOV [5000], AX
Program 2
Dividend: 5000H; Divisor: 6000; Quotient: 6200; remainder: 6021
MOV AX, [5000]
DIV [6000]
MOV [6200], AL
MOV [6021], AH

XVIII) CALL 8bit/16bit/32 bit offset address; CALL 80, CALL 23EF
CALL 2000:588F
XIV) RET
XX) IRET - Return from ISR- Interrupt Service Routine
LOOP instructions
1) LOOP 8bit address; Count value in the counter register, CX=9
2) LOOPE / LOOPZ 8bit address ( CX!=0 and ZF=1)
3) LOOPNE / LOOPNZ (CX!=0 and ZF=0)

MOV CX, 9
Label1: MOV AL, BL
…..

LOOP label1
Processor control instructions
I) CLC – clear carry flag
II) CMC - complement CF
III) STC- Set CF
IV) CLD - Clear Direction flag
V) STD – Set DF
VI) CLI – Clear Interrupt flag
VII) STI – Set IF
VIII) HLT
IX) WAIT
X) LOCK
XI) NOP
XII) ESC
8087- numeric coprocessor.. instruction set, architecture
ESC: instructions of coprocessor/ slave processor’s instruction
String Manipulation Instructions
Default Source Segment and Index Register: COLLEGE
Data Segment (DS) and Source Index (SI) Register
Default Destination Segment and Index Register:
Extra Segment (ES) and Destination Index (DI) Register
Direction flag (DF), DF=0 -> Auto increment mode, DF=1 -> Auto decrement mode
1) MOVSB - Move String Bytes from DS:[SI] to ES:[DI]
2) MOVSW - Move the String Word from DS:[SI] to ES:[DI] 2300 -> 4000,
2301->4001; DF=0
DF=1 ; 2300 -> 4000, 22FF -> 3FFF
3) CMPSB – Compare the String Bytes;
4) CMPSW - Compare the String Words;
5) LODSB – Load the String bytes at DS:[SI] into AL
6) LODSW - Load the String Words at DS:[SI] into AX
7) STOSB – Store the String bytes in AL at ES:[DI]
8) STOSW - Store the String Words in AX at ES:[DI]
9) SCASB – Scan the string byte [ES:[DI] with AL]
10) SCASW - Scan the string word [ES:[DI] with AX]
11) REP – Repeat (Repeat the string instructions until CX becomes 0) CX=5
REP MOVSB;
12) REPE or REPZ – Repeat on Equal/ Repeat on zero flag is 1
 (Repeat the string instructions if CX is not equal to 0 and ZF=1)
13) REPNE or REPNZ – Repeat on Not Equal/Repeat on Not Zero flag
(Repeat the string instructions if CX is not equal to 0 and ZF!=0)

REPNE SCASB
String size is 8bytes, DS-5000, ES- 6000, SI-0100, DI-0200
MOV CX, 0008
MOV AX, 5000H
MOV DS, AX
MOV AX, 6000H
MOV ES, AX
MOV SI, 0100H
MOV DI, 0200H
CLD
REP MOVSB
HLT