LAB01 report.

Name: Le Duc Vu Student’s ID: 18021443

Assignment: LAB01 Group 5

1. 1-bit comparator
 1-bit comparator truth table

equi x y eqo
1 0 0 1
1 1 1 1
x x x 0
Table 1:truth table of the 1-bit comparator with 3 inputs

The minimum logic function derived from the truth table is:

<=>
 Simulation of 1-bit comparator with the truth table above.

Figure 1: Simulation result of the 1-bibt comparator.

 1-bit comparator with structural description

ARCHITECTURE dataflow OF Comparator2 IS

BEGIN -- dataflow

-- Students complete the following line

eqo <= (NOT (x XOR y)) AND eqi;

END dataflow;

ARCHITECTURE structural of Comparator2 is

component inv is
GENERIC (
 delay : TIME := 1 NS);

PORT (
i : IN STD_LOGIC;
o : OUT STD_LOGIC);
end component;

component nand2 is
GENERIC (
delay : TIME := 2 NS);

PORT (
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
o : OUT STD_LOGIC);
end component;

component nor2 is
GENERIC (
delay : TIME := 2 NS);

PORT (
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
o : OUT STD_LOGIC);
end component;

SIGNAL check1: STD_LOGIC;

SIGNAL check2: STD_LOGIC;
SIGNAL check3: STD_LOGIC;
SIGNAL check4: STD_LOGIC;
SIGNAL check5: STD_LOGIC;

begin
na1 : nand2 PORT MAP(i1 => x, i2 => y, o => check1);
no1 : nor2 PORT MAP(i1 => x, i2 => y, o => check2);
inv1 : inv PORT MAP(i => check2, o => check3);
na2 : nand2 PORT MAP(i1 => check1, i2 => check3, o => check4);
na3 : nand2 PORT MAP(i1 => check4, i2 => eqi, o => check5);
inv2 : inv PORT MAP(i => check5, o => eqo);

end structural;

Table 2: structural architecture of the 1-bit comparator.

 Figure 2: simulation result of the new 1-bit comparator.

Looking at the waveform of figure 2, the outputs of the 1-bit comparator seem a bit different.
This is because each logic gate, XOR, INV, NAND all have some certain propagation delay.
However, but the final outputs is the same as that of the 1-bit comparator with no delays by the
end of each clock, since the clock period is longer than the critical path of the circuit.

2. Generate iterative structure

ARCHITECTURE dataflow OF Comparator2 IS

BEGIN -- dataflow

-- Students complete the following line

eqo <= (NOT (x XOR y)) AND eqi;

END dataflow;

ARCHITECTURE structural of Comparator2 is

component inv is
GENERIC (
delay : TIME := 1 NS);

PORT (
i : IN STD_LOGIC;
o : OUT STD_LOGIC);
end component;

component nand2 is
GENERIC (
 delay : TIME := 2 NS);

PORT (
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
o : OUT STD_LOGIC);
end component;

component nor2 is
GENERIC (
delay : TIME := 2 NS);

PORT (
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
o : OUT STD_LOGIC);
end component;

SIGNAL check1: STD_LOGIC;

SIGNAL check2: STD_LOGIC;
SIGNAL check3: STD_LOGIC;
SIGNAL check4: STD_LOGIC;
SIGNAL check5: STD_LOGIC;

begin
na1 : nand2 PORT MAP(i1 => x, i2 => y, o => check1);
no1 : nor2 PORT MAP(i1 => x, i2 => y, o => check2);
inv1 : inv PORT MAP(i => check2, o => check3);
na2 : nand2 PORT MAP(i1 => check1, i2 => check3, o => check4);
na3 : nand2 PORT MAP(i1 => check4, i2 => eqi, o => check5);
inv2 : inv PORT MAP(i => check5, o => eqo);

end structural;

Figure 3: two n-bit input comparator.

The figure below is the simulation result of the circuit generated from the code above
 Figure 4: simulation result of the two n-input comparator.

Encoder

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY encoder IS

PORT (
data_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
segments_out : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));

END encoder;

ARCHITECTURE beh OF encoder IS

BEGIN -- beh

encoder_proc: process(data_in)
begin
case data_in is
when "0000" => segments_out <= "0000001"; -- "0"
when "0001" => segments_out <= "1001111"; -- "1"
when "0010" => segments_out <= "0010010"; -- "2"
when "0011" => segments_out <= "0000110"; -- "3"
when "0100" => segments_out <= "1001100"; -- "4"
when "0101" => segments_out <= "0100100"; -- "5"
when "0110" => segments_out <= "0100000"; -- "6"
 when "0111" => segments_out <= "0001111"; -- "7"
when "1000" => segments_out <= "0000000"; -- "8"
when "1001" => segments_out <= "0000100"; -- "9"
when "1010" => segments_out <= "0000010"; -- a
when "1011" => segments_out <= "1100000"; -- b
when "1100" => segments_out <= "0110001"; -- C
when "1101" => segments_out <= "1000010"; -- d
when "1110" => segments_out <= "0110000"; -- E
when "1111" => segments_out <= "0111000"; -- F
when others => null;
end case;
end process encoder_proc;

END beh;
Figure 5: encoder of 7-segment LED.

Testbench

library ieee;
use ieee.std_logic_1164.STD_LOGIC_VECTOR;
use ieee.std_logic_1164.all;
use ieee.numeric_std_unsigned;
use ieee.numeric_std.all;

-------------------------------------------------------------------------------

ENTITY encoder_tb IS

END encoder_tb;

-------------------------------------------------------------------------------

ARCHITECTURE testbench OF encoder_tb IS

COMPONENT encoder
PORT (
data_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
segments_out : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END COMPONENT;

-- component ports
SIGNAL data_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL segments_out : STD_LOGIC_VECTOR(6 DOWNTO 0);

-- clock
signal Clk : std_logic := '1';

BEGIN -- testbench
 -- component instantiation
DUT: encoder
PORT MAP (
data_in => data_in,
segments_out => segments_out);

-- clock generation
Clk <= not Clk after 10 ns;

-- waveform generation
WaveGen_Proc: process
begin
-- insert signal assignments here
for i in 0 to 15 loop
data_in <= std_logic_vector(to_unsigned(i,4)); wait until Clk = '1';
end loop;
end process WaveGen_Proc;

END testbench;

-------------------------------------------------------------------------------

CONFIGURATION encoder_tb_testbench_cfg OF encoder_tb IS

FOR testbench
END FOR;
END encoder_tb_testbench_cfg;
Figure 6: testbench of the 7-segment LED.

Figure 7: seven segment led encoder simulation result.

In the simulation above, I changed the data_in to human-readable format, which is numbers in base
10, but the segments of the 7-segment LED remain in binary format for the sake of clarity.