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28-32 GHz 5G LNA for Massive MIMO

Applications
Shahid Jamil, Muhammad Usman, Hamza Atiq, and Rashad Ramzan, Sr., Member, IEEE

to overcome these constraints. This stimulates the application

Abstract— Recent advancements in the hardware integration of more advanced CMOS technology nodes by RFIC
of RF communication systems have been driven by the designers in order to take advantage of Moore's law of area,
requirements of high data rates as well as efficient utilization power consumption, and digital logic speed scaling [5]. To
of bandwidth. 5G networks have been developed as a follow-on
to 4G networks because they deliver hundred times better data meet the technology trends of mm-wave 5G IC design,
rates as well as lower latency as compared to the existing 4G CMOS integration of SoC transceivers must give greater
networks. LNA is regarded the most critical component of 5G matching between active and passive components.
front-end module because it defines the overall transceiver In this scenario, a compact LNA with a very small
sensitivity. This article presents a mm-Wave (28-32 GHz) LNA silicon footprint along with lower power requirements is
for 5G applications. The proposed LNA uses cascode topology, essential that can exhibit superior performance throughout a
used to increase output resistance, which in turn increases the
gain as well as the isolation between input and output nodes. wide range of frequencies. LNA is regarded as the most
This decreases the effect of miller feedback capacitance. critical component of 5G front-end module because as it
Likewise, voltage to current feedback reduces the defines the overall transceiver sensitivity [6]. Therefore, 5G
transconductance required for input matching. The noise at the
input and output nodes becomes correlated and, by design, the Oxygen
circuit partially cancels the channel thermal noise of the cascode Absorption Band
transistors using feedback. The proposed LNA is designed and
fabricated using TSMC 65nm Bulk CMOS technology.
Measurement results show that the designed LNA achieves a Beach Front Water Vapors
peak S21 of 18.48dB with a wideband 3-dB bandwidth in the Spectrum Absorption Band
range of 26 to 33.6 GHz. The NF is also less than 3dB over the
entire band of interest. The proposed LNA occupies a 300×100
µm2 area with a power consumption of 17 mW including the 28-32 65-163 164-200
output buffer stage. GHz GHz GHz
Index Terms— LNA, Wideband LNA, 5G LNA, mmWave,
CMOS LNA, 65nm CMOS, MIMO LNA Minimum Atmospheric
3GHz Absorption Band 200GHz
I. INTRODUCTION
Fig. 1. Available mm-wave frequency spectrum

I n recent decades, the fifth-generation (5G) wireless

technology has evolved, which could deliver better data
rates as well as reduced latency as compared to 4G
technology [1], [2]. Similarly, millimeter-band frequencies TRX 1
are currently becoming more popular which provide higher
data rates as well as better resolution for a wide spectrum of TRX 2
applications, including augmented reality (AR), smart
homes, self-driving vehicles etc. [3]. Fig. 1 depicts the mm- TR
wave spectrum, which also encompasses merits and demerits TRX 3
of using certain frequency bands for communication. Based
on the suggested frequency spectrum for 5G by [4], the 28- TRX N
32GHz mm-wave band was chosen in this study for LNA
design due to the property of low atmospheric absorption in
this band.
In 5G network-based systems, more than one Phase
PA Shifter
transceiver (TRX) is used to implement massive multiple-
input multiple-output (MIMO) and phased array technique.
The architecture of a 5G phased-array transceiver is shown in ϕ
Fig. 2. Hence, IC transceivers in the mm-wave 5G frequency
bands must be modified such that they consume less LNA
area, power and yield higher linearity. The precise
monolithic unification of RF, analog, and digital portions of Fig. 2. Block diagram of the phased-array transceiver
the transceiver in a fully integrated SoC system can be used
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LNA is anticipated to deliver a certain amount of gain VDD VDD

without adding any significant noise in the transceiver.
Likewise, reduced VDD in modern CMOS technologies also ZL ZL
limits the circuit topologies that may be used for LNA.
RFOUT RFOUT
Furthermore, in 5G massive MIMO systems, an inductor-free
VG
version of LNA is also desirable because it consumes lower RFIN
area.
Wideband LNAs provide a flat gain and impedance
(a) (b) RFIN
matching over the entire bandwidth which can be achieved
using various techniques i.e., common source with resistive
Fig. 3. Different topologies of LNA: (a) CS LNA with resistive input
input termination, feedback, common gate and input filter [7]. termination, (b) CG LNA
Common source (CS) LNA with input resistive
termination is the easiest method to achieve 50 Ω wideband
impedance matching by adding a shunt resistor of 50 Ω with VDD
the input of LNA, as shown in Fig. 3(a). This resistor divides
the input signal by half and adds its thermal noise, i.e., ZL
degrades the noise performance of LNA or higher NF. This
method results in a trade-off between input matching and Feedback RFOUT
noise figure optimization [7].
Similarly, common gate (CG) LNA, illustrated in Fig. 3(b), RFIN
provides the optimal wideband input impedance matching
through the resistance looking into its source. The
mathematical expression for input impedance in common
Fig. 4. LNA with feedback topology
gate LNA is given in (1). The CG LNA intrinsically provides
wideband input impedance matching at the cost of higher NF,
lower gain, and higher power consumption [8]. The VDD
mathematical expressions for NF and gain (A) are given in
(2) and (3), respectively. The NF of CG LNA can only be ZL
improved by increasing the transconductance (gm) of the
transistor yielding a trade-off with power and input
RFOUT
impedance matching [9].
1
𝑍𝑖𝑛 = (1) RFIN Filter
𝑔𝑚
𝛾
𝑁𝐹 = 10𝑙𝑜𝑔⁡(1 + ) (2)
𝛼𝑅𝑠 𝑔𝑚 Fig. 5. LNA topology using filter
𝐺𝑎𝑖𝑛⁡ = 𝐴 = 𝑔 𝑍 (3)
𝑚 𝐿
Where 𝑔𝑚 is transconductance, γ is the parameter of noise, This paper is organized as follows. In section-II, different
α is the ratio of transconductance (𝑔𝑚 ) to drain-to-source architectures of state-of-the-art wideband LNAs are
conductance (𝑔𝑑𝑠 ) at zero bias and 𝑅𝑠 is source resistance. discussed. Section-III presents the proposed
Negative feedback in the LNA breaks the trade-off circuit/architecture of the LNA. The measurement results for
between the noise figure optimization and power the proposed LNA are discussed in section-IV, followed by
consumption in wideband LNA [10]. Theoretically, the best section-V, in which performance comparison with state-of-
performance can be achieved using a lossless transformer. the-art LNAs is provided. The last section-VI concludes the
But practically, a wideband transformer is lossy and occupies paper.
a large area. Therefore, lossy feedback like a resistor, resistor-
capacitor, reactive feedback, and transistor is better to break II. STATE-OF-THE-ART WIDEBAND LNAS
this trade-off. Feedback supports wideband input impedance An inductor-less wideband LNA for sub 6GHz frequencies
matching without dividing the signal through a noisy was presented in [13] employing the techniques of current
attenuator before amplification [7]. Hence, its noise reuse for the reduction of current through the load resistor and
performance is better than the previous topology. Fig. 4 shows at the same time improving the gain, noise performance, and
the feedback LNA. power consumption. Similarly, 50Ω wideband input
Filter LNA, illustrated in Fig. 5, incorporates filter at the matching and partial noise cancellation were achieved in [13]
input or output of LNA and allows it to resonate over the by utilizing the common drain stage in the feedback path.
entire bandwidth for wideband impedance matching. In [11], A gm-boosting based Common Gate (CG) LNA using a
the use of an LC network was demonstrated to achieve a passive transformer was proposed in [14]. This technique is
bandwidth of 6-10 GHz with constant gain. This topology is utilized to meet the trade-off between noise and input
generally implemented with a CS transistor with an inductive matching while consuming lower power. Similarly, [15]
degenerated stage. It exhibits good NF and power presented a design of low power LNA in 65nm CMOS using
consumption with higher gain and input impedance matching multi-cascode configuration along with noise reduction
over the entire bandwidth [12].
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VDD
topology. Inductors have been designed and positioned
between the transistors of the cascode arrangement to
L1 CO R2
decrease the NF, while at the same time increasing the small-
signal gain. Based on this technique, power of 28.8 mW is M2
consumed while they achieved a peak gain of 14.3 dB with a M4
noise figure of 3.8 dB at 38 GHz. The chip size of the M1 C1 RFout
proposed LNA (comprising all the testing pads) was 0.55 x C0
RFin Vb2
0.45 mm2 [15]. M0 M5
[16] proposed an LNA for millimeter-wave (mm-Wave) Vb1
Cgs
band utilizing gm-boosting technique along with L0 M3
transformers. It not only improves the stability of the circuit
but also alleviates the gain while suppressing the noise figure.
Likewise, a novel architecture for wideband input impedance
Fig. 6. Schematic of proposed mm-wave LNA for 5G applications
matching utilizing two common gate (CG) transistors was
presented in [17]. One of the CG transistors is positioned
Due to high quality factor of the inductors, and cascode
above the other in a current reuse mode, such that they appear
configuration the voltage gain is increased by shunt peaking.
parallel at the input. By using this technique, the input
In the proposed LNA, M0 is used as a main transistor
transconductance needed is reduced by half as
which provides gain. M1 is used as a cascode transistor. This
compared to the basic CG LNA without any impact on the
cascode topology increases output resistance, which in turn
overall gain for each NMOS transistor.
helps to augment gain, while also increasing isolation
A compact wideband low-noise amplifier (LNA) using
between input and output nodes. This results in lowering
source degeneration topology for the purpose of bandwidth
minimizing the effect of miller feedback capacitance.
extension was presented in [17]. Transformer-based gate-
The transistor (M2) is utilized for voltage to current
drain feedback is utilized to attain a wideband response by
feedback, which ultimately reduces the transconductance
achieving the maximum gain at high frequencies. Likewise,
required for input matching. The noise at the input and output
two resonance points (using transformer) independently
nodes becomes corelated due to feedback and, by design, the
positioned at low and high frequencies inside the band of
circuit partially cancels the channel thermal noise of the
operation are utilized to achieve wideband input matching.
cascode transistors. The transistors (M4 and M5) are used as
Likewise, [18] presented a novel continually-stepped variable
output buffer stage (common drain) to provide 50Ω matching
gain (CSVG) 2-stage LNA by incorporating a tunable-
for testing purposes.
transformer at the 2nd-stage for millimeter-wave(mm-Wave)
operation. A. Gain Analysis of Proposed LNA
Another wideband LNA based on complementary common Small signal model of main amplifier portion of proposed
gate (CCG) stage and common source (CS) stages was LNA is provided in Fig. 7. To perform gain analysis of
presented in [19]. In this architecture, the CCG stage saves dc proposed LNA, it is assumed that input and output
power by the current reuse technique. Similarly, replacing capacitances are resonated out by the parallel inductors L0
two inductors with a single transformer reduces chip area. and L1 respectively. Mathematical expression of 𝑣𝑜1 after
Load reuse technique is utilized to simultaneously achieve applying KCL at node 𝑣𝑜1 is given in (4).
wideband gain, wideband input matching, and flat noise
𝑔𝑚0
figure (NF). In the similar manner, an LNA for 5G 𝑣𝑜1 = − ( ) ∗ 𝑣𝑅𝐹𝑖𝑛 (4)
applications is presented in [19] utilizing positive feedback, 𝑔𝑑𝑠0 + 𝑔𝑚1
which inherently cancels the noise produced by the input CG Similarly, mathematical expression of 𝑣𝑜 after applying KCL
transistor. at node 𝑣𝑜 ⁡is given in (5).
The LNA designs presented by [15], [18], [19] and [20]
consume a relatively higher silicon area, however power 𝑣𝑜 = 𝑔𝑚1 𝑅1 𝑣𝑜1 (5)
consumption of LNA design presented by [16] is higher. The After substituting value of 𝑣𝑜1 from (4) in (5) and re-
proposed LNA design aims to improve both of these aspects arranging it, mathematical expression of small signal gain (A)
simultaneously while maintaining all other performance for the proposed LNA is obtained as given in (6).
parameters like gain, NF, linearity and BW.
𝑣𝑜 𝑔𝑚0 𝑔𝑚1 𝑅1
𝐴= =− (6)
III. PROPOSED LNA DESIGN FOR 5G APPLICATIONS 𝑣𝑅𝐹𝑖𝑛 𝑔𝑑𝑠0 + 𝑔𝑚1
Due to wideband nature, low power, and excellent noise The effect of output resistance of cascode (𝑅𝑜𝑢𝑡 ) is ignored
performance, the circuit topology presented by [13] was in (6). Now, by incorporating the value of 𝑅𝑜𝑢𝑡 , the
modified or this mm-wave 5G LNA design. Since the mathematical expression of gain given in (6) can be re-written
parasitic effect of the transistor’s gate to source capacitance as given in (7).
becomes very high, therefore, an inductor-less design is not 𝑔𝑚0 𝑔𝑚1 (𝑅1 ||𝑅𝑜𝑢𝑡 )
possible. Therefore, in the proposed LNA as shown in Fig. 6, 𝐴=− (7)
𝑔𝑑𝑠0 + 𝑔𝑚1
an inductor (L0) at the input is used to resonate out the
capacitance of the transistor M0 (Cgs). Similarly, another If 𝑅1 >> 𝑅𝑜𝑢𝑡 and 𝑔𝑚1 >> 𝑔𝑑𝑠0 then gain expression given
inductor (L1) is used for shunt peaking at the output node. in (7) can be simplified as shown in (8).
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𝐴 = −𝑔𝑚0 𝑅𝑜𝑢𝑡 (8) Rout

gm2(vo - vgs0)
B. Analysis of Input and Output Resistance for the Proposed
Ig = 0
LNA
The mathematical expression for the input impedance (𝑅𝑖𝑛 ) +
(gm1)*vgs1
can also be derived from the small signal model of proposed R0 Vo
LNA given in Fig. 7. The below calculations are performed
Ig = 0
assuming that the gate capacitance at the input has been + -
neutralized by the inductor L0. By applying KCL at the input 1/gm2
node, following mathematical expression given in (9) is vgs1
obtained. 1/gm1
vRFin I_in
𝐼_𝑖𝑛 + 𝑔𝑚2 𝑣𝑜 − 𝑔𝑚2 𝑣𝑖𝑛 = 𝑔𝑑𝑠3 𝑣𝑅𝐹𝑖𝑛 (8) - Vo1

+ (gm0)*vgs0
Similarly, (6) can be re-arranged as shown below.
𝑣𝑜 = −|𝐴| ∗ 𝑣𝑅𝐹𝑖𝑛 (9) 1/gds3 1/gds0
` vgs0
After substituting value of 𝑣𝑜 from (9) in (8) and re- Rin
arranging it, mathematical expression of input resistance -
(𝑅𝑖𝑛 ) for the proposed LNA is obtained as shown in (10).
𝑣𝑜𝑢𝑡 1 Fig. 7. Small signal model of proposed LNA
𝑅𝑖𝑛 = = (10)
𝐼_𝑖𝑛 𝑔𝑚2 (1 + |𝐴|) + 𝑔𝑑𝑠3
Rout
If 𝑔𝑑𝑠3 << 𝑔𝑚2 (1 + |𝐴|) then 𝑅𝑖𝑛 expression given in (10)
can be simplified as shown in (11).
Iout
𝑣𝑜𝑢𝑡 1
𝑅𝑖𝑛 = = (11)
𝐼_𝑖𝑛 𝑔𝑚2 (1 + |𝐴|)
(gm1)*vgs1 +
In a typical common gate (CG) amplifier the
transconductance required for 50Ω matching should be 1/gds1 Vo
20mS. However, in our proposed LNA, the required
Ig = 0
transconductance, as depicted in (11) is decreased by a factor -
of (1+|A|) where A is the forward voltage gain. Hence. for a +
voltage gain of 9 (i.e. 19 dB), the required transconductance
required for 50Ω matching is 2mS. This lesser requirement of vgs1
transconductance results in the smaller size of the feedback 1/gm1
transistor (M2) and also reduces the power consumption in -
the feedback branch.
Vo1
Similarly, in order to calculate the output resistance (𝑅𝑜𝑢𝑡 ),
consider the simplified small signal model as shown in Fig.
8. Mathematical expression of 𝐼𝑜𝑢𝑡 after applying KCL at 1/gds0
output node is given in (12).
𝐼𝑜𝑢𝑡 = −𝑔𝑚1 𝑣𝑜1 + 𝑔𝑑𝑠1 𝑣𝑜 − 𝑔𝑑𝑠1 𝑣𝑜1 (12)
Similarly, mathematical expression of 𝑣𝑜1 after applying
KCL at node 𝑣𝑜1 ⁡is given in (13). Fig. 8. Simplified small signal model of proposed LNA
𝑔𝑑𝑠1
𝑣𝑜1 = 𝑣 (13)
𝑔𝑑𝑠0 + 𝑔𝑚1 + 𝑔𝑑𝑠1 𝑜 𝑅𝑜𝑢𝑡 = 𝑟𝑜0 ⁡ + ⁡ 𝑟𝑜1 + 𝑔𝑚1 𝑟𝑜0 𝑟𝑜1 (16)
After substituting value of 𝑣𝑜1 from (13) in (12) and re-
arranging it, mathematical expressions of 𝑅𝑜𝑢𝑡 are obtained
C. Noise Analysis of Proposed LNA
as given in (15) and (16). It can be clearly inferred from (16)
that instead of being a sum of the drain to source resistances, There exist two dominant noise sources at mm-Wave
𝑅𝑜𝑢𝑡 is basically increased due to cascode action. frequencies. First is channel thermal noise and second is gate
resistance noise. Due to the feedback used in the proposed
𝐼𝑜𝑢𝑡 (𝑔𝑑𝑠1 𝑔𝑑𝑠0 ) LNA, the channel and gate resistance noise become corelated.
= (14)
𝑣𝑜𝑢𝑡 (𝑔𝑑𝑠0 + 𝑔𝑑𝑠1 + 𝑔𝑚1 ) Since the cascode pair transistors are greater in size, hence
their noise contribution has the most effect on the circuit’s
𝑣𝑜𝑢𝑡 1 1 𝑔𝑚1 overall noise figure. Therefore, cascode pair is characterized
𝑅𝑜𝑢𝑡 = = + + (15) for both channel and gate resistance noise. Gate resistance
𝐼𝑜𝑢𝑡 𝑔𝑑𝑠0 𝑔𝑑𝑠1 𝑔𝑑𝑠0 𝑔𝑑𝑠1
noise can be considered as more important because it is
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present at the input node and is directly added into the input VDD
RF signal.

1) Channel Thermal Noise

For simplicity in noise analysis, the cascode pair is R0
represented with a single transistor (M0) in the noise
modelling of proposed LNA as shown in Fig. 9 such that the Vo
M2
forward gain and output resistance conditions hold. M2 is the
feedback transistor. By applying KCL at the 𝑣𝑜 and 𝑣𝑠 nodes, Vng
following mathematical expressions are obtained as shown in RG Vg Channel Thermal
(17) and (18).
−𝑣𝑜
𝑅𝑜𝑢𝑡
= 𝐼𝑛0 + 𝑔𝑚0 𝑣𝑠 (17)
Vs

Rs
*
Gate Resistance
Noise of M0
M0
* In0
Noise of M0

𝑣𝑠 (1 + 𝑔𝑚2 𝑅𝑠 )
𝑣𝑜 = (18)
𝑔𝑚2 𝑅𝑠
After substituting value of 𝑣𝑜 from (18) in (17), the Fig. 9. Noise modelling of proposed LNA
mathematical expressions of 𝐼𝑛0 is re-arranged to obtain the
expression as given in (19). By combining (23), (24) and (25), the mathematical
expression can be re-written as give below.
𝑣𝑠 (1 + 𝑔𝑚2 𝑅𝑆 + 𝑔𝑚0 𝑔𝑚2 𝑅𝑠 𝑅𝑜𝑢𝑡 )
𝐼𝑛0 = − (19) 𝑣𝑠 (1 + 𝑔𝑚2 𝑅𝑠 (1 + |𝐴|) = −𝑔𝑚2 𝑅𝑠 |𝐴|⁡𝑣𝑛𝑔 (26)
𝑔𝑚2 𝑅𝑠 𝑅𝑜𝑢𝑡
After applying input matching condition based on (11) and Now, by applying input matching condition based on (11),
gain expression derived from (8), the above-mentioned the above-mentioned mathematical expression can be re-
mathematical expression can be re-organized as shown in organized as shown in (27).
(20). |𝐴|
𝑣𝑠 = ∗𝑣 (27)
𝐼𝑛0 𝑅𝑜𝑢𝑡 2(1 + |𝐴|) 𝑛𝑔
𝑣𝑠 = (20)
2(|𝐴| + 1) Assuming A >> 1, the above mathematical expression for
Input referred channel noise of the transistor M0 is shown input referred gate resistance noise can be re-organized as
in (20). In terms of noise parameters, (20) can be re-written follows.
as shown below. 4𝐾𝑇𝑅𝐺
𝐾𝑇𝛾 𝑣𝑠2 = (28)
12
𝑣𝑠2 =
1 2 (21)
As it is clear from (28), the input referred noise
𝑔𝑚 (1 + )
𝐴 contribution of the gate resistance is decreased by 4 times just
In case of very high value of voltage gain (A), the as it is in the case of channel noise. Hence, it proves that by
simplified version of above mathematical expression is given design the proposed LNA circuitry decreases the noise
below. contribution of the main transistor (M0) by 4 times.
𝐾𝑇𝛾 D. Design Methodology
𝑣𝑠2 = (22)
𝑔𝑚 The major design challenge with the LNA design is to
attain lowest possible noise figure at mm-wave frequencies,
Compared to input referred noise of the classic cascode
while simultaneously maximizing the Fmax of the selected
amplifier, the noise in proposed LNA is 4 times (6 dB) less.
topology. Hence, it is required to re-optimize the LNA design
Moreover. (22) also indicates that the noise of the cascode
in order to choose optimum bias point of transistors. Noise
transistors can be reduced by biasing the transistors such that
figure can be optimized at mm-wave frequencies by choosing
their transconductance is high. This concept is utilized in
optimum bias point and sizing of transistors. For this purpose,
properly deciding the biasing points of the LNA.
[21] proposed a method to optimally choose the biasing point
2) Gate Resistance Noise
of transistors by plotting noise figure and Fmax vs current
Similar to channel noise, the input referred gate resistance
density (mA/um). The point of current density which
noise can also be calculated using the similar procedure. By
produces minimum noise figure is chosen while bias current
applying KVL, the mathematical expression between 𝑣𝑔 and
and size of cascode transistor pairs are also optimized to yield
𝑣𝑛𝑔 is given in (23). minimum noise figure as shown in Fig. 10.
𝑣𝑔 = 𝑣𝑠 + 𝑣𝑛𝑔 (23) Similarly, two inductors are also designed which are used
Similarly, as passive resonators. One inductor (L0) at the input is used
to resonate out the capacitance of the transistor M0 (Cgs).
𝑣𝑠 (1 + 𝑔𝑚2 𝑅𝑠 ) = 𝑔𝑚2 𝑅𝑠 𝑣𝑜 (24) Similarly, another inductor (L1) is used for shunt peaking at
the output node. Inductors are simulated in Keysight RF Pro
𝑣𝑜 = −|𝐴|⁡𝑣𝑔 (25) (integrated with cadence virtuoso) where TSMC 65nm Bulk
CMOS substrate was used. Inductance and quality factors
were measured through momentum simulations. Virtuoso
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layout of inductors is given in Fig. 11 whereas Keysight RF-

Pro view of the designed inductors is given in Fig. 12.
Likewise, in order to suppress the parasitic inductance and
resistance of the interconnects leading to VDD I/O pads of
the LNA stage, a proper combination of de-coupling
capacitors is also employed.

IV. IMPLEMENTATION AND RESULTS

The proposed mm-Wave LNA discussed in section III is
designed and fabricated using TSMC 65nm Bulk CMOS
Technology. Micrograph of the fabricated LNA is shown in
Fig. 13. Total active chip area is 0.18µm2 for the proposed
LNA. Fig. 10. Noise figure and Fmax vs current density plot (This graph
The fabricated LNA circuits are measured using GSG would be replaced excel graph after measurements)
probes by Cascode technologies. These probes are calibrated
up to the tips of the probes. S-parameter measurements are
performed using 67GHz PNA by Keysight.
Fig. 14 and Fig. 15 show the comparison of post layout and
measured S21 and NF results respectively for the fabricated
LNA. It can be seen from the post layout results that this work
achieved a peak S21 value of 18.48dB. Wideband 3-dB
bandwidth for the designed LNA is in the range of 26 to 33.6
GHz. Likewise, the NF is also less than 3dB over the entire
band of interest, including the effect of the buffer. Fig. 16
shows the plot of measured S11 and S22. Both S11 and S22
are less than -10dB in the band of interest depicting the 50Ω
input and output matching of LNA. Similarly, Fig. 17 and
Fig. 18 show the linearity plots for the proposed LNA with a
Fig. 11. Virtuoso layout view of designed inductor
1dB compression point of -24.5 dBm and IIP3 of -20 dBm.
Measured power consumption for the complete LNA
circuitry including the buffer stage is 17 mW.

V. PERFORMANCE COMPARISON WITH STATE-OF-THE-ART

LNA DESIGNS
A comparison table along with discussion of results would
be completed after measurements of the chips is done.
TABLE I. PERFORMANCE COMPARISON OF STATE-OF-THE-ART
LNAs WITH PROPOSED LNA
Our
Parameter [22] [23] [24] [25] [26] Work
Fig. 12. Keysight RF-Pro view of designed inductor

Technology 65 nm CMOS
S21 (dB) 10.2 18.3 18.2 10.7 14.3
15.8- 24.9- 22- 7.6- 35-
Freq. (GHz)
30.3 32.5 34 29 43
3dB BW
14.5 7.6 12 21.4 8
(GHz)
NF (dB) 3.3 3.25 3.9 4.5 3.8
Area (mm2) 0.18 0.11 0.16 0.23 0.25
PDC (mW) 12.4 20.5 9.8 12.1 28.8
P1dB (dBm) - -24 -21 - -
IIP3 (dBm) -0.5 - - 1.4 -9.5

Fig. 13. Micrograph of fabricated LNA in TSMC 65nm bulk CMOS

VI. CONCLUSION process (This figure would be replaced with micrographs)
Millimeter-band frequencies have become more popular
in recent times because they can provide higher data rates as to current feedback is employed to reduce the
well as efficient utilization of frequency spectrum. This transconductance requirements for input matching. The
article presented a mm-wave LNA for 5G applications. The proposed circuit topology partially cancels noise by design
proposed LNA utilized cascode topology, which increases the because noise becomes correlated at the input and output
output resistance, ultimately improving the gain as well as the nodes due to the presence of feedback. The proposed LNA is
isolation between input and output nodes. Similarly, a voltage successfully fabricated using TSMC 65nm Bulk CMOS
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technology. Measurement results show that the fabricated

LNA achieved superior performance as compared to the
state-of-the-art designs of LNA. Peak S21 value of 18.48dB
with a wideband 3-dB bandwidth in the range of 26 to
33.6GHz is measured. The measured NF is also less than 3dB
over the entire band of interest. The active area occupied by
the fabricated LNA is 300×100µm2 with 17mW power
consumption including the output buffer stage.
For this purpose, [21] proposed a method to optimally
choose the biasing point of transistors by plotting noise figure
and Fmax vs current density (mA/um)

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