1(a) The truth table below has two inputs, A and B, and two outputs, S and C.

(i) Write a logic expression for S in terms of A and B.

[1]

(ii) Write a logic expression for C in terms of A and B.

[1]

(iii) Use the expressions for S and C to draw a single logic circuit for the truth table.

[2]

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 (b) Using the rules for manipulating Boolean expressions simplify the following:
A ∧B ∨ A∧(B∨C) ∨ B∧(B∨C)

[4]

2(a) An XOR gate is shown below. Complete the truth table for XOR.

A B Q
1 1
1 0
0 1
0 0

[2]

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 (b) A set of logic gates are connected as below.

(i) Complete the Truth Table below:

A B Cin S Cout

1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0

[4]

(ii) Explain what the circuit does. You should refer to A, B, Cin, S and Cout in your answer.

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 [4]

(c)

(i) Write a Boolean expression equivalent to S.

[1]

(ii) Write a Boolean expression equivalent to Cout.

[2]

3(a) All users of a computer system have a unique username and password. The computer system has implemented
two-factor authentication so that users must respond to either an email or text message containing a secret code
to be able to access the system.

Let:

A be a Boolean value for if a user enters a valid username

B be a Boolean value for if a user enters a password that matches their username

C be a Boolean value for if a user is able to respond to an email containing a secret code

D be a Boolean value for if a user is able to respond to a text message containing a secret code

Q be a Boolean value for if entry to the computer system is allowed

Complete the Boolean expression below:

Q≡

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 (b) Another Boolean expression for a logic system is shown below:
Q ≡ ¬ (¬ A ∧ ¬ B)

(i) Simplify this Boolean expression so that it does not include any negation. You must explain which Boolean
algebra rule(s) you are using at each step.

[2]

(c)

The logic circuit above has two inputs (A, B) and two outputs (S, C).

(i) Give the Boolean expressions for the outputs S and C.

S≡

C≡

[2]

(ii) Complete the truth table for this logic circuit.

A B S C
0 0
0 1
1 0

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 1 1

(iii) Describe how this logic circuit can be adapted to add together two 4-bit binary numbers.

[4]

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 4(a) Elliott has designed a logic circuit. The expression he has created for the logic circuit is:

Q = (A ∧ ¬B) ∨ (¬A ∧ C ∧ D) ∨ (A ∧ B)

Complete the Karnaugh Map below to simplify this expression. Show your working.

Simplified expression:

[4]

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 (b) Draw a Logic diagram for the following expression:

Q = ¬(A ∧ B) ∨ (C ∧¬ D)

[3]

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 5 Burger House is a fast food restaurant which wants to encourage healthy eating amongst its younger diners.

(a)
(i) Shown below in Fig.2 is the Burger House children’s menu.

Children receive a free toy when they select a meal (i.e. one burger, one side dish and one dessert)
made up of only healthy options.

Let g be a Boolean value for if a child has chosen a grilled chicken burger.
Let s be a Boolean value for if a child has chosen salad.
Let c be a Boolean value for if a child has chosen carrot sticks.
Let f be a Boolean value for if a child has chosen fruit salad.
Let t be a Boolean value for whether a child receives a toy.

Write an expression using Boolean algebra to determine whether a child receives a toy when they select
a meal.

t=

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 [3]

(b)
(ii) Burger House wants to add this logic into its till system.
Complete the code below assuming that g,s,c,f and t are Boolean variables with the same meaning as
part (i).

[2]

6 An electronics engineer needs a circuit with the following logic.

(A∧B) ∨ (¬A∧B) ∨ (¬C∧¬D)

Complete and use the Karnaugh map below to simplify the expression above.

Simplified expression:

[4]

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 7 Complete the truth table to represent the following Boolean expression.

Q ≡ ¬ (A Λ B) V C

A B C Q
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

[2]

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 8 Daniel is an engineer. He has created the following logic circuit shown in Fig. 4.

Fig. 4

Complete the truth table below for the logic circuit shown in Fig. 4.

A B C D X
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
[4]

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 9(a)

State the Boolean expression represented by the Karnaugh map in Fig. 9.1, in its smallest form.

[4]

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 (b) State the simplified versions of the following Boolean expressions:

(i) ¬ ¬A

[1]

(ii) (¬A Λ ¬B)

[1]

(iii) ¬(¬A Λ ¬B)

[1]

10(a) A NAND gate and its truth table are shown in Fig. 10.1.

Draw a set of gates equivalent to a NAND gate, but built only of AND, OR and NOT gates.

[2]

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 (b) The component below is a D-Type, positive edge triggered, flip-flop.

State the purpose of a flip-flop.

[1]

(c) Draw the output of the flip-flop from Fig. 10.2 on the diagram below.

[3]

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 11(a) Draw an XOR gate.

[1]
(b) Explain the difference in the function of OR and XOR gates.

[2]

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 (c) A circuit contains the logic gates shown below.

(i) Complete the logic table below.

A B C D Output
1 1 1 1
1 1 1 0
1 1 0 1
1 1 0 0
1 0 1 1
1 0 1 0
1 0 0 1
1 0 0 0
0 1 1 1
0 1 1 0
0 1 0 1
0 1 0 0
0 0 1 1
0 0 1 0
0 0 0 1
0 0 0 0
[4]

(ii) Complete the Boolean expression below to represent the circuit.

≡ Output

[2]

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 12(a) A cinema offers discounted tickets, but only under one of the following conditions:
• Customer is under 18 and has a student card.
• Customer is over 60 and has ID which proves this.

Let:

A be Customer is under 18

B be Customer has a student card

C be Customer is over 60

D be Customer has ID

Q be Discount ticket issued

Complete the Boolean expression below:

Q≡ [3]

(b) The cinema has a voucher which promises free popcorn when the voucher is produced whilst buying a soft drink
or bottle of water.

Let:

E be Voucher is shown

F be Soft drink is bought

G be Bottle of water is bought

R be Free popcorn given.

This could be written as:

R ≡ (E⋀F) ⋁ (E⋀G)

(i) Complete the truth table below.

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 E F G (E⋀F) (E⋀G) (E⋀F)⋁(E⋀G)

1 1 1

1 1 0

1 0 1

1 0 0

0 1 1

0 1 0

0 0 1

0 0 0

[4]

(ii) Simplify the expression

(E⋀F) ⋁ (E⋀G)

[2]

Most films are now distributed to cinemas digitally. A studio allows cinemas to download its latest film 5 days
before the release date via a private download. It wants to ensure that no cinema shows it before the release
date.

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 13(a) A half adder has the truth table shown below:

A B Sum Carry

1 1 0 1

1 0 1 0

0 1 1 0

0 0 0 0

Draw a half adder using logic gates.

[3]

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 (b) Draw the logic gates represented by the Karnaugh Map below. Show your working.

[4]

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 14(a)
Draw a logic gate diagram to represent the Boolean expression

Q≡¬A⋁B

[2]
(b) Find the Boolean expression represented in the Karnaugh Map below. Show your working.

[5]

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 15 A company releases an in-home virtual assistant called ‘Bertie Butler’.

The device, when placed in a room, listens out for the phrase “Hey Bertie”. When someone says that phrase it
then listens to the question that follows and tries to give a relevant answer.

Bertie Butler has a number of built-in input and output devices.

Bertie Butler’s circuitry is designed to only listen out for “Hey Bertie” under certain circumstances, which are:

The privacy button (P) must be off and the microphone must generate a signal (S) to say a sound has been
heard.

(i) Complete the truth table for whether the device is listening (L).

P S L
False False
False True
True False
True True
[2]

(ii) Draw logic gates to represent the circuitry needed.

[3]

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 16(a)

(i) Complete the Karnaugh map below for the Boolean expression (¬ A ∧ ¬ B) ∨ ( A ∧ ¬ B)

[3]

(ii) Use the Karnaugh map to find a simplified Boolean expression that is equivalent to (¬ A ∧ ¬ B) ∨ ( A ∧ ¬ B)

[2]

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 (b)

(i) State the purpose of a D-type flip-flop circuit.

[2]

(ii) Describe the inputs and outputs used by a D-type flip-flop circuit, explaining how the inputs are used to
control the outputs.

[4]

END OF QUESTION PAPER

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 Mark Scheme

Question Answer/Indicative content Marks Guidance

1 a i S=A XOR B 1 For 1 mark.

ii C=A AND B 1 For 1 mark.

iii 2 For 2 marks – two gates with correct

inputs.

b 4 For 4 marks - 1 mark for each bullet

completed correctly.

Total 8

2 a A B Q 2
1 1 0
1 0 1
0 1 1
0 0 0

1 mark for the first two rows

1 mark for the last two rows

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 Mark Scheme

Question Answer/Indicative content Marks Guidance

b i 4

1 Mark for rows 1 and 2

1 Mark for rows 3 and 4

1 Mark for rows 5 and 6

1 Mark for rows 7 and 8

ii – Circuit adds two bits (and a carry bit) 4

together / is an adder.
– A B and Cin are added together
– The result is given in S
– And a carry bit in Cout
(1 per –)

c i 1 Accept XOR instead of ∨

Accept instead of ∨

ii 2 Accept XOR instead of ∨

Accept instead of ∨
One mark for ((A∨B) ∧ Cin)
Accept AND instead of ∧
One mark for ∨ (A ∧ B)
Accept OR instead of ∨

Accept + instead of ∨

Total 13

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 Mark Scheme

Question Answer/Indicative content Marks Guidance

3 a Q≡A∧B 3 AO1.2 Q ≡ A ∧ B ∧ (C ∨ D)
∧
(C ∨ D) Accept alternative symbols for AND / OR
e.g. Q = A AND B AND (C OR D)
Brackets must be included for 3rd point
Allow XOR for bullet point 3
Any additional symbols max 2 marks

b Identification of De Morgan’s and/or 2 AO2.2

double negation rule
Correct final answer to give A v B

c i S=A⊻B 2 AO2.1 Accept alternative symbols for AND /XOR

C=A∧B

ii 1 mark for S column 2 AO2.1 A B S C

1 mark for C column
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

iii Logic circuit adds together 2 binary 4 AO1.2

digits / half adder
S gives sum, C gives carry
Two half adders can be joined
together…
…with an OR gate
to form full adder
4 full adders can be used to add two
four bit numbers
Carry out on one joined to carry in on
next

Total 13

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 Mark Scheme

Question Answer/Indicative content Marks Guidance

4 a Solution: 4 (AO2.1) Brackets are not required for the simplified

(2) expression
(AO2.2)
(2) Examiner’s Comments
This question was answered well with
many candidates achieving all 4 marks.
Some completed the table correctly but
were not able to simplify the expression
appropriately.

1 mark per bullet up to a maximum of 4

marks:

1 mark for filling in the table correctly

1 mark for the group shown in red
1 mark for the group shown in green
1 mark for the simplified expression A
∨ (C ∧ D)

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 Mark Scheme

Question Answer/Indicative content Marks Guidance

b 3 (AO3.1) Allow NAND gate as alternative for BP1

(3)
Examiner’s Comments
As with the first part of this question, this
was answered well. Most candidates used
the same gates that are shown in the mark
scheme, although equivalent gates were
1 mark per bullet up to a maximum of 3 accepted. Some candidates lost marks for
marks: not being clear on the type of gate they
had decided on.
An AND gate taking A and B as inputs
with the output connecting to a NOT Exemplar 2
gate
An AND gate taking C and the NOT of
D as the inputs
An OR gate taking the outputs of the
NOT and AND gates

Exemplar 2 was given full marks. This

candidate has gained all 3 marks as the
gates are correct and are clearly drawn to
avoid confusion. Each gate also has the
correct number of inputs and outputs in all
three instances.

Logic gate guidance

To make sure full credit is given for the
answers provided, it is essential that the
drawings are clear enough to distinguish
one gate from another. Some gates look
similar, so the lines and symbols need to
be clear enough to establish which gate
has been used.

Total 7

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 Mark Scheme

Question Answer/Indicative content Marks Guidance

5 i t≡g∧s∨c∧f 3 For 3 marks.

1 mark for ∧ used to conjoin g and f to rest

of expression.
1 mark for s ∨ c.
1 mark for brackets around s ∨ c.

Give full marks to any equivalent

expression.

Accept different notations.

t ≡ g. s + c .f

ii 2 For 2 marks.

Accept forms.

Accept && and || operators.

Allow follow through mark from 5a)i).

Total 5

6 Simplified expression: B v (¬C∧¬D) 4 For 4 marks.

1 mark for simplified expression: B ∨

(¬C∧¬D)
1 mark for filling in table correctly.
1 mark for identifying each grouping
(maximum 2). Allow follow through if tabled
filled incorrectly giving one mark for each
valid grouping if it is the most efficient
possible to a maximum of two marks.

Total 4

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 Mark Scheme

Question Answer/Indicative content Marks Guidance

7 A B C Q 2 (AO2.2) Examiner’s Comments

0 0 0 1
Most candidates achieved both marks on
0 0 1 1 this question. The presentation of some
0 1 0 1 responses made it difficult to determine if
the candidate was offering a zero or a one.
0 1 1 1
Centres should encourage candidates to
1 0 0 1 rewrite their response if they have
1 0 1 1 overwritten a zero with a one and vice
versa.
1 1 0 0
1 1 1 1

First 4 rows correct 1 mark

Last 4 rows correct 1 mark

Total 2

8 4 Award 1 mark for each group of 4 1’s / 0’s.

AO2.2
(4)

Total 4

9 a (¬A ∧¬D) ∨(A ∧B ∧C) ∨(¬B ∧¬C ∧¬D) 4

One mark for each bracketed section.
One mark for them being joined with ORs

b i A 1

ii ¬(A∨ B) 1

iii A∨B 1

Total 7

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 Mark Scheme

Question Answer/Indicative content Marks Guidance

10 a 2

One AND one NOT gate used (1)

In correct configuration (1)

b To store the state of a bit 1

c 3

One mark for each two correct clock

cycles.

Total 6

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 Mark Scheme

Question Answer/Indicative content Marks Guidance

11 a 1 AO1.1 Accept diagram of gate only without input /

output

Examiner’s Comments

There were very few candidates who could

not correctly draw an XOR gate.

b OR gate outputs true if at least one of its 2 AO1.2 Accept appropriate, correctly labelled, truth
inputs is true (1) tables. One mark for each truth table.

XOR gate output true if and only if one of Examiner’s Comments

its inputs is true. (1)
A lack of clarity of expression led to
candidates not gaining credit in this
question. Some candidates who achieved
full marks supported their descriptions with
correct two-input truth tables which clearly
demonstrated the difference.

c i 4 AO2.2 Examiner’s Comments

This question was well received by

candidates with most achieving full marks.

ii (A ∨ B) ∨ (C ∨ D) ≡ Output 2 AO2.2 Accept answer without brackets.

Accept alternative notation i.e. OR , +

A ∨ B (1 Mark)
Examiner’s Comments
∨ (C ∨ D) (1 Mark)
Boolean expressions were in the main
correct. All standard notations was credited
provided it was used consistently.

Total 9

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 Mark Scheme

Question Answer/Indicative content Marks Guidance

12 a Q = (A∧B) ∨ (C∧D) 3 Accept (C∧D) ∨ (A∧B)

(AO1.2) Accept (B∧A) instead of (A∧B)

1 mark for (A∧B) Accept (D∧C) instead of (C∧D)

1 mark for (C∧D) Accept alternative notations (e.g. +/. OR /

AND)

1 mark for the ∨ joining the two parts. Accept AB as (A.B) and CD as (C.D)

Accept answers without brackets

Examiner’s Comments
In general, most candidates achieved all of
the available marks in these questions.

b i E F G (E⋀F) (E⋀G) (E⋀F)V 4

(E⋀G)
(AO1.2)
1 1 1 1 1 1
1 1 0 1 0 1
1 0 1 0 1 1
1 0 0 0 0 0
0 1 1 0 0 0
0 1 0 0 0 0
0 0 1 0 0 0
0 0 0 0 0 0

1 mark for each of the pairs of rows.

ii (F∨G) ∧ E 2 Accept:

(AO2.2) (G∨F) ∧ E

One mark for the (F∨G) E ∧ (F∨G)

One mark for the ∧ E E ∧ (G∨F)

Examiner’s Comments
In general, most candidates achieved all of
the available marks in these questions.

Total 9

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 Mark Scheme

Question Answer/Indicative content Marks Guidance

13 a 3

(AO1,1)

XOR Gate (1)

AND Gate (1)

Correct connections and no additional

gates (1)

Examiner’s Comments
Most candidates scored well on these
questions demonstrating their
understanding of logic gate circuits. Some
candidates simplified the circuit in part b)
which achieved full marks provided the
resultant circuit gave the same output.

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 Mark Scheme

Question Answer/Indicative content Marks Guidance

b – Correctly identified groups on 4

Karnaugh map / Correct boolean
statement.(1)
(AO2.2)

– NOT A AND NOT C Gates (1)

– A AND C gates (1)

– Both sets of gates joined by OR

gate (with no other gates used).
(1)
(¬A ⋀ ¬C) ⋁ (A⋀C)

Or equivalent.

Or equivalent.

Examiner’s Comments
Most candidates scored well on these
questions demonstrating their
understanding of logic gate circuits. Some
candidates simplified the circuit in part b)
which achieved full marks provided the
resultant circuit gave the same output.

Total 7

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 Mark Scheme

Question Answer/Indicative content Marks Guidance

14 a 2 (AO1.2)

Examiner’s Comments

Most candidates achieved both the

- A going into NOT gate. available marks on this question.
- B and NOT A going into OR gate (and
Q coming out of it)
(1 Mark per -, Max 2)

b - Groups correctly identified (with no 5 (AO1.2)

further groups).
- Answer includes ¬ C∧¬D
- Answer includes ¬ C∧¬D
- Answer includes ¬ C∧¬D
- All three sections joined with ∧s in any
order but with
no further sections.
E.g.
(A∧¬B )∨(A∧¬C )∨(¬ C∧¬D)
The brackets aren’t necessary
(1 Mark per -, Max 5) Examiner’s Comments

The question required candidates to find

the Boolean expression represented in the
Karnaugh Map. Most candidates achieved
a mark for showing the correct groupings
on the map. Many went on to achieve
some marks for the resultant expression.
Some candidates specified NOT(C AND D)
instead of NOT C AND NOT D evidently
assuming the expressions are the same.

Total 7

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 Mark Scheme

Question Answer/Indicative content Marks Guidance

15 i P S L 2 Accept any sensible representation of True

AO1.2 or False
False False False
False True True Examiner’s Comments
True False False
Well answered by most candidates with
True True False
some opting for a different representation
of True / False in their response. These
responses, where correct, were condoned
1 Mark for first 2 rows, 1 Mark for second 2
but centres would best advise candidates
rows.
to use the representations given in the
context in future series.

ii -P going into NOT Gate 3

-S going into AND gate…
-…NOT P going into AND gate, L coming AO3.1
out of it and no additional gates or
connections.
(1 per -, max 3)

Examiner’s Comments

Generally, candidates responded well to

this question, but some candidates used
incorrect logic gate representations.
Centres should remind candidates of the
acceptable boolean algebra logic gate
representations see specification appendix
5d.

Total 5

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 Mark Scheme

Question Answer/Indicative content Marks Guidance

16 a i left column filled with 1s (¬ A ∧ ¬ B) … 3

right column filled with 1s ( A ∧ ¬ B)…
…Middle 2 columns filled with zero or AO1.2
blank (1)
AO2.2
(2)

ii ¬ B / NOT B 2
Karnaugh map used to show 1s
highlighted with overlap AO2.2

b i Delay / store a value… 2

…of 1 bit
When a signal is given AO1.1

ii Data input 4
Clock input
Q output AO1.1
When clock input goes high… (2)
…Q changes to D AO1.2
NOT Q is reverse of Q (2)

Total 11

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