Synthesis of Computational Structures

for Analog Signal Processing

Cosmin Radu Popa

Synthesis of Computational
Structures for Analog Signal
Processing
Cosmin Radu Popa
Faculty of Electronics, Telecommunications
and Information Technology
University Politehnica of Bucharest
Bucharest, Romania
[email protected]

ISBN 978-1-4614-0402-6 e-ISBN 978-1-4614-0403-3

DOI 10.1007/978-1-4614-0403-3
Springer New York Dordrecht Heidelberg London
Library of Congress Control Number: 2011934510

# Springer Science+Business Media, LLC 2011

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This book is dedicated to my beloved
daughter Ilinca Maria.
Preface

Signal processing represents an important domain of electronics, in the last years

many efforts being directed for improving the performances of these structures.
The approach of the signal processing from an analog perspective presents the
advantage of allowing an important reduction of the circuits’ power consumption.
The compact implemented structures are compatible with ultimate low-power
designs and find a lot of applications such as portable equipments, wireless nano-
sensors or medical implantable devices. Even the power consumption is continuous
for analog circuits comparing with digital structures that consume only in the
switching intervals, the possibility of an important reduction of designs’ complex-
ities and of the number of their constitutive active devices strongly decrease the
medium power consumption per unity of time for analog designs. Moreover, low-
power analog signal processing circuits are often implemented using subthreshold-
operated MOS transistors, having extremely low values of drain currents, this fact
producing an additionally lowering of the total power requested by the analog
computational structures. The original approach of designing analog signal proces-
sing circuits using multifunctional structures also contributes to the decreasing of
power consumption per implemented function.
Another important advantage of analog signal processing is that the speed of
circuits is usually greater than the speed of digital computational circuits, allowing
a real time signal processing.
Two important classes of analog signal processing circuits can be identified. The
first class corresponds to linear structures, such as differential amplifier structures,
multiplier circuits or active resistor structures, being necessary to develop particular
linearization techniques in order to improve their general performances. The second
class of analog signal processing circuits covers the area of nonlinear structures:
squaring or square-rooting circuits, exponential structures or vector summation and
Euclidean distance circuits. In this case, the most important goal is to minimize the
approximation error of the implemented function. In order to improve the circuits’
frequency response, a part of analog signal processing circuits are implemented

vii
viii Preface

using exclusively MOS transistors biased in saturation region. In cases in which the
low-power operation is crucial, the subthreshold operation of MOS active devices
represents the single choice for the designer.
In order to obtain an important reduction of design costs and of power consump-
tion for the designed circuits, multifunctional computational structures can be
implemented. Their principle of operation is based on the possibility of a multiple
use of the same functional cell that is named multifunctional circuit core. As the
design effort is mostly focused on the improving of the core performances and
because the most important silicon area is consumed by the multifunctional core,
the reutilization of this part of the multifunctional structure for all circuit functions
will strongly decrease the complexity and power consumption per implemented
function. The multifunctional structures present the important advantage of a
relatively simple reconfiguration, small changing of the design allowing to obtain
all necessary linear or nonlinear circuit functions.
The first chapter is dedicated to the presentation of linearization techniques for
improving the performances of CMOS differential structures, fundamental circuits
in VLSI analog and mixed-signal designs. The mathematical fundamentals are
structured in eight different elementary mathematical principles, each of them
being illustrated by concrete implementations in CMOS technology of their func-
tional relations.
As it exists a relative limited number of mathematical principles that are used for
implementing the multiplier circuits, the first part of Chap. 2 is dedicated to the
analysis of the mathematical relations that represent the functional core of the
designed circuits. In the second part of the chapter, starting from these elementary
principles, there are analyzed and designed concrete multiplier circuits, grouped
according to their constitutive mathematical principles. Both current and voltage
multiplier circuits are presented, their operation being extensively described in
Chap. 2.
The squaring function can be relatively easily obtained considering the intrinsic
squaring characteristic of the MOS transistor biased in saturation region. Referring
to the input variable, the squaring circuits can be clustered in two important classes:
voltage squarers and current squarers, for both of them, the output variable being,
usually, a current. The first part of Chap. 3 is dedicated to the analysis of the
mathematical relations that represent the functional core of the designed circuits,
while, in the second part of the chapter, starting from these elementary principles,
there are analyzed and designed concrete squaring circuits, clustered according to
their constitutive mathematical principles.
An important class of VLSI computational structures is represented by the
square-root circuits. Frequently implemented using a translinear loop, they exploit
the squaring characteristic of MOS transistors biased in saturation region. The
presented design techniques are based on five different elementary mathematical
principles, each of them being illustrated in Chap. 4 by concrete implementations in
CMOS technology.
Exponential circuits represent important building blocks with many applications
in VLSI designs. In CMOS technology, the exponential law is available only for
Preface ix

the weak inversion operation of MOS transistor, the circuits designed using
subthreshold-operated MOS active devices having the disadvantage of a poor
frequency response. Thus, circuits realized in CMOS technology that require a
good frequency response can be designed using exclusively MOS transistors biased
in saturation region. The first part of Chap. 5 is dedicated to the analysis of the
mathematical relations that represent the functional core of the designed circuits.
In the second part of the chapter, using these elementary principles, there are analyzed
and designed concrete exponential circuits, grouped according to the mathematical
principles they are based on.
Chap. 6 is dedicated to the analysis and design of Euclidean distance circuits,
classified (depending on their input variable), in computational structures having
current-input or voltage-input vectors.
Functionally equivalent with a classical resistor, but presenting many important
advantages in comparison with them, active resistor structures are extensively
analyzed in Chap. 7. The goal of designing this class of active structures is mainly
related to the possibility of an important reduction of the silicon area, especially for
large values of the simulated resistances. The techniques presented for designing
active resistor structures are based on six different elementary mathematical prin-
ciples, each of them being illustrated by concrete implementations in CMOS
technology.
A multitude of fundamental linear or nonlinear analog signal processing blocks
can be realized starting from the same core, the optimization techniques implemen-
ted for the core being efficient for all derived circuits. The structures that can be
realized starting from an improved performance multifunctional core are: differen-
tial amplifiers, multiplier circuits, active resistors (having both positive and nega-
tive controllable equivalent resistance), squaring, square-rooting or exponential
circuits. Additionally, developing proper approximation functions, multifunctional
structures are able to generate any continuous mathematical function. The circuits
shown in Chap. 8 are based on four different elementary mathematical principles,
being also presented concrete implementations in CMOS technology of these
complex computational structures.

Bucharest, Romania Cosmin Radu Popa

Contents

1 Differential Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Mathematical Analysis for Synthesis of Differential
Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 First Mathematical Principle (PR 1.1) . . . . . . . . . . . . . . . . . . . . . . 1
1.1.2 Second Mathematical Principle (PR 1.2) . . . . . . . . . . . . . . . . . . . 2
1.1.3 Third Mathematical Principle (PR 1.3) . . . . . . . . . . . . . . . . . . . . . 2
1.1.4 Fourth Mathematical Principle (PR 1.4). . . . . . . . . . . . . . . . . . . . 2
1.1.5 Fifth Mathematical Principle (PR 1.5). . . . . . . . . . . . . . . . . . . . . . 3
1.1.6 Sixth Mathematical Principle (PR 1.6) . . . . . . . . . . . . . . . . . . . . . 3
1.1.7 Seventh Mathematical Principle (PR 1.7) . . . . . . . . . . . . . . . . . . 3
1.1.8 Different Mathematical Principle for Differential
Amplifiers (PR 1.D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Analysis and Design of Differential Structures . . . . . . . . . . . . . . . . . . . . 4
1.2.1 Differential Structures Based on the First
Mathematical Principle (PR 1.1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2.2 Differential Structures Based on the Second
Mathematical Principle (PR 1.2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.2.3 Differential Structures Based on the Third
Mathematical Principle (PR 1.3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.2.4 Differential Structures Based on the Fourth
Mathematical Principle (PR 1.4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
1.2.5 Differential Structures Based on the Fifth
Mathematical Principle (PR 1.5) . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
1.2.6 Differential Structures Based on the Sixth
Mathematical Principle (PR 1.6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
1.2.7 Differential Structures Based on the Seventh
Mathematical Principle (PR 1.7) . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
1.2.8 Differential Structures Based on Different
Mathematical Principle (PR 1.D) . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
1.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

xi
xii Contents

2 Voltage and Current Multiplier Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

2.1 Mathematical Analysis for Synthesis of Multipliers . . . . . . . . . . . . . . 89
2.1.1 Mathematical Analysis of Voltage Multiplier
Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
2.1.2 Mathematical Analysis of Current Multiplier
Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
2.2 Analysis and Design of Multiplier Circuits . . . . . . . . . . . . . . . . . . . . . . . 93
2.2.1 Design of Voltage Multiplier Circuits . . . . . . . . . . . . . . . . . . . . . 93
2.2.2 Design of Current Multiplier Circuits . . . . . . . . . . . . . . . . . . . . . 164
2.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

3 Squaring Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

3.1 Mathematical Analysis for Synthesis of Squaring Circuits . . . . . . . 185
3.1.1 Mathematical Analysis of Voltage Squaring Circuits . . . . . 185
3.1.2 Mathematical Analysis of Current Squaring Circuits . . . . . 186
3.2 Analysis and Design of Squaring Circuits. . . . . . . . . . . . . . . . . . . . . . . . . 188
3.2.1 Design of Voltage Squaring Circuits . . . . . . . . . . . . . . . . . . . . . . 188
3.2.2 Design of Current Squaring Circuits . . . . . . . . . . . . . . . . . . . . . . 224
3.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

4 Square-Root Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

4.1 Mathematical Analysis for Synthesis of Square-Root
Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
4.1.1 First Mathematical Principle (PR 4.1) . . . . . . . . . . . . . . . . . . . . . 249
4.1.2 Second Mathematical Principle (PR 4.2) . . . . . . . . . . . . . . . . . . 249
4.1.3 Third Mathematical Principle (PR 4.3) . . . . . . . . . . . . . . . . . . . . 250
4.1.4 Fourth Mathematical Principle (PR 4.4). . . . . . . . . . . . . . . . . . . 250
4.1.5 Different Mathematical Principle (PR 4.D) . . . . . . . . . . . . . . . 250
4.2 Analysis and Design of Square-Root Circuits . . . . . . . . . . . . . . . . . . . . . 250
4.2.1 Square-Root Circuits Based on the First
Mathematical Principle (PR 4.1) . . . . . . . . . . . . . . . . . . . . . . . . . . 250
4.2.2 Square-Root Circuits Based on the Second
Mathematical Principle (PR 4.2) . . . . . . . . . . . . . . . . . . . . . . . . . . 252
4.2.3 Square-Root Circuits Based on the Third
Mathematical Principle (PR 4.3) . . . . . . . . . . . . . . . . . . . . . . . . . . 257
4.2.4 Square-Root Circuits Based on the Fourth
Mathematical Principle (PR 4.4) . . . . . . . . . . . . . . . . . . . . . . . . . . 260
4.2.5 Square-Root Circuits Based on Different
Mathematical Principles (PR 4.D) . . . . . . . . . . . . . . . . . . . . . . . . . 262
4.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Contents xiii

5 Exponential Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

5.1 Mathematical Analysis for Synthesis of Exponential
Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
5.1.1 First Mathematical Principle (PR 5.1) . . . . . . . . . . . . . . . . . . . . . 267
5.1.2 Second Mathematical Principle (PR 5.2) . . . . . . . . . . . . . . . . . . 268
5.1.3 Third Mathematical Principle (PR 5.3) . . . . . . . . . . . . . . . . . . . . 269
5.1.4 Fourth Mathematical Principle (PR 5.4). . . . . . . . . . . . . . . . . . . 270
5.1.5 Fifth Mathematical Principle (PR 5.5). . . . . . . . . . . . . . . . . . . . . 271
5.1.6 Sixth Mathematical Principle (PR 5.6) . . . . . . . . . . . . . . . . . . . . 273
5.1.7 Seventh Mathematical Principle (PR 5.7) . . . . . . . . . . . . . . . . . 274
5.1.8 Eighth Mathematical Principle (PR 5.8). . . . . . . . . . . . . . . . . . . 277
5.1.9 Ninth Mathematical Principle (PR 5.9). . . . . . . . . . . . . . . . . . . . 278
5.2 Analysis and Design of Exponential Circuits . . . . . . . . . . . . . . . . . . . . . 280
5.2.1 Exponential Circuits Based on the First
Mathematical Principle (PR 5.1) . . . . . . . . . . . . . . . . . . . . . . . . . . 280
5.2.2 Exponential Circuits Based on the Second
Mathematical Principle (PR 5.2) . . . . . . . . . . . . . . . . . . . . . . . . . . 295
5.2.3 Exponential Circuits Based on the Third
Mathematical Principle (PR 5.3) . . . . . . . . . . . . . . . . . . . . . . . . . . 297
5.2.4 Exponential Circuits Based on the Fourth
Mathematical Principle (PR 5.4) . . . . . . . . . . . . . . . . . . . . . . . . . . 299
5.2.5 Exponential Circuits Based on the Fifth
Mathematical Principle (PR 5.5) . . . . . . . . . . . . . . . . . . . . . . . . . . 300
5.2.6 Exponential Circuits Based on the Sixth
Mathematical Principle (PR 5.6) . . . . . . . . . . . . . . . . . . . . . . . . . . 301
5.2.7 Exponential Circuits Based on the Seventh
Mathematical Principle (PR 5.7) . . . . . . . . . . . . . . . . . . . . . . . . . . 302
5.2.8 Exponential Circuits Based on the Eighth
Mathematical Principle (PR 5.8) . . . . . . . . . . . . . . . . . . . . . . . . . . 303
5.2.9 Exponential Circuits Based on the Ninth
Mathematical Principle (PR 5.9) . . . . . . . . . . . . . . . . . . . . . . . . . . 304
5.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

6 Euclidean Distance Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

6.1 Mathematical Analysis for Synthesis
of Euclidean Distance Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
6.1.1 Euclidean Distance of Voltage Input Vectors . . . . . . . . . . . . . 309
6.1.2 Euclidean Distance of Current Input Vectors . . . . . . . . . . . . . 310
6.2 Analysis and Design of Euclidean Distance Circuits. . . . . . . . . . . . . . 311
6.2.1 Euclidean Distance Circuits for Voltage
Input Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
6.2.2 Euclidean Distance Circuits for Current
Input Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
6.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
xiv Contents

7 Active Resistor Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

7.1 Mathematical Analysis for Synthesis
of Active Resistor Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
7.1.1 First Mathematical Principle (PR 7.1) . . . . . . . . . . . . . . . . . . . . . 323
7.1.2 Second Mathematical Principle (PR 7.2) . . . . . . . . . . . . . . . . . . 323
7.1.3 Third Mathematical Principle (PR 7.3) . . . . . . . . . . . . . . . . . . . . 324
7.1.4 Fourth Mathematical Principle (PR 7.4). . . . . . . . . . . . . . . . . . . 324
7.1.5 Fifth Mathematical Principle (PR 7.5). . . . . . . . . . . . . . . . . . . . . 324
7.1.6 Different Mathematical Principles (PR 7.D) . . . . . . . . . . . . . . 324
7.2 Analysis and Design of Active Resistor Circuits. . . . . . . . . . . . . . . . . . 324
7.2.1 Active Resistor Circuits Based on the
First Mathematical Principle (PR 7.1) . . . . . . . . . . . . . . . . . . . . . 324
7.2.2 Active Resistor Circuits Based on the
Second Mathematical Principle (PR 7.2) . . . . . . . . . . . . . . . . . . 341
7.2.3 Active Resistor Circuits Based on the
Third Mathematical Principle (PR 7.3) . . . . . . . . . . . . . . . . . . . . 346
7.2.4 Active Resistor Circuits Based on the
Fourth Mathematical Principle (PR 7.4). . . . . . . . . . . . . . . . . . . 349
7.2.5 Active Resistor Circuits Based on the
Fifth Mathematical Principle (PR 7.5). . . . . . . . . . . . . . . . . . . . . 352
7.2.6 Active Resistor Circuits Based on Different
Mathematical Principles (PR 7.D) . . . . . . . . . . . . . . . . . . . . . . . . . 356
7.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

8 Multifunctional Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

8.1 Mathematical Analysis for Synthesis
of Multifunctional Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
8.1.1 First Mathematical Principle (PR 8.1) . . . . . . . . . . . . . . . . . . . . . 363
8.1.2 Second Mathematical Principle (PR 8.2) . . . . . . . . . . . . . . . . . . 371
8.1.3 Third Mathematical Principle (PR 8.3) . . . . . . . . . . . . . . . . . . . . 374
8.1.4 Fourth Mathematical Principle (PR 8.4). . . . . . . . . . . . . . . . . . . 374
8.2 Analysis and Design of Multifunctional Structures . . . . . . . . . . . . . . . 385
8.2.1 Multifunctional Structures Based on the
First Mathematical Principle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
8.2.2 Multifunctional Structures Based on the
Second Mathematical Principle. . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
8.2.3 Multifunctional Structures Based on the
Third Mathematical Principle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
8.2.4 Multifunctional Structures Based on the
Fourth Mathematical Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
8.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
Contents xv

Appendix 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

Appendix 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
Chapter 1
Differential Structures

1.1 Mathematical Analysis for Synthesis

of Differential Amplifiers

Elementary mathematical principles represent the functional basis for designing

differential structures [1–55], each theoretical principle corresponding to a class of
differential amplifiers. Usually, the proper operation of these circuits uses a biasing
in saturation of MOS active devices. The notations of variables are: V1 and V2
represent the input potentials, IOUT signifies the output current, while, usually, VO ,
VO1 and VO2 constant voltages are introduced for modeling a voltage shifting. In
order to obtain a differential structure able to amplify with small distortions an input
signal, a linear behavior of the circuit must be implemented.

1.1.1 First Mathematical Principle (PR 1.1)

The first mathematical principle used for implementing differential amplifiers is

based on the following relations:
pffiffiffiffi pffiffiffiffi
IOUT ¼ A I2  I1
rffiffiffiffi
K K
I1 ¼ ðVGS1  VT Þ2 ) IOUT ¼A ðV2  V1 Þ
2 2
K
I2 ¼ ðVGS2  VT Þ2
2
VGS2  VGS1 ¼ V2  V1 ð1:1Þ

The differential amplifiers based on the previous relation compute a current

proportional with the differential input voltage, V2  V1

C.R. Popa, Synthesis of Computational Structures for Analog Signal Processing, 1

DOI 10.1007/978-1-4614-0403-3_1, # Springer Science+Business Media, LLC 2011
2 1 Differential Structures

1.1.2 Second Mathematical Principle (PR 1.2)

The mathematical relation that models this principle is:

 2  2  2  2
V1 V2 V2 V1
 VO1   VO1 þ VO2   VO2 
2 2 2 2
   
V1  V2 V1 þ V2 V1  V2 V1 þ V2
¼  2VO1 þ 2VO2 
2 2 2 2
¼ ðVO2  VO1 ÞðV1  V2 Þ ¼ ct: ðV1  V2 Þ ð1:2Þ

The circuits that use this principle generate a current proportional with the
differential input voltage, V1  V2 .

1.1.3 Third Mathematical Principle (PR 1.3)

This principle is illustrated by the following mathematical relation:

h i h i
AðV1  V2 Þ2 þ BðV1  V2 Þ þ C  AðV1  V2 Þ2  BðV1  V2 Þ þ C
¼ 2BðV1  V2 Þ ð1:3Þ

The output current will be also proportional with the differential input voltage,
V1  V2

1.1.4 Fourth Mathematical Principle (PR 1.4)

The mathematical relation that models this principle is:

     
V1 2 V1 2 V1 2
V C  V O  VT þ þ VO  VT þ  VC  VO  VT 
2 2 2
 2
V1
 VO  V T  ¼ V1 ð2VC  2VO  2VT Þ
2
þ V1 ð2VO  2VT Þ ¼ 2V1 ðVC  2VT Þ ð1:4Þ

The output current of the differential amplifier is linearly dependent on the input
voltage, V1 .
1.1 Mathematical Analysis for Synthesis of Differential Amplifiers 3

1.1.5 Fifth Mathematical Principle (PR 1.5)

The fifth mathematical principle can be written as follows:

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
 
V 1  V2 K
IOUT ¼ 4K IO þ ðV1  V2 Þ  K 2 ðV1  V2 Þ2 2
2 4
pffiffiffiffiffiffiffiffi
¼ KIO ðV1  V2 Þ (1.5)

1.1.6 Sixth Mathematical Principle (PR 1.6)

The method modeled by this mathematical principle, used for linearizing the
transfer characteristic of differential structures, uses an anti-parallel connection of
two differential amplifiers, the controlled asymmetries between their biasing
currents, also between the aspect ratios of their transistors fulfilling this desiderate.

1.1.7 Seventh Mathematical Principle (PR 1.7)

This principle is useful for obtaining a rail-to-rail operation of a differential struc-

ture, based on a parallel connection of two complementary differential amplifiers.
The mathematical relations of this principle are shown in the following lines:
pffiffiffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffi
IOUT ¼ 2K IOp þ IOn ðV1  V2 Þ (1.6)

pffiffiffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffi

IOn þ IOp ¼ 2 IO (1.7)

resulting:
pffiffiffiffiffiffiffiffiffiffi
IOUT ¼ 8KIO ðV1  V2 Þ (1.8)

1.1.8 Different Mathematical Principle for Differential

Amplifiers (PR 1.D)

There are some circuits based on different mathematical principles that are useful
for linearizing the behavior of differential amplifiers.
4 1 Differential Structures

1.2 Analysis and Design of Differential Structures

The classical MOS differential presents a strong nonlinear behavior, as a result

of the quadratic characteristic of their constitutive transistors biased in saturation
region. In order to improve the linearity of the structure, it is necessary to develop
efficient linearization techniques, functional mathematical principles being elaborated
for fulfilling this desiderate.
Based on the previous presented mathematical analysis, it is possible to design
different types of differential structures, included in eight classes, corresponding to
the previous presented eight mathematical principles (PR 1.1 – PR 1.7 and PR 1.D).
The MOS differential amplifier represents a fundamental block in analog design,
having a large area of applications. The analysis of the large signal operation for the
classical MOS differential structure (Fig. 1.1) [1, 2] can quantitatively evaluate
the circuit’s nonlinearity, being possible to determine the weight of each superior-
order distortion introduced by the structure nonlinearity.
The VI ¼ V1  V2 differential input voltage can be expressed as follows:
rffiffiffiffiffiffi! rffiffiffiffiffiffi! rffiffiffiffi
2I1 2I2 2 pffiffiffiffi pffiffiffiffi
VI ¼ VGS1  VGS2 ¼ VT þ  VT þ ¼ I1  I2 (1.9)
K K K

Squaring and replacing the sum I1 þ I2 with IO , it results:

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi KV 2
2 I1 ðIO  I1 Þ ¼ IO  I (1.10)
2

The resultant second-order equation will be:

 2
1 KVI2
I12  IO I1 þ IO  ¼0 (1.11)
4 2

I1 I2

V1 M1 M2 V2

IO RO

Fig. 1.1 Classical MOS

differential structure
1.2 Analysis and Design of Differential Structures 5

having the following solutions:

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
IO IO KVI2 K 2 VI4
ðI1 Þ1;2 ¼   2 (1.12)
2 2 IO 4IO

so:
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
IO IO KVI2 K 2 VI4 IO IO KVI2 K 2 VI4
I1 ¼ þ  2 ; I2 ¼   2 (1.13)
2 2 IO 4IO 2 2 IO 4IO

The output differential current will be:

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
KVI2 K 2 VI4 VI
I2  I1 ¼ IO  2 ¼ 4KIO  K 2 VI2 (1.14)
IO 4IO 2

The ðI2  I1 ÞðVI Þ function is strongly nonlinear, the quantitative evaluation of its
nonlinearity being possible using a Taylor series expansion. So, it is necessary to
compute the superior-order derivates of the following function:
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
f ðVI Þ ¼ 4KIO  K 2 VI2 (1.15)

and their values for VI ¼ 0 The first-order derivate is:

 1=2
f 0 ðVI Þ ¼ K 2 VI 4KIO  K 2 VI2 (1.16)

while the second-order one has the following expression:

 3=2
f 00 ðVI Þ ¼ 4K 3 IO 4KIO  K 2 VI2 (1.17)

resulting:

f 0 ðVI ÞjVI ¼0 ¼ 0 (1.18)

1 1=2
f 00 ðVI ÞjVI ¼0 ¼  K 3=2 IO (1.19)
2

The Taylor series expansion of the function (1.14) gives:

1=2 K 3=2 K 5=2

ðI2  I1 Þ ðVI Þ ¼ K 1=2 IO VI þ 1=2
VI3 þ 3=2
VI5 þ    (1.20)
8IO 128IO
6 1 Differential Structures

Fig. 1.2 The I1 ðVI Þ and I2 ðVI Þ dependencies for the classical differential amplifier

or:

ðI2  I1 Þ ðVI Þ ¼ a1 VI þ a3 VI3 þ a5 VI5 þ    (1.21)

The first term is linearly dependent on the input voltage, while the last two terms
model the third-order and fifth-order nonlinearities of the differential structure.
The dependencies of the drain currents I1 and I2 on the differential input
voltage VI for the differential amplifier from Fig. 1.1 are presented in Fig. 1.2.
Considering a load resistance RL ¼ 10 k O, the simulation of the transfer char-
acteristic VO ðVI Þ ¼ RL ðI2  I1 Þ ðVI Þ for the differential amplifier presented in
Fig. 1.1 is shown in Fig. 1.3.
The simulation of the transfer characteristic VO ðVI Þ for a maximal input range
between  0:4 V and 0:4 V and a biasing current IO having the values 0:1 mA,
0:2 mA and 0:3 mA is shown in Fig. 1.4. It could be remarked an increasing
of the differential-mode voltage gain for an increasing of the biasing current IO
(using
pffiffiffi relation (1.20)), the doubling of the biasing current generating an increasing
of 2 of the voltage gain.
The voltage gain is  10:95 (using relation (1.20)), while the simulated value
is  10:43.
Fig. 1.5 presents the simulation of the transfer characteristic of the differential
amplifier for different values of the common-mode input voltage VC ¼ ðV1 þ V2 Þ=2
(between 1 V and 1:3 V), showing a minimal value of VC of about 1:2 V. The
simulation was made considering a passive load attached to the differential amplifier
from Fig. 1.1, having R1 ¼ R2 ¼ 10 k O and a supply voltage VDD ¼ 9 V.
1.2 Analysis and Design of Differential Structures 7

Fig. 1.3 The VO ðVI Þ dependence for the classical differential amplifier

Fig. 1.4 Parametric VO ðVI Þdependence for the classical differential amplifier

Figure 1.6 represents the simulation of the transfer characteristic of the differential
amplifier for different values of the common-mode input voltage VC ¼ ðV1 þ V2 Þ=2
(between 8:9 V and 9:1 V), showing a maximal value for VC of about 9 V.
The simulation was made considering a particular implementation of the current
source IO from Fig. 1.1 using a classical current mirror.
8 1 Differential Structures

Fig. 1.5 The VO ðVI Þ dependence for multiple common-mode input voltages (1)

Fig. 1.6 The VO ðVI Þ dependence for multiple common-mode input voltages (2)

1.2.1 Differential Structures Based on the First Mathematical

Principle (PR 1.1)

The method for obtaining a linear transfer characteristic of the differential amplifier
based on the first mathematical principle (PR 1.1) uses the compensation of the
squaring characteristic of the MOS transistor biased in saturation using comple-
mentary square-root circuits.
1.2 Analysis and Design of Differential Structures 9

Fig. 1.7 Differential VDD

structures (1) based on PR 1.1
M1a V1 V2 M2a
Ka Ka

VO
M1b M2b
Kb Kb

I1 I2

M1 M2
V1 K K

V2

IO

-VDD

The first circuit using this method is shown in Fig. 1.7 [3] and it uses two
square-root circuits for improving the linearity of the differential amplifier.
Using relation that describes the operation of M1a–M1b and M2a–M2b square-
root circuits, the output voltage of the differential amplifier from Fig. 1.7 will be:
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffi
pffiffiffiffiffiffi 1 1 1 pffiffiffiffiffiffi 1 1 1
VO ¼ V2  V1 ¼ 2I2 þ   2I1 þ  (1.22)
Ka Kb Kb K a Kb Kb

Because:
rffiffiffiffi rffiffiffiffi
pffiffiffiffi pffiffiffiffi K K
I2  I1 ¼ ðVGS2  VGS1 Þ ¼ ðV2  V1 Þ (1.23)
2 2

it results:
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffi
pffiffiffiffi 1 1 1
VO ¼ K þ  ðV2  V1 Þ (1.24)
Ka K b Kb

equivalent with a linear dependence of the output voltage on the differential input
voltage.
10 1 Differential Structures

VDD

V1 V2
M7 M5 M6 M8
IOUT1 I3 I3 I4 I4 IOUT2

I1 I2
VC
M1 M2

M3 M4

Fig. 1.8 Differential structures (2) based on PR 1.1

The principle of operation for the differential amplifier shown in Fig. 1.8 [4] is
based on the compensation of the squaring characteristic of parallel-coupled differ-
ential amplifiers M5–M6 and M7–M8 by two square-rooting circuits, M1–M3 and
M2–M4. The principle of operation is similar with the principle of the circuit
presented in Fig. 1.7, the advantage being the exclusively biasing in saturation of
all MOS transistors.
The differential output current of the circuit can be expressed as follows:

IOUT1  IOUT2 ¼ ðI3  I1 Þ  ðI4  I2 Þ (1.25)

The constant potential VC is equal with the difference between two gate-source
voltages. Supposing a biasing in saturation of all identical MOS transistors, it results:
rffiffiffiffiffiffi rffiffiffiffiffiffi
2I1 2I3
VC ¼ VGS1  VSG3 ¼  (1.26)
K K

So:
rffiffiffiffi
pffiffiffiffi pffiffiffiffi K
I1 ¼ I3 þ VC (1.27)
2

resulting:

K 2 pffiffiffiffiffiffiffiffiffiffi
I1 ¼ I 3 þ V þ 2KI3 VC (1.28)
2 C

and, similarly:

K 2 pffiffiffiffiffiffiffiffiffiffi
I2 ¼ I 4 þ V þ 2KI4 VC (1.29)
2 C
1.2 Analysis and Design of Differential Structures 11

VDD

M1 M2
4K 4K
I1 I2

M3 M4

M5 M6 M7 M8
4K 4K
I5 I8
IO IO
IOUT1 IOUT2

Fig. 1.9 Current-mode square-root circuit (1)

From (1.25), (1.28) and (1.29), it results a square-root dependence of the

differential output current on the input currents:
pffiffiffiffiffiffi pffiffiffiffi pffiffiffiffi
IOUT1  IOUT2 ¼ 2K VC I4  I3 (1.30)
pffiffiffiffi pffiffiffiffi
The differential expression I4  I3 is a function of the input potentials V1
and V2 , as follows:
rffiffiffiffi rffiffiffiffi
pffiffiffiffi pffiffiffiffi K K
I4  I3 ¼ ðVSG6  VT Þ  ðVSG5  VT Þ
2 2
rffiffiffiffi rffiffiffiffi
K K
¼ ðVSG6  VSG5 Þ ¼ ðV1  V2 Þ ð1:31Þ
2 2

From (1.30) and (1.31), it results a linear dependence of the output current on the
differential input voltage:

IOUT1  IOUT2 ¼ KVC ðV1  V2 Þ (1.32)

Alternate implementations of square-root circuits used for linearizing the transfer

characteristic of the classical differential amplifier are shown in Figs. 1.9–1.13 [4].
For the square-root circuit shown in Fig. 1.9, the translinear loop realized using
M1, M3, M5 and M6 transistors has the following characteristic equation:

VSG3 þ VSG6 ¼ VSG1 þ VSG5 (1.33)

So:
pffiffiffiffiffi pffiffiffiffi pffiffiffiffi
IO þ I1 ¼ I5 (1.34)
12 1 Differential Structures

VDD

I1 I2

M1 M2 M3 M4
VB2
VB1 VB1
M5 M6 M7 M8

I5 I8

IOUT1 IOUT2

Fig. 1.10 Current-mode square-root circuit (2)

VDD

M5 M6

VC VC

M2 M1 M4 M3
IOUT1 ID2 I1 I2 ID3 IOUT2
I1 I1 I2 I2

Fig. 1.11 Current-mode square-root circuit (3)

VDD

VC M5

I1 I2
M6
M1 M2

M3 M4
IO
I I’

Fig. 1.12 Current-mode IOUT1 IOUT2

square-root circuit (4)
1.2 Analysis and Design of Differential Structures 13

VDD
VC
M1 M2

M3 M4

IOUT1 I3 I4 IOUT2

I1 I1 I2 I2

Fig. 1.13 Current-mode square-root circuit (5)

Squaring the previous relation, it is possible to write that:

pffiffiffiffiffiffiffiffi
I5 ¼ IO þ I1 þ 2 IO I1 (1.35)

In a similar way, it results, from the right part of the circuit:

pffiffiffiffiffiffiffiffi
I8 ¼ IO þ I2 þ 2 IO I2 (1.36)

The differential output current of the squaring structure can be expressed as

follows:
pffiffiffiffiffipffiffiffiffi pffiffiffiffi
IOUT1  IOUT2 ¼ ðI5 þ I2 Þ  ðI8 þ I1 Þ ¼ 2 IO I1  I2 (1.37)

In order to obtain a linear differential amplifier, the square-root circuit shown in

Fig. 1.9 must have as input currents the drain currents I1 and I2 of a classical
differential amplifier M9–M10, resulting the circuit presented in Fig. 1.14. [4]
The differential output current of this circuit can be obtained replacing the
expressions of I1 and I2 drain currents by their squaring dependencies on the gate-
source voltages:
rffiffiffiffi
pffiffiffiffiffi K pffiffiffiffiffiffiffiffiffiffi
IOUT1  IOUT2 ¼ 2 IO ðVSG9  VSG10 Þ ¼ 2KIO ðV2  V1 Þ (1.38)
2

For the square-root circuit presented in Fig. 1.10, the translinear loop achieved
using M1, M2, M5 and M6 transistors has the following characteristic equation:

VB2  VB1 ¼ ðVGS1 þ VSG5 Þ  ðVGS2 þ VSG6 Þ (1.39)

resulting:
rffiffiffiffi
K pffiffiffiffi pffiffiffiffi
ðVB2  VB1 Þ ¼ 2 I5  2 I1 (1.40)
2
14 1 Differential Structures

VDD

IO

M1 V1 V2 M2
4K 4K
M9 M10
I1 I2
M3 M4

M5 M6 M7 M8
4K
I5 I8
IO IO
IOUT1 IOUT2

Fig. 1.14 Differential structures (3) based on PR 1.1

or:
rffiffiffiffi
pffiffiffiffi pffiffiffiffi VB2  VB1 K
I5 ¼ I1 þ (1.41)
2 2

Squaring the previous relation, it results:

rffiffiffiffiffiffiffi
KI1 ðVB2  VB1 Þ2
I5 ¼ I1 þ ðVB2  VB1 Þ þ K (1.42)
2 8

and, similarly:
rffiffiffiffiffiffiffi
KI2 ðVB2  VB1 Þ2
I8 ¼ I2 þ ðVB2  VB1 Þ þ K (1.43)
2 8

The differential output current can be expressed as follows:

IOUT1  IOUT2 ¼ ðI5 þ I2 Þ  ðI8 þ I1 Þ (1.44)

From (1.42)–(1.44), the expression of the differential output current becomes:

rffiffiffiffi
K pffiffiffiffi pffiffiffiffi
IOUT1  IOUT2 ¼ ðVB2  VB1 Þ I1  I 2 (1.45)
2

The implementation of a differential amplifier using this square-root circuit is

shown in Fig. 1.15 [4].
1.2 Analysis and Design of Differential Structures 15

VDD
IO

V1 V2
M9 M10
I1 I2

M1 M2 M3 M4
VB2
VB1 VB1
M5 M6 M7 M8

I5 I8

IOUT1 IOUT2

Fig. 1.15 Differential structures (4) based on PR 1.1

The differential output current of the linear differential amplifier from Fig. 1.15
can be obtained replacing I1 and I2 currents by their squaring dependencies on the
gate-source voltages:

K K
IOUT1  IOUT2 ¼ ðVB2  VB1 Þ ðVSG9  VSG10 Þ ¼ ðVB2  VB1 Þ ðV2  V1 Þ (1.46)
2 2

equivalent with:

K
Gm ¼ ðVB2  VB1 Þ (1.47)
2

The square-root circuit presented in Fig. 1.11 is composed from two identical
cores (M1–M2 and M3–M4), each of them computing the square-root function of
an input current. For M1–M2 pair, VC input voltage can be expressed as follows:
rffiffiffiffi
2 pffiffiffiffiffiffi pffiffiffiffi
VC ¼ VSG2  VSG1 ¼ ID2  I1 (1.48)
K

So:
rffiffiffiffi
pffiffiffiffiffiffi K pffiffiffiffi
ID2 ¼ VC þ I1 (1.49)
2
16 1 Differential Structures

VDD

M5 M6

VC VC
M2 M1 M4 M3
I1 I2
IOUT1 ID1 ID3 IOUT2
I1 I1 I2 I2

V1 M7 M8 M9 M10 V2

-VDD

Fig. 1.16 Differential structures (5) based on PR 1.1

or:

K 2 pffiffiffiffiffiffi pffiffiffiffi
ID2 ¼ I1 þ V þ 2K VC I1 (1.50)
2 C

The expression of the first output current will be:

K 2 pffiffiffiffiffiffi pffiffiffiffi
IOUT1 ¼ ID2  I1 ¼ V þ 2K VC I1 (1.51)
2 C

Similarly:

K 2 pffiffiffiffiffiffi pffiffiffiffi
IOUT2 ¼ V þ 2K VC I2 (1.52)
2 C

resulting the following expression of the differential output current:

pffiffiffiffiffiffi pffiffiffiffi pffiffiffiffi
IOUT1  IOUT2 ¼ 2K VC I1  I2 (1.53)

Attaching two parallel-connected classical differential amplifiers to the double

square-root circuit presented in Fig. 1.11, it results a differential amplifier with a
linear transfer characteristic (Fig. 1.16) [4].
For this circuit, the differential input voltage can be expressed as follows:
rffiffiffiffi
2 pffiffiffiffi pffiffiffiffi
V1  V2 ¼ VGS7  VGS10 ¼ I1  I2 (1.54)
K
1.2 Analysis and Design of Differential Structures 17

From (1.53) and (1.54), it is possible to obtain the expression of the differential
output current as a function on the differential input voltage:

IOUT1  IOUT2 ¼ KVC ðV1  V2 Þ (1.55)

so an equivalent transconductance of the circuit expressed by:

Gm ¼ KVC (1.56)

For the square-root circuit shown in Fig. 1.12, the translinear loop realized using
M1, M3, M5 and M6 transistors has the following characteristic equation:

VSG1 þ VSG3 ¼ VSG5 þ VSG6 (1.57)

Noting VSG5 þ VSG6 with VC , it results:

rffiffiffiffi
pffiffi K pffiffiffiffi
I¼ ðVC  2VT Þ  I1 (1.58)
2

So:

K pffiffiffiffiffiffiffiffiffiffi
I ¼ I1 þ ðVC  2VT Þ2  2KI1 ðVC  2VT Þ (1.59)
2

The expression of the first output current will be:

K pffiffiffiffiffiffiffiffiffiffi
IOUT1 ¼ I þ I2 ¼ I1 þ I2 þ ðVC  2VT Þ2  2KI1 ðVC  2VT Þ (1.60)
2

and, similarly:

K pffiffiffiffiffiffiffiffiffiffi
IOUT2 ¼ I1 þ I2 þ ðVC  2VT Þ2  2KI2 ðVC  2VT Þ (1.61)
2

The differential output current can be expressed as follows:

pffiffiffiffiffiffi pffiffiffiffi pffiffiffiffi
IOUT1  IOUT2 ¼ 2K ðVC  2VT Þ I2  I1 (1.62)

The biasing voltage is equal with:

rffiffiffiffiffiffiffi
2IO
VC ¼ VSG5 þ VSG6 ¼ 2VT þ 2 (1.63)
K

Replacing (1.63) in (1.62), it can be obtained:

pffiffiffiffiffipffiffiffiffi pffiffiffiffi
IOUT1  IOUT2 ¼ 4 IO I2  I1 (1.64)
18 1 Differential Structures

Fig. 1.17 Differential VDD

structures (6) based on PR 1.1
IO

V1 V2
M7 M8
M5
I1 I2
M6
M1 M2

M3 M4
IO
I I’

IOUT1 IOUT2

The implementation of a differential amplifier using this square-root circuit is

presented in Fig. 1.17 [4, 5].
The differential output current of the linear differential amplifier from Fig. 1.17
can be obtained replacing the currents I1 and I2 by their squaring dependencies
on the gate-source voltages:
rffiffiffiffi
pffiffiffiffiffi K pffiffiffiffiffiffiffiffiffiffi
IOUT1  IOUT2 ¼ 4 IO ðVSG8  VSG7 Þ ¼ 8KIO ðV1  V2 Þ (1.65)
2

The equivalent transconductance of the circuit can be expressed as follows:

pffiffiffiffiffiffiffiffiffiffi
Gm ¼ 8KIO (1.66)

Another possible implementation of a square-root circuit based on a similar

principle is shown in Fig. 1.13.
The VC potential can be expressed as follows:
rffiffiffiffi
2 pffiffiffiffi pffiffiffiffi
VC ¼ VSG3  VGS1 ¼ I3  I1 (1.67)
K

resulting:
rffiffiffiffi
pffiffiffiffi pffiffiffiffi K
I3 ¼ I1 þ VC (1.68)
2

Squaring the previous relation, the expression of I3 current will be:

K 2 pffiffiffiffiffiffiffiffiffiffi
I3 ¼ I 1 þ V þ 2KI1 VC (1.69)
2 C
1.2 Analysis and Design of Differential Structures 19

VDD

VC
M1 M2

M3 M4

IOUT1 I3 I4 IOUT2

I1 I1 I2 I2
M5 M6 M7 M8
V1 V2

Fig. 1.18 Differential structures (7) based on PR 1.1

and, similarly:

K 2 pffiffiffiffiffiffiffiffiffiffi
I4 ¼ I 2 þ V þ 2KI2 VC (1.70)
2 C

The output currents have the following expressions:

K 2 pffiffiffiffiffiffiffiffiffiffi
IOUT1 ¼ I3  I1 ¼ V þ 2KI1 VC (1.71)
2 C

and:

K 2 pffiffiffiffiffiffiffiffiffiffi
IOUT2 ¼ I4  I2 ¼ V þ 2KI2 VC (1.72)
2 C

So, the differential output current will be:

pffiffiffiffiffiffi pffiffiffiffi pffiffiffiffi
IOUT1  IOUT2 ¼ 2K VC I1  I2 (1.73)

The implementation of a differential amplifier using this square-root circuit is

presented in Fig. 1.18 [4]. The I1 and I2 currents are generated by two parallel-
connected differential amplifiers, M5–M8 and M6–M7, respectively.
The differential output current of the linear differential amplifier from Fig. 1.18
can be obtained replacing the I1 and I2 currents by their squaring dependencies on
the gate-source voltages of M5–M8 transistors:
rffiffiffiffi
pffiffiffiffiffiffi K
IOUT1  IOUT2 ¼ 2K VC ðVGS5  VGS8 Þ ¼ K VC ðV1  V2 Þ (1.74)
2
20 1 Differential Structures

VDD

IOUT1’ IO IO IOUT2’
SQR SQR

I1 I2

V1 M1 M2 V2
IOUT
I1 + I2

Fig. 1.19 Differential structures (8) based on PR 1.1

resulting:

Gm ¼ KVC (1.75)

The same method for improving the linearity of the classical differential
amplifier is used for designing the following differential amplifier. The principle
is presented in Fig. 1.19, while the implementation of square-root circuits from
Fig. 1.19 [4, 6] is shown in Fig. 1.20a [7].

1.2.1.1 The FGMOS Transistor

The multiple-input floating-gate transistor (M from Fig. 1.20a) is an ordinary MOS

device whose gate is floating. The basic structure of a n-channel floating-gate MOS
transistor is shown in Fig. 1.20b. The first silicon layer forms the floating-gate over
the channel, while the second polysilicon layer forms the multiple input gates,
which is located over the floating-gate. This floating-gate is capacitive coupled
to the multiple input gates. The symbolical representation of such devices with n
inputs is shown in Fig. 1.20c.
The drain current of a FGMOS transistor with n-input gates working in the
saturation region is given by the following equation:
" #2
K Xn
ID ¼ ki ðVi  VS Þ  VT (1.76)
2 i¼1

where K ¼ mn Cox ðW=LÞ is the transconductance parameter of the transistor, mn is

the electron mobility, Cox is the gate oxide capacitance, W=L is the transistor aspect
1.2 Analysis and Design of Differential Structures 21

a b
VDD V 1 V2 ... ... Vn
C1 C2 ... ... Cn
D S
floating-
gate
n+ n+
IOUT1,2’
p substrat
IO
I1,2 IO I
M c V1 V2 Vn
... ...
4K
M1/
M2 MO
K K
D S
-VDD
B

Fig. 1.20 Current-mode square-root circuit (6)

ratio, ki ; i ¼ 1; :::; n are the capacitive coupling ratios, Vi is the ith input voltage,
VS is the source voltage and VT is the threshold voltage of the transistor. The
capacitive coupling ratio is defined as:

Ci
ki ¼ P
n (1.77)
Ci þ CGS
i¼1

Ci represent the input capacitances between the floating-gate and each of the i-th
input and CGS is the gate-source capacitance. Equation (1.76) shows that the
FGMOS transistor drain current in saturation is proportional with the square of
the weighted sum of the input signals, where the weight of each input signal is
determined by the capacitive coupling ratio of the input.
The drain current of M transistors from Fig. 1.20a can be expressed as follows:
 2
4K VGSO þ VGS1;2
I¼  VT (1.78)
2 2

while VGSO and VGS1;2 expressions can be obtained from the squaring dependencies
of the drain currents of MO and M1/M2 transistors on their gate-source voltages
pffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
VGSO ¼ VT þ 2IO =K and VGS1;2 ¼ VT þ 2I1;2 =K . So:

pffiffiffiffiffi pffiffiffiffiffiffiffi 2 pffiffiffiffiffiffiffiffiffiffiffi

I¼ IO þ I1;2 ¼ IO þ I1;2 þ 2 IO I1;2 (1.79)

resulting:
pffiffiffiffiffiffiffiffiffiffiffi
IOUT1;2 0 ¼ I  IO  I1;2 ¼ 2 I1;2 IO (1.80)
22 1 Differential Structures

VDD

M5 M6

M9 M10
I1 I2 IOUT1
I2 I1 I2 I1 I1’ I 2' IOUT2
V2 M2 M1 V1 M3 M7 M8 M4

VC2

VC1

Fig. 1.21 Differential structures (9) based on PR 1.1

The circuit shown in Fig. 1.19 will have a linear transfer characteristic:
pffiffiffiffiffipffiffiffiffi pffiffiffiffi
IOUT ¼ IOUT1 0  IOUT2 0 ¼ 2 IO I1  I2
rffiffiffiffi
pffiffiffiffiffi K pffiffiffiffiffiffiffiffiffiffi
¼ 2 IO ðVGS1  VGS2 Þ ¼ 2KIO ðV1  V2 Þ ¼ Gm ðV1  V2 Þ ð1:81Þ
2
pffiffiffiffiffiffiffiffiffiffi
Gm ¼ 2KIO being the circuit transconductance. So, in a first-order analysis, the
dependence of the output current of the differential circuit on its differential input
voltage is perfectly linear.
A similar method used for linearizing the transfer characteristic of the differen-
tial amplifier is presented in Fig. 1.21 [8].
The elementary differential amplifier is composed by M1 and M2 transistors.
The linearization of its transfer characteristic is realized using two square-root
circuits (M3–M6 and M7–M10), their operation being characterized by the follow-
ing relations:
rffiffiffiffi
2 pffiffiffiffi pffiffiffiffiffi0
VC2 ¼ VGS7  VGS8 ¼ I1  I 1 (1.82)
K

resulting:

K 2 pffiffiffiffiffiffi pffiffiffiffi
I1 0 ¼ I 1 þ VC2  2K VC2 I1 (1.83)
2
The output current of the first square-root circuit is:

K 2 pffiffiffiffiffiffi pffiffiffiffi
IOUT1 ¼ I1  I1 0 ¼  VC2 þ 2K VC2 I1 (1.84)
2
1.2 Analysis and Design of Differential Structures 23

Similarly, for the second square-root circuit, the output current can be expressed
as follows:

K 2 pffiffiffiffiffiffi pffiffiffiffi
IOUT2 ¼ I2  I2 0 ¼  VC2 þ 2K VC2 I2 (1.85)
2

Because:

IOUT ¼ IOUT2  IOUT1 (1.86)

it can be obtained:
pffiffiffiffiffiffi pffiffiffiffi pffiffiffiffi
IOUT ¼ 2K VC2 I1  I2 (1.87)

As all MOS transistors are biased in saturation region, the differential input
voltage of the M1–M2 differential amplifier depends on the difference of the
square-roots of the drain currents, I1 and I2 :
rffiffiffiffi
2 pffiffiffiffi pffiffiffiffi
V1  V2 ¼ VGS1  VGS2 ¼ I1  I2 (1.88)
K

From the previous relations it results:

IOUT ¼ KVC2 ðV1  V2 Þ (1.89)

equivalent with a constant transconductance of the entire differential amplifier

presented in Fig. 1.21, Gm ¼ KVC2 .
Comparing with the previous similar circuit, the linear differential amplifier
from Fig. 1.21 presents the important advantage of implementing also the multiplier
function (VC2 and V1  V2 can be considered as input voltages).

1.2.2 Differential Structures Based on the Second

Mathematical Principle (PR 1.2)

The symmetrical circuit presented in Fig. 1.22 [9] represents a differential amplifier
having the transfer characteristic linearized using the second mathematical princi-
ple (PR 1.2).
The gate-source voltages of M1a and M4a transistors are equal because they
are identical and are biased at the same drain current I1a . As V1 ¼ VGS1a þ VGS4a ,
24 1 Differential Structures

IOUT1 IOUT2

I1a I3a IO I3b I1b

M1a M3a VO M3b M1b
V1 V2
4K 4K

M5
M2a M2b
M4a 4K M6 4K M4b

M7

Fig. 1.22 Differential structures (1) based on PR 1.2

it results that the gate potential of M2a transistor is V1 =2. Similarly, the gate-source
voltages of M2a and M3a are equal, resulting:
rffiffiffiffiffiffiffiffi!
V1 2I3a
VO  ¼ 2VGS3a ¼ 2 VT þ (1.90)
2 4K

equivalent with:
 2
K V1
I3a ¼ VO   2VT (1.91)
2 2

and:
 2
K V1
I1a ¼  VT (1.92)
2 2

The difference between the previous currents can be expressed as follows:

K
I1a  I3a ¼ ðVO  3VT Þ ðV1  VO þ VT Þ (1.93)
2

Similarly, the I1b  I3b differential current will have the following expression:

K
I1b  I3b ¼ ðVO  3VT Þ ðV2  VO þ VT Þ (1.94)
2
1.2 Analysis and Design of Differential Structures 25

Fig. 1.23 Differential

structures (2) based on PR 1.2 IOUT1 IOUT2

I1 I4
V1 M1 M4 V2
I2 I5
M2 M5
M3 M6

VC

Thus, the total differential output current of the circuit, IOUT1  IOUT2 , will be:

IOUT1  IOUT2 ¼ ðI1a þ I3b Þ  ðI1b þ I3a Þ ¼ ðI1a  I3a Þ

K (1.95)
 ðI1b  I3b Þ ¼ ðVO  3VT ÞðV1  V2 Þ
2

The VO biasing voltage is implemented as a current-controlled voltage source,

this realization having the advantage of removing the dependence of the circuit
performances on the variation of the threshold voltage with temperature and
technological parameters:
rffiffiffiffiffiffiffi!
2IO
VO ¼ 3VGS5 ¼ 3 VT þ (1.96)
K

For this particular realization of the voltage source VO , the total differential
output current becomes:
rffiffiffiffiffiffiffiffi
KIO
IOUT1  IOUT2 ¼3 ðV1  V2 Þ (1.97)
2

It was obtained a linear dependence of the output current on the differential input
voltage, resulting an equivalent transconductance of the entire structure that can be
controlled by the IO biasing current:
rffiffiffiffiffiffiffiffi
IOUT1  IOUT2 KIO
Gm ¼ ¼3 (1.98)
V1  V2 2

An alternate implementation of a linear differential amplifier using the same

linearization principle is presented in Fig. 1.23 [9].
26 1 Differential Structures

The differential output current of the circuit can be expressed as follows:

IOUT ¼ IOUT1  IOUT2 ¼ ðI1 þ I5 Þ  ðI2 þ I4 Þ ¼ ðI1  I2 Þ  ðI4  I5 Þ (1.99)

Because M1 and M3 transistors are identical and they are biased at the same
drain current, their gate-source voltages will be equal, so:

 2
K V1
I1 ¼  VT (1.100)
2 2

and:

 2
K V1
I2 ¼  VC  V T (1.101)
2 2

Similarly, for the right part of the circuit, the expressions of the drain currents are:

 2
K V2
I4 ¼  VT (1.102)
2 2

and:

 2
K V2
I5 ¼  VC  V T (1.103)
2 2

resulting:

K K K
IOUT ¼ VC ðV1  VC  2VT Þ  VC ðV2  VC  2VT Þ ¼ VC ðV1  V2 Þ (1.104)
2 2 2

the equivalent transconductance being expressed by:

K
Gm ¼ VC (1.105)
2

The circuit presented in Fig. 1.23 presents the disadvantage of requiring a

current from the VC voltage source. In order to avoid a current consumption from
the external VC voltage source, the circuit presented in Fig. 1.23 can be modified,
as it is shown in Fig. 1.24.
1.2 Analysis and Design of Differential Structures 27

IOUT1 IOUT2

I1 I5

V1 M1 M5 V2
I2 IO 4IO IO I6

M2 M4 M8 M6
VC VC
M3 M7
I2 + I O M9 I6+ IO

Fig. 1.24 Differential structures (2) based on PR 1.2 with implementation of VC source

The VC potential is obtained as the difference between the gate-source of

M9 transistor (biased at 4IO current) and the gate sources of M4 or M8 transistors
(working at IO current):

VC ¼ VGS9  VGS4 ¼ VGS9  VGS8

rffiffiffiffiffiffiffi! rffiffiffiffiffiffiffi! rffiffiffiffiffiffiffi
8IO 2IO 2IO (1.106)
¼ VT þ  VT þ ¼
K K K

Replacing (1.106) in (1.105), it results:

rffiffiffiffiffiffiffiffi
KIO
IOUT ¼ ðV1  V2 Þ (1.107)
2

In this case, the equivalent transconductance can be controlled by the reference

current IO :
rffiffiffiffiffiffiffiffi
KIO
Gm ¼ (1.108)
2

A differential difference amplifier (DDA) can be designed using two previous

presented differential amplifiers, the block diagram of the DDA being shown in
Fig. 1.25. These circuits present a multitude of applications such as amplifying or
comparing of differential input voltages and designing complex active filters.
The output current of the DDA can be expressed as follows:

IOUT ¼ ðIOUT1I þ IOUT2II Þ  ðIOUT2I þ IOUT1II Þ

¼ ðIOUT1I  IOUT2I Þ  ðIOUT1II  IOUT2II Þ ð1:109Þ
28 1 Differential Structures

CM
IOUT

IOUT1-I IOUT2-I IOUT1-II IOUT2-II

V1 DA I V2 V3 DA II V4

Fig. 1.25 The block diagram of a DDA circuit

VDD
IOUT

IOUT1-I IOUT2-II
IOUT2-I IOUT1-II

V1 I2-I IO 4IO IO I6-I V2 V3 I2-II IO 4IO IO I6-II V4

IO +I2-I IO + I6-I IO +I2-II IO + I6-II

Fig. 1.26 DDA circuit

Considering that DA I and DA II differential amplifiers from Fig. 1.25 are

identical, the expression of the output current becomes:

IOUT ¼ Gm ½ðV1  V2 Þ  ðV3  V4 Þ (1.110)

with Gm expressed by (1.108). The complete implementation of the DDA structure

is presented in Fig. 1.26.
The differential amplifier shown in Fig. 1.27 [10] presents a linear transfer
characteristic, obtained using the same mathematical principle, its equivalent
transconductance being controlled by a reference voltage.
The expression of I3 current is:

K K
I3 ¼ ðVGS5  VT Þ2 ¼ ðVSG3  VT Þ2 (1.111)
2 2

Because M1 and M3 are identical and they are biased at the same drain current,
their source-gate voltages will be equal, so:

K K
I3 ¼ ðVSG1  VT Þ2 ¼ ðVDD  V2  VT Þ (1.112)
2 2
1.2 Analysis and Design of Differential Structures 29

VDD

M10 M9
V2 V1
M1 M6 M7 M2

IOUT
I3 I2 I1 I4
M5 M8
M13 M14

M3 M4
VC

M11 M12

Fig. 1.27 Differential structure (3) based on PR 1.2

Similarly:

K
I4 ¼ ðVDD  V1  VT Þ (1.113)
2

The I1 current can be expressed as follows:

K K
I1 ¼ ðVGS14  VT Þ2 ¼ ðVSG4 þ VC  VT Þ2
2 2
K
¼ ðVDD  V1 þ VC  VT Þ2 ð1:114Þ
2

and, similarly:

K
I2 ¼ ðVDD  V2 þ VC  VT Þ2 (1.115)
2

The expression of the differential output current is:

IOUT ¼ ðI1 þ I3 Þ  ðI2 þ I4 Þ (1.116)

30 1 Differential Structures

VDD
M5 M6
VA’ VB’
V1 VA VB V1
M1 Ma M2 M3 Mb M4
V2
IO IO

ID1 + ID3 ID2 + ID4

Fig. 1.28 Differential structure (4) based on PR 1.2 – circuit’s core

resulting:

K
IOUT ¼ ðV2  V1 Þð2VDD  V1  V2 þ 2VC  2VT Þ
2
K
 ðV2  V1 Þð2VDD  V1  V2  2VT Þ ¼ KVC ðV2  V1 Þ ð1:117Þ
2

The advantage of this linear differential amplifier is the independence of its

equivalent transconductance on the threshold voltage, the result being an important
increasing of the circuit accuracy.
The linearization technique for the differential amplifier presented in Fig. 1.28
[11, 12] exploits the second mathematical principle (PR 1.2). Its output current is
made to be linearly dependent on the drain currents of M1–M4 transistors using
a current mirror (not shown in Fig. 1.28), IOUT ¼ ðID1 þ ID3 Þ  ðID2 þ ID4 Þ:

K K
ðVA 0  V1  VT Þ þ ðVB 0  V2  VT Þ
2 2
IOUT ¼
2 2
K K
 ðVA  V2  VT Þ  ðVB 0  V1  VT Þ
0 2 2
ð1:118Þ
2 2

resulting:

K
IOUT ¼ ðV2  V1 Þð2VA 0  V1  V2  2VT Þ
2
K
þ ðV1  V2 Þð2VB 0  V1  V2  2VT Þ ð1:119Þ
2

and:

IOUT ¼ K ðVB 0  VA 0 ÞðV1  V2 Þ (1.120)

1.2 Analysis and Design of Differential Structures 31

VDD

M12 M13

M11 M14
M5 M6
VA’ VB’
V1 VA VB V1
M1 Ma M2 M3 Mb M4
V2
IO IO IOUT

M9 M7 M17 M15

M10 M8 M18 M16

Fig. 1.29 Differential structure (4) based on PR 1.2 – complete implementation

Because:
rffiffiffiffiffiffiffi
0 2IO
VA ¼ VA þ VSGa ¼ VA þ VT þ (1.121)
K

and:
rffiffiffiffiffiffiffi
0 2IO
VB ¼ VB þ VSGb ¼ VB þ VT þ (1.122)
K

it results:

IOUT ¼ K ðVB  VA Þ ðV1  V2 Þ (1.123)

The equivalent transconductance of the entire structure presented in Fig. 1.28

can be expressed as follows:

IOUT
Gm ¼ ¼ K ð VB  V A Þ (1.124)
V1  V 2

The complete implementation of previous differential amplifier (Fig. 1.29) [11]

contains two cascode current mirrors, M7–M10 and M15–M18, in order to increase
the circuit accuracy.
The efficiency of the second mathematical principle can be illustrated by the
differential amplifier presented in Fig. 1.30 [13], having a very simple implemen-
tation comparing with the previous circuits. The VC1 and VC2 voltages represent
32 1 Differential Structures

Fig. 1.30 Differential VDD

structure (5) based on PR 1.2
M7 M8

IOUT

M3 M5 M4 M6
V1 V1
VP1 VP2

IO1 V2 IO2
M1 M2
VC1 VC2

constant external potentials that impose the drain currents of M1 and M2 transistors
to be equal with IO1 and IO2 , respectively. The VP2  VP1 voltage is considered to be
imposed by an external circuit.
The differential amplifier is composed from two parallel-connected differential
stages (M3–M5 and M4–M6), having different biasing currents (IO1 and IO2 ,
respectively). The output current of the entire structure can be expressed as
follows:

IOUT ¼ ID3 þ ID4  ID5  ID6 (1.125)

equivalent with:

K K
IOUT ¼ ðV1  VP1  VT Þ2 þ ðV2  VP2  VT Þ2
2 2
K K
 ðV2  VP1  VT Þ  ðV1  VP2  VT Þ2
2
ð1:126Þ
2 2

or:

IOUT ¼ K ðV1  V2 Þ ðVP2  VP1 Þ (1.127)

As VP1 and VP2 potentials are fixed, the behavior of the circuit shown in Fig. 1.30
is linear, having an equivalent transconductance expressed as:

Gm ¼ K ðVP2  VP1 Þ (1.128)

A method for obtaining a linear differential amplifier is presented in Fig. 1.31.

1.2 Analysis and Design of Differential Structures 33

VDD VDD

I1 I4

V1 M1 M5 M6 M2
V2
I2 I3

M7 M8

M3 M4

VC

Fig. 1.31 Differential structure (6) based on PR 1.2

Because M5 and M3 transistors are biased at the same drain current,

VGS5 ¼ VGS3 ¼ VC , for the left part of the circuit, the differential output current
will have the following expression:

K K K
I1  I 2 ¼ ðV1  VT Þ2  ðV1  VC  VT Þ2 ¼ VC ð2V1  VC  2VT Þ (1.129)
2 2 2

Similarly, for the right part of the circuit, it results:

K
I4  I3 ¼ VC ð2V2  VC  2VT Þ (1.130)
2

Using a current mirror (not shown in Fig. 1.31), the differential output current of
the differential amplifier presented in Fig. 1.31 is designed to be:

IOUT ¼ ðI1  I2 Þ  ðI4  I3 Þ ¼ KVC ðV1  V2 Þ (1.131)

The equivalent transconductance of the structure is independent on the threshold

voltage, with the result of reducing the circuit errors.
Another implementation of a linear differential amplifier based on the same
mathematical principle is presented in Fig. 1.32 [14].
The expressions of IOUT1 and IOUT2 currents are:

K K
IOUT1 ¼ ðVL  VT Þ2 þ ðVR  VB  VT Þ2 (1.132)
2 2
34 1 Differential Structures

Fig. 1.32 Differential

structure (7) based on PR 1.2 IOUT1 IOUT2

V1

VL VR
VB VB

V2
IO

and:

K K
IOUT2 ¼ ðVR  VT Þ2 þ ðVL  VB  VT Þ2 (1.133)
2 2

Implementing an output current IOUT as the difference between IOUT1 and IOUT2 ,
it results:

K
IOUT ¼ IOUT1  IOUT2 ¼ ðVL  VR ÞðVL þ VR  2VT Þ
2 (1.134)
K
þ ðVR  VL ÞðVL þ VR  2VB  2VT Þ
2

So:

IOUT ¼ KVB ðVL  VR Þ ¼ KVB ðV1  V2 Þ (1.135)

The equivalent transconductance of the circuit can be controlled by the biasing

voltage VB .

1.2.3 Differential Structures Based on the Third

Mathematical Principle (PR 1.3)

The circuit shown in Fig. 1.33 [15] represents a differential amplifier having the
transfer characteristic linearized using the third mathematical principle (PR 1.3). The
advantage of the following circuits is represented by the possibility of implementing
also the squaring function, by considering the sum of their output currents.
1.2 Analysis and Design of Differential Structures 35

2IO

V2 V1
M3 M4

ID3 ID4
IOUT1 VDD IOUT2

IC
M1 M5 M6 M7 M8 M2
VC

M9
2IO 2IO

Fig. 1.33 Differential structure (1) based on PR 1.3

The current sources and the circuit’s connections impose the following relation
between the currents:

ID3 þ ID6 ¼ ID4 þ ID7 ¼ ID3 þ ID4 ¼ 2IO (1.136)

resulting ID6 ¼ ID4 and ID7 ¼ ID3 . The translinear loops containing M1, M5, M6
and M2, M7, M8 transistors have the following characteristic equations:

VGS1  VC ¼ VGS5  VGS6 (1.137)

and:

VGS2  VC ¼ VGS8  VGS7 (1.138)

resulting:
rffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffi
2IOUT1 2 pffiffiffiffiffiffi pffiffiffiffiffiffi
VT þ  VC ¼ ID3  ID4 (1.139)
K K

and:
rffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffi
2IOUT2 2 pffiffiffiffiffiffi pffiffiffiffiffiffi
VT þ  VC ¼ ID4  ID3 (1.140)
K K
36 1 Differential Structures

The IOUT1 and IOUT2 output currents can be expressed as follows:

"rffiffiffiffi #2
K 2 pffiffiffiffiffiffi pffiffiffiffiffiffi
IOUT1 ¼ ID3  ID4 þ ðVC  VT Þ (1.141)
2 K

and:
"rffiffiffiffi #2
K 2 pffiffiffiffiffiffi pffiffiffiffiffiffi
IOUT2 ¼ ID4  ID3 þ ðVC  VT Þ (1.142)
2 K

or:

pffiffiffiffiffiffi pffiffiffiffiffiffi 2 pffiffiffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffi K

IOUT1 ¼ ID3  ID4 þ 2K ID3  ID4 ðVC  VT Þ þ ðVC  VT Þ2
2
(1.143)

and:

pffiffiffiffiffiffi pffiffiffiffiffiffi 2 pffiffiffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffi K

IOUT2 ¼ ID4  ID3 þ 2K ID4  ID3 ðVC  VT Þ þ ðVC  VT Þ2
2
(1.144)

The circuit’s differential input voltage is equal with the difference between two
source-gate voltages:
rffiffiffiffi
2 pffiffiffiffiffiffi pffiffiffiffiffiffi
V1  V2 ¼ VSG3  VSG4 ¼ ID3  ID4 (1.145)
K

From (1.143), (1.144) and (1.145), the expressions of the output currents become:

K K
IOUT1 ¼ ðV1  V2 Þ2 þ K ðV1  V2 ÞðVC  VT Þ þ ðVC  VT Þ2 (1.146)
2 2

and:

K K
IOUT2 ¼ ðV1  V2 Þ2  K ðV1  V2 ÞðVC  VT Þ þ ðVC  VT Þ2 (1.147)
2 2

As VC voltage is equal with the gate-source of M9 transistor, that is biased at

the IC constant current, the previous relations become:

K pffiffiffiffiffiffiffiffiffiffi
IOUT1 ¼ ðV1  V2 Þ2 þ 2KIC ðV1  V2 Þ þ IC (1.148)
2
1.2 Analysis and Design of Differential Structures 37

IOUT1 IO IO IOUT2

2IO
V1 M5 M6 M7 M8 V2

I1 + IO I2 + IO

IO IO

M1 M2 M3 M4
V
2IO 2IO

Fig. 1.34 Differential structure (2) based on PR 1.3

and:

K pffiffiffiffiffiffiffiffiffiffi
IOUT2 ¼ ðV1  V2 Þ2  2KIC ðV1  V2 Þ þ IC (1.149)
2

The differential output current will have the following expression:

pffiffiffiffiffiffiffiffiffiffi
IOUT1  IOUT2 ¼ 8KIC ðV1  V2 Þ (1.150)

so, the circuit implements a linear dependence of the differential output current on
the differential input voltage, the equivalent transconductance being:
pffiffiffiffiffiffiffiffiffiffi
Gm ¼ 8KIC (1.151)

A realization of a linear differential amplifier using the computation of the

arithmetical mean for input potentials is presented in Fig. 1.34.
As M1–M4 transistors implement an arithmetical mean circuit, the expression
of V potential will be:

V1 þ V2
V¼ (1.152)
2
38 1 Differential Structures

IOUT1 IO IO IOUT2

V1 M1 M2 M3 M4 V2

Fig. 1.35 Differential structure (3) based on PR 1.3

For M5–M6 differential amplifier, the differential input voltage can be expressed
as follows:
rffiffiffiffi
2 pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffi
V1  V ¼ VGS5  VGS6 ¼ IOUT1  IO (1.153)
K

Replacing (1.152) in (1.153), it results:

rffiffiffiffiffiffiffiffi
KIO K
IOUT1 ¼ IO þ ðV1  V2 Þ þ ðV1  V2 Þ2 (1.154)
2 8

Similarly, for M7–M8 differential amplifier, it can be obtained:

rffiffiffiffiffiffiffiffi
KIO K
IOUT2 ¼ IO  ðV1  V2 Þ þ ðV1  V2 Þ2 (1.155)
2 8

The output current of the differential amplifier circuit shown in Fig. 1.34 will be:
pffiffiffiffiffiffiffiffiffiffi
IOUT ¼ IOUT1  IOUT2 ¼ 2KIO ðV1  V2 Þ (1.156)

A differential amplifier with linear transfer characteristic can be implemented

using two classical differential amplifiers (Fig. 1.35) [16].
For M1–M2 differential amplifier, the differential input voltage can be expressed
as follows:
rffiffiffiffi
2 pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffi
V1  V2 ¼ IOUT1  IO (1.157)
K
1.2 Analysis and Design of Differential Structures 39

VDD

IOUT1 IO IOUT2

VC + VIN M1 VC M3 M2 VC - VIN

IO

- VDD

Fig. 1.36 Differential structure (4) based on PR 1.3

resulting:

pffiffiffiffiffiffiffiffiffiffi K
IOUT1 ¼ IO þ 2KIO ðV1  V2 Þ þ ðV1  V2 Þ2 (1.158)
2

Similarly, for M3–M4 differential amplifier, the expression of I2 current will be:

pffiffiffiffiffiffiffiffiffiffi K
IOUT2 ¼ IO  2KIO ðV1  V2 Þ þ ðV1  V2 Þ2 (1.159)
2

The output current of the differential amplifier will be linearly dependent on the
differential input voltage:
pffiffiffiffiffiffiffiffiffiffi
IOUT ¼ IOUT1  IOUT2 ¼ 8KIO ðV1  V2 Þ (1.160)

The circuit presented in Fig. 1.36 [17] is used for linearizing the transfer
characteristic of a classical differential amplifier.
The difference between gate-source voltages of M1 and M3 transistors can be
expressed as follows:

VGS1  VGS3 ¼ ðVC þ VIN Þ  VC (1.161)

For a biasing in saturation of all MOS transistors from Fig. 1.36, it results:
rffiffiffiffi
2 pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffi
VIN ¼ IOUT1  IO (1.162)
K
40 1 Differential Structures

IOUT1 IOUT2

M1 M2
V1 IO IO V2

IOUT1 VO VO IOUT2
- + + -

IO IO
IO IO

Fig. 1.37 Differential structure (5) based on PR 1.3 – principle of operation

So, the expression of I1 current will be:

K 2 pffiffiffiffiffiffiffiffiffiffi
IOUT1 ¼ IO þ VIN þ 2KIO VIN (1.163)
2

Similarly, computing the difference between the gate-source voltages of M2–M3

transistors, it results:

K 2 pffiffiffiffiffiffiffiffiffiffi
IOUT2 ¼ IO þ VIN  2KIO VIN (1.164)
2

The differential output current for the circuit presented in Fig. 1.36 will be:
pffiffiffiffiffiffiffiffiffiffi
IOUT ¼ IOUT1  IOUT2 ¼ 8KIO VIN (1.165)

The following presented principle for linearizing the transfer characteristic of

a differential structure is based on the constant sum of gate-source voltages, the
circuit’s core being represented by a particular implementation of a differential
amplifier (Fig. 1.37) [18] that provides a linear behavior of the circuit.
For a biasing in saturation of MOS transistors from Fig. 1.37, the V1  V2
differential input voltage can be expressed as follows:

V1  V2 ¼ VGS1  VO (1.166)

and:

V1  V2 ¼ VO  VGS2 (1.167)

resulting the expressions of the sum and difference between gate-source voltages:

VGS1 þ VGS2 ¼ 2VO (1.168)

1.2 Analysis and Design of Differential Structures 41

and:

VGS1  VGS2 ¼ 2ðV1  V2 Þ (1.169)

The differential output current IOUT is:

K K
IOUT ¼ IOUT1  IOUT2 ¼ ðVGS1  VT Þ2  ðVGS2  VT Þ2 (1.170)
2 2

equivalent with:

K
IOUT ¼ ðVGS1  VGS2 ÞðVGS1 þ VGS2  2VT Þ (1.171)
2

Replacing (1.168) and (1.169) in (1.171), it results a linear transfer characteristic

of the differential amplifier presented in Fig. 1.37:

IOUT ¼ 2K ðVO  VT ÞðV1  V2 Þ (1.172)

Usually, the VO voltage sources are implemented as current-controlled voltage

sources. The simplest way to realize these sources, having the advantages of
simplicity, also of minimizing the errors introduced by the bulk effect is to use
the gate-source voltage of a MOS transistor in saturation, biased at a constant
current, IO :
rffiffiffiffiffiffiffi
2IO
VO ¼ VGSO ¼ VT þ (1.173)
K

Replacing these particular expressions of VO voltage sources in the general

expression (1.172) of the output current of the differential amplifier, it can be
obtained:
pffiffiffiffiffiffiffiffiffiffi
IOUT ¼ 8KIO ðV1  V2 Þ (1.174)
pffiffiffiffiffiffiffiffiffiffi
so, an equivalent transconductance of the differential amplifier Gm ¼ 8KIO that
can be very easily controlled by the biasing current, IO .
A similar linearization technique is used for the circuit shown in Fig. 1.38 [19].
The VO voltage sources from Fig. 1.37 are implemented in Fig. 1.38 using the
gate-source voltages of M3 and M4 transistors, biased at constant current, IO .
Considering a biasing in saturation of MOS transistors, the output differential
current IOUT can be expressed using (1.172) and (1.174):
pffiffiffiffiffiffiffiffiffiffi
IOUT ¼ 2K ðV1  V2 ÞðVO  VT Þ ¼ 8KIO ðV1  V2 Þ (1.175)
42 1 Differential Structures

VDD

IO IO
IOUT

IOUT1 IOUT2

M1 M2

V1 M3
M4 V2

Fig. 1.38 Differential structure (5) based on PR 1.3 – first implementation

The equivalent transconductance of the structure is:

IOUT pffiffiffiffiffiffiffiffiffiffi
Gm ¼ ¼ 8KIO (1.176)
V1  V2

In Fig. 1.39 [19], the VO voltage sources from Fig. 1.37 are realized as current-
controlled voltage sources, the gate-source voltages of M3 and M5 transistors being
dependent on the IO biasing current. Similarly with the previous circuits, the IOUT
output differential current can be expressed as:
pffiffiffiffiffiffiffiffiffiffi
IOUT ¼ IOUT1  IOUT2 ¼ 2K ðV1  V2 ÞðVO  VT Þ ¼ 8KIO ðV1  V2 Þ (1.177)

The equivalent transconductance of the structure is:

IOUT pffiffiffiffiffiffiffiffiffiffi
Gm ¼ ¼ 8KIO (1.178)
V1  V2

A differential amplifier with linear transfer characteristic based on the same

mathematical principle can be designed (Fig. 1.40) [20] using two translinear loops
implemented using M1, M3, M8, M7 and M5, M6, M4, M2 transistors, respectively.
Using the notation VGS ðIÞ for the absolute value of the gate-source voltage of
a MOS transistor biased at a drain current equal with I, it is possible to write:
rffiffiffiffi
2 pffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffi
V1  V2 ¼ 2VGS ðIO Þ  2VGS ðIOUT1 Þ ¼ 2 IO  IOUT1 (1.179)
K
1.2 Analysis and Design of Differential Structures 43

VDD

M7 M8
IO IO
IOUT1 IO IOUT2

V1 M1 M3 M5 M2
V2
VO VO
I O + I1 IO + I2

M4 M6

-VDD

Fig. 1.39 Differential structure (5) based on PR 1.3 – second implementation

VDD

IO IO

M3 M8 M6 M4

V1 V2
M1 M5 M7 M2

IOUT1 IOUT2

Fig. 1.40 Differential structure (5) based on PR 1.3 – third implementation

and:
rffiffiffiffi
2 pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffi
V1  V2 ¼ 2VGS ðIOUT2 Þ  2VGS ðIO Þ ¼ 2 IOUT2  IO (1.180)
K

It results:
rffiffiffiffi
pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffi V1  V2 K
IOUT1 ¼ IO  (1.181)
2 2
44 1 Differential Structures

VDD

IOUT1 IOUT2

V1 M1 M3 M4 M2 V2

I
I’
VC
M5 M6

Fig. 1.41 Differential structure (5) based on PR 1.3 – third implementation (improved version)

and:
rffiffiffiffi
pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffi V1  V2 K
IOUT2 ¼ IO þ (1.182)
2 2

So:
pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffi
IOUT1 þ IOUT2 ¼ 2 IO (1.183)

and:
rffiffiffiffi
pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffi K
IOUT2  IOUT1 ¼ ðV1  V2 Þ (1.184)
2

The differential output current will have the following expression:

pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffi
IOUT2  IOUT1 ¼ IOUT2  IOUT1 IOUT2 þ IOUT1
pffiffiffiffiffiffiffiffiffiffi
¼ 2KIO ðV1  V2 Þ ¼ Gm ðV1  V2 Þ ð1:185Þ

The equivalent transconductance of the differential amplifier is:

pffiffiffiffiffiffiffiffiffiffi
Gm ¼ 2KIO (1.186)

The principle of operation of the differential amplifier presented in Fig. 1.41 [21] is
similar with the general principle described for the previous circuit. The VO voltage
1.2 Analysis and Design of Differential Structures 45

VDD

IOUT1 IOUT2

M1 M3’ M4’ M2
V1 4K 4K V2
M3’ M4’’
4K 4K
I
I’
VC
M5 M6

Fig. 1.42 Differential structure (5) based on PR 1.3 – fourth implementation

sources from Fig. 1.37 are implemented in Fig. 1.41 using the gate-source voltages
of M3 and M4 transistors. Because, from the current equations, I ¼ I 0 ¼ 0, the
M3–M6 transistors will be biased at the same drain currents, imposed by the VC
potential. Since they are identical, their gate-source voltages will be equal, so
VO ¼ VGS3 ¼ VGS4 ¼ VC . Using the general relation (1.172), the differential output
current can be expressed as follows:

IOUT ¼ IOUT1  IOUT2 ¼ 2K ðVC  VT Þ ðV1  V2 Þ (1.187)

the equivalent transconductance being:

Gm ¼ 2K ðVC  VT Þ (1.188)

In order to avoid the dependence of the equivalent transconductance on thresh-

old voltage, the M3 and M4 transistors from Fig. 1.41 have been replaced in Fig. 1.42
[21] with two series-connected MOS transistors, M3’–M3” and M4’–M4”. The
voltage sources VO will have the following expression:
rffiffiffiffiffiffiffiffiffi! rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
0 00 2ID5 2 K
VO ¼ VGS3 þ VGS3 ¼ 2 VT þ ¼ 2VT þ ðVC  VT Þ2 ¼ VC þ VT
4K K 2
(1.189)

Replacing (1.189) in (1.172), it results:

IOUT ¼ 2KVC ðV1  V2 Þ (1.190)

46 1 Differential Structures

VDD

M6a M7a M7b M6b

M5a 2K M5b
K 2K K

IOUT1 IOUT1 IOUT2 IOUT2

M1a M2a M3a M3b M2b M1b

V1 V2

IO1 IO2
A I B
I’
IOUT1 2IOUT1 2IOUT1 IO IO 2IOUT2 2IOUT2 IOUT2
M10a M9a M8a V M11a M11b M9b M10b
C
M8b

Fig. 1.43 Differential structure (5) based on PR 1.3 – fourth implementation (improved version)

So, the equivalent transconductance, Gm ¼ 2KVC will be not dependent on the

threshold voltage and VC voltage can control it.
Another realization of a differential amplifier with linear behavior based on
the third mathematical principle is presented in Fig. 1.43 [22]. The M1 and
M2 transistors from Fig. 1.37 have been replaced in Fig. 1.43 by two series-
connected transistors, M1a–M2a and M1b–M2b, while the voltage sources VO
from Fig. 1.37 have been practically implemented in Fig. 1.43 by the gate-source
voltages of M3a and M3b transistors. The current equations impose I ¼ I 0 ¼ 0,
so IO1 ¼ IO2 ¼ IO . Because M3a, M3b, M11a and M11b transistors are identical
and biased at the same current, their gate-source voltages will be identical,
so VO ¼ VGS3a ¼ VGS3b ¼ VC . Using (1.172), it can be obtained:

IOUT ¼ IOUT1  IOUT2 ¼ 2K ðVC  VT Þ ðV1  V2 Þ (1.191)

The equivalent transconductance is:

Gm ¼ 2K ðVC  VT Þ (1.192)

The replacing of M3a and M3b transistors with two series-connected MOS
transistors, M3a’–M3a” and M3b’–M3b” (Fig. 1.44) [21, 22], allows to remove
the dependence of the circuit equivalent transconductance on the threshold voltage:

Gm ¼ 2KVC (1.193)

The advantage of the circuits presented in Figs. 1.43 and 1.44 with respect to
the circuits shown in Figs. 1.41 and 1.42 consists in the availability of the output
currents IOUT1 and IOUT2 as external currents, being possible to process them
1.2 Analysis and Design of Differential Structures 47

VDD

IOUT1 IOUT1 IOUT2 IOUT2

M3a’ M3b’
V1 4K 4K V2

I M3a’’ M3b”
A 4K B
4K I’
IOUT1 2IOUT1 2IOUT1
IO IO 2IOUT2 2I IOUT2
OUT2

VC

Fig. 1.44 Differential structure (6) based on PR 1.3

V DD

M9 M10
M3 M5

IOUT
V1 M4 M6 V2
M1 M2

IOUT1 IOUT2
IO IO
M8 M7 M11 M12

Fig. 1.45 Differential structure (7) based on PR 1.3

in order to implement other classes of circuits (active resistors, multipliers or

multifunctional structures).
A differential amplifier with linear behavior obtained using the same mathe-
matical principle is presented in Fig. 1.45, the NMOS transistors being replaced
by complementary PMOS active devices. The VO voltage sources from Fig. 1.37 are
practically implemented in Fig. 1.45 [23] using the source-gate voltages of M4 and
M6 transistors, biased at constant current IO .
rffiffiffiffiffiffiffi
2IO
VO ¼ VSG4 ¼ VSG6 ¼ VT þ (1.194)
K
48 1 Differential Structures

VDD

M9 M7 M8 M10 M23 M25

VO VO
M17 M18
V1 V2 IOUT
M11 M12
M13 M14

M20 M21
VC
M33 M34
M15 M16 M22 M24

Fig. 1.46 Differential structure (8) based on PR 1.3 – complete implementation

Fig. 1.47 Differential

structure (8) based on PR 1.3 IO + IOUT2 IO + IOUT1
– principle of operation
+ - - +
IO IO
VO VO

V1 V2
M13 M14
IO IO

IOUT1 IOUT2

IOUT
CM

Using the general relation (1.172), the differential output current can be
expressed as follows:
pffiffiffiffiffiffiffiffiffiffi
IOUT2  IOUT1 ¼ 2K ðVO  VT ÞðV1  V2 Þ ¼ 2 2KIO ðV1  V2 Þ (1.195)

resulting an equivalent transconductance of the entire structure, given by:

pffiffiffiffiffiffiffiffiffiffi
Gm ¼ 2 2KIO (1.196)

A similar method based on the constant sum of gate-source voltages is used in

Fig. 1.46 [23].
The principle diagram, equivalent with the previous circuit is presented in Fig. 1.47.
1.2 Analysis and Design of Differential Structures 49

The core of the differential amplifier is represented by the M13 and M14
transistors, while the VO current-controlled voltage sources are implemented
using M11 and M12 transistors, biased at a current imposed by M15 and M16
transistors (having the gate-source voltages determined by the VC control voltage).
The current mirror from Fig. 1.47 is implemented in Fig. 1.46 using M34–M22,
M33–M24 and M23–M25 pairs, with the goal of realizing the difference of the
drain currents of M13 and M14 transistors. For the circuit presented in Fig. 1.47, the
differential input voltage can be expressed as follows:

V1  V2 ¼ VSG14  VO (1.197)

and:

V1  V2 ¼ VO  VSG13 (1.198)

resulting:

VSG14  VSG13 ¼ 2ðV1  V2 Þ (1.199)

and:

VSG14 þ VSG13 ¼ 2VO (1.200)

The differential output current for the circuit presented in Fig. 1.47 will be:

K K
IOUT2  IOUT1 ¼ ðVSG14  VT Þ2  ðVSG13  VT Þ2
2 2
K
¼ ðVSG14  VSG13 ÞðVSG13 þ VSG14  2VT Þ ð1:201Þ
2

Replacing (1.199) and (1.200) in (1.201), it results:

IOUT2  IOUT1 ¼ 2K ðV1  V2 ÞðVO  VT Þ (1.202)

For the complete circuit presented in Fig. 1.46, the VO voltage sources will have
the following relations:

VO ¼ VSG11 ¼ VSG12 ¼ VGS15 ¼ VGS16 ¼ VC (1.203)

Because M11, M12, M15 and M16 transistors are identical and they work at the
same drain current, it results:

IOUT2  IOUT1 ¼ 2K ðV1  V2 Þ ðVC  VT Þ (1.204)

50 1 Differential Structures

M11’ M12’

M11 M12

M11’’ M12’’

Fig. 1.48 Improving method for the differential structure (8) based on PR 1.3

so, an equivalent transconductance of the circuit expressed by:

Gm ¼ 2K ðVC  VT Þ (1.205)

The disadvantage of the circuit is represented by the dependence of its equiva-

lent transconductance on the threshold voltage, concretized in the existance of
errors introduced by the bulk effect. In order to avoid this aspect, M11 and M12
transistors from Fig. 1.46 must be replaced (Fig. 1.48) with two series connections
of two transistors, M11’–M11’ and M12’–M12”, respectively, each of them having
K 0 ¼ K 00 ¼ 4K.
For this new configuration, the expression of VO becomes:

VO ¼ VSG11 0 þ VSG11 00 ¼ 2VSG11 0 (1.206)

rffiffiffiffiffiffiffiffiffiffiffiffi! rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2ID11 0 2 K
VO ¼ 2 VT þ ¼ 2VT þ ðVC  VT Þ2 (1.207)
4K K 2

resulting:

VO ¼ V C þ VT (1.208)

In this case, the circuit equivalent transconductance becomes independent on the

threshold voltage:

Gm ¼ 2KVC (1.209)

A differential amplifier with linear behavior, having a similar principle of

operation is presented in Fig. 1.49 (M5, M6, M12 and M13 transistors have the
parameter K fourth time greater than the other circuit’s transistors). The M1 and M2
transistors form the differential input stage, excited by the differential input voltage
V1  V2 , while M1 and M2 transistors, together with the current mirrors M17–M18
and M19–M20, mirror the output currents from the differential amplifier (IOUT1 and
IOUT2 ) for obtaining the differential output current IOUT . The VO voltage sources
1.2 Analysis and Design of Differential Structures 51

VDD
M19 M20

IOUT1
M18 M17
IOUT2 IOUT
M8 M9 M14
IOUT IOUT1
IOUT2

V1 M1 M2 V2
M3 M16 M4
M11
M5 M12

M6 M13

M7 M10
VC1 M15
VC2
-VDD

Fig. 1.49 Differential structure (9) based on PR 1.3

from Fig. 1.37 are implemented in Fig. 1.49 using M5–M6 and M12–M13 pairs,
biased at a constant current. This current is imposed using M8–M9–M14 current
mirror by M7 transistor, having the gate-source voltage determined by VC1 control
potential.
The voltage VO can be expressed as follows:
rffiffiffiffiffiffiffiffiffi!
2ID5
VO ¼ VGS5 þ VGS6 ¼ 2 VT þ
4K
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 K
¼ 2VT þ ðVC1  VT Þ2 ¼ VC1 þ VT ð1:210Þ
K 2

So, using relation (1.172), it results:

Gm ¼ 2KVC1 : (1.211)

The advantage of the circuit consists in the possibility of controlling Gm tran-

sconductance by VC1 potential, as well as the independence of the equivalent
transconductance on the bulk effect.
A differential amplifier with linear behavior based on a translinear loop is
presented in Fig. 1.50 [24].
The translinear loop containing M2, M3, M4 and M7 transistors has the follow-
ing characteristic equation:
rffiffiffiffi
2 pffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffi
V1  V2 ¼ 2VGS ðIO Þ  2VGS ðIOUT1 Þ ¼ 2 IO  IOUT1 (1.212)
K
52 1 Differential Structures

VDD

V1 M7 M1 M2 M8 V2

M3 M6

M4 M5

IO I1 I2 IO

Fig. 1.50 Differential structure (10) based on PR 1.3

resulting:
rffiffiffiffiffiffiffiffi
K KIO
IOUT1 ¼ IO þ ðV1  V2 Þ2  ðV1  V 2 Þ (1.213)
8 2

Similarly, analyzing the translinear loop containing M1, M5, M6 and M8

transistors, it results:
rffiffiffiffiffiffiffiffi
K KIO
IOUT2 ¼ IO þ ðV1  V2 Þ2 þ ðV1  V 2 Þ (1.214)
8 2

The differential output current of the circuit presented in Fig. 1.50 will have the
following expression:
pffiffiffiffiffiffiffiffiffiffi
IOUT2  IOUT1 ¼ 2KIO ðV1  V2 Þ (1.215)

A linearization technique [25] using the third mathematical principle (PR 1.3),
based on the utilization of translation blocks for realizing DC shifting of input
potentials has the block diagram presented in Fig. 1.51 [25].
The “DA” block represents a classical active-load differential amplifier, having
the common-sources point biased at a potential V fixed by the circuit “M”. This
circuit computes the arithmetical mean of input potentials, providing a very good
linearity of the entire structure, with the contribution of “T” blocks (which are used
for introducing a translation of input potentials).
1.2 Analysis and Design of Differential Structures 53

V1 M V2

IO IO
T T
V
V1T V2T
DA

IOUT

Fig. 1.51 Differential structure (11) based on PR 1.3 – block diagram

Fig. 1.52 Differential V

structure (11) based on PR 1.3
– DA block implementation

V1T V2T
M1 M2
IOUT1 IOUT2 IOUT

M3 M4

1.2.3.1 The “DA” (Differential Amplifier) Block

The “DA” block is implemented as a classical active-load differential amplifier,

having the concrete realization presented in Fig. 1.52 [25–27].
Considering a biasing in saturation of all MOS devices from Fig. 1.52, the output
current of the differential amplifier can be expressed as:

K
IOUT ¼ ðV1T  V2T Þ ð2V  V1T  V2T  2VT Þ (1.216)
2

In order to obtain a linear transfer characteristic IOUT ðV1T  V2T Þ, it is necessary

that the second parenthesis from (1.216) to be constant with respect to the differential
input voltage, V1T  V2T :

2V  V1T  V2T  2VT ¼ A ¼ ct: (1.217)

54 1 Differential Structures

Fig. 1.53 Differential

structure (11) based on PR
1.3 – T block implementation IO IO

M9 M9’
V1 V2

V1T V2T

resulting the necessity of implementing a V voltage equal with:

V1T þ V2T A
V¼ þ VT þ (1.218)
2 2

1.2.3.2 The “T” (Translation) Block

The translation of the V potential with VT þ A=2 (relation (1.218)) can be obtained
using the “T” block, having the implementation presented in Fig. 1.53.
Because the same IO current is passing through transistors from Fig. 1.53, it is
possible to write that:
rffiffiffiffiffiffiffi
2IO
V1 ¼ V1T þ VT þ (1.219)
K

and:
rffiffiffiffiffiffiffi
2IO
V2 ¼ V2T þ VT þ (1.220)
K

So, both input potentials V1 and V2 are DC shifted with the same amount,
pffiffiffiffiffiffiffiffiffiffiffiffiffi
VT þ 2IO =K .

1.2.3.3 The “M” (Arithmetic Mean) Block

In order to obtain the arithmetic mean of input potentials expressed by (1.221)

relation, the circuit from Fig. 1.54 [25] can be used, having the advantages of using
only MOS transistors biased in saturation region and of avoiding any current
consumption from the input voltage sources, V1 and V2 .
1.2 Analysis and Design of Differential Structures 55

IO /2 IO /2

V1 V2
M14 M15 M15’ M14’

IO IO
V

Fig. 1.54 Differential structure (11) based on PR 1.3 – M block implementation

The M14–M15 and M14’–M15’ differential amplifiers are biased at the same
current, IO and, additionally, the sum of drain currents of M15 and M15’ transistors
are, also, equal with IO . As a result, gate-source voltages of M14 and M15’
transistors are equal and, similarly, gate-source voltages of M14’ and M15 transis-
tors are equal. In order to obtain the expression of V voltage, it can write that V1 
V ¼ VGS14  VGS15 and V  V2 ¼ VGS15 0  VGS14 0 . Subtracting these two relations
and using the previous observations, V potential will represent the arithmetical
mean of V1 and V2 input potentials:

V1 þ V2
V¼ (1.221)
2

So:
rffiffiffiffiffiffiffi
V1T þ V2T 2IO
V¼ þ VT þ (1.222)
2 K
pffiffiffiffiffiffiffiffiffiffiffiffiffi
Comparing (1.218) and (1.212) relations, it results that A ¼ 2 2IO =K , so:
rffiffiffiffiffiffiffi
K 2IO pffiffiffiffiffiffiffiffiffiffi
IOUT ¼ ðV1T  V2T Þ2 ¼ 2KIO ðV1T  V2T Þ (1.223)
2 K

equivalent (using (1.219) and (1.220)) with:

pffiffiffiffiffiffiffiffiffiffi
IOUT ¼ 2KIO ðV1  V2 Þ ¼ Gm ðV1  V2 Þ (1.224)
pffiffiffiffiffiffiffiffiffiffi
Gm ¼ 2KIO being the equivalent transconductance of the differential amplifier.
In conclusion, a linear transfer characteristic of the differential structure having
the block diagram presented in Fig. 1.51 is obtained by using a proper voltage
biasing of the classical differential amplifier from Fig. 1.52. The full implementa-
tion of the linearized differential structure is presented in Fig. 1.55. An equivalent
structure, obtained by replacing the “DA” block from Fig. 1.51 with a complemen-
tary circuit is presented in Fig. 1.56 [25].
56 1 Differential Structures

VDD

M11 M12 M12’ M11’

M10 M13 M13’ M10’

IO/2 “M” IO/2
“T”
M14 M15’
“T”
V1 M9 M15 M14’ M9’ V2
0
2IOUT1 IO 2IOUT2
IO
V
IOUT1 IOUT2
V1T V2T
M1 M2
IO M5 M5’ IO
IOUT1 IOUT2 IOUT
IO
M4 M3 M3’ M4’
M16 M6 M8 M2 M2’M8’ M6’

“DA”

Fig. 1.55 Differential structure (11) based on PR 1.3 – complete implementation

VDD

V2 K K V1
IOUT

V2T IOUT2 V1T

VC 4K IOUT2 IOUT1 4K VC
V IOUT1
IOUT2 2IOUT1
4K 4K

V1 V2
V

Fig. 1.56 Differential structure (11) based on PR 1.3 – alternate complete implementation
1.2 Analysis and Design of Differential Structures 57

Fig. 1.57 Differential

structure (12) based on PR 1.3 IOUT
– block diagram

V1 V2
DA

VC
T

V’

A similar behavior can be obtained based on the block diagram presented in

Fig. 1.57, using another structure for replacing the block diagram from Fig. 1.51.
The full implementation of the differential amplifier using this architecture is
shown in Fig. 1.58.
A differential amplifier with linear transfer characteristic using FGMOS
transistors is presented in Fig. 1.59 [28].
Considering that FGMOS transistors from Fig. 1.59 have different inputs, the
expressions of their drain currents will be:
 2
K V1 þ VPOL1
IOUT1 ¼  V  VT (1.225)
2 2
 2
K V2 þ VPOL2
IOUT2 ¼  V  VT (1.226)
2 2

and:
 2
K V1 þ V2 þ 2VPOL3
IO ¼  V  VT (1.227)
2 4

Replacing in (1.225) and (1.226) the expression of V potential, expressed from

(1.227), it results:

rffiffiffiffiffiffiffi!2
K V1  V2 þ 2VPOL1  2VPOL3 2IO
IOUT1 ¼ þ (1.228)
2 4 K
58 1 Differential Structures

VDD

IOUT

IOUT1IOUT2 IOUT2
V1 V2

IOUT1 IOUT2
V
IOUT1 2IOUT2

V’=(V1 + V2)/2 4K

V1 V2 4K

K
VC

Fig. 1.58 Differential structure (12) based on PR 1.3 – complete implementation

and:

rffiffiffiffiffiffiffi!2
K V2  V1 þ 2VPOL2  2VPOL3 2IO
IOUT2 ¼ þ (1.229)
2 4 K

The differential output current of the circuit presented in Fig. 1.59 will have the
following expression:
 
K V1  V2 VPOL1  VPOL2
IOUT1  IOUT2 ¼ þ
2 2 2
rffiffiffiffiffiffiffi!
VPOL1 þ VPOL2 2IO
  VPOL3 þ 2 ð1:230Þ
2 K

In order to obtain a linear differential amplifier, the structure must be symmetrical,

so VPOL1 ¼ VPOL2 , resulting:
rffiffiffiffiffiffiffi!
K 2IO
IOUT1  IOUT2 ¼ ðV1  V2 Þ VPOL1  VPOL3 þ 2 (1.231)
4 K
1.2 Analysis and Design of Differential Structures 59

VDD

IO

IOUT2 IOUT1
VPOL2 VPOL3
VPOL1
1 1 1
M2 1/2 M3 M1 1
V2 1 1/2 V1
V

Fig. 1.59 Differential structure (13) based on PR 1.3

VDD

VC
M3 M4

IOUT1 IOUT2

M5 M6

VB - V1/2 VB + V1/2
M1 M7 M8 M2

Fig. 1.60 Differential structure based on PR 1.4

1.2.4 Differential Structures Based on the Fourth Mathematical

Principle (PR 1.4)

A possible illustration of the utilization of fourth mathematical principle (PR 1.4)

for linearizing the transfer characteristic of a differential structure is presented in
Fig. 1.60 [29]. The symmetrical structure is responsible for an important improve-
ment of the circuit accuracy.
60 1 Differential Structures

Fig. 1.61 Differential

structure based on PR 1.4 – IOUT1 IOUT2
symbolic representation

VB - V1/2 DA VB + V1/2

VC

The expression of IOUT1 output current is:

K K
IOUT1 ¼ ðVGS5  VT Þ2 þ ðVGS8  VT Þ2 (1.232)
2 2

which is equivalent with:

K K
IOUT1 ¼ ðVC  VGS3  VT Þ2 þ ðVGS8  VT Þ2 (1.233)
2 2

Because M1 and M3 transistors are identical and they are biased at the same
drain current, their gate-source voltages will be equal, so:

K K
IOUT1 ¼ ðVC  VGS1  VT Þ2 þ ðVGS8  VT Þ2 (1.234)
2 2

or:
   
K V1 2 K V1 2
IOUT1 ¼ VC  VB þ V  VT þ þ VB  V  VT þ (1.235)
2 2 2 2

Similarly, the second output current, IOUT2 , will have the following expression:
   
K V1 2 K V1 2
IOUT2 ¼ VC  VB þ V  VT  þ VB  V  VT  (1.236)
2 2 2 2

The differential output current can be expressed as follows:

IOUT1  IOUT2 ¼ KV1 ðVC  VB þ V  VT Þ

þ KV1 ðVB  V  VT Þ ¼ K ðVC  2VT Þ V1 ð1:237Þ

The symbolic representation of the circuit is shown in Fig. 1.61.

1.2 Analysis and Design of Differential Structures 61

Fig. 1.62 Classical MOS

differential structure I1 I2

V1 V2

IO’

1.2.5 Differential Structures Based on the Fifth

Mathematical Principle (PR 1.5)

The method for obtaining a linear behavior of the differential amplifier using the
fifth mathematical principle (PR 1.5) is based on a proper biasing of the structure at
a current that is dependent on the differential input voltage.
The analysis of the classical differential amplifier (Fig. 1.62) using MOS
transistors biased in saturation region illustrates a strongly nonlinear behavior,
that can be quantitatively evaluated by the (1.14) dependence of IOUT differential
output current on the differential input voltage, VI ¼ V1  V2 .
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
KðV1  V2 Þ2 K 2 ðV1  V2 Þ4
IOUT ¼ I1  I2 ¼ IO 0  (1.238)
IO 0 4IO 02

equivalent with:
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
V1  V2
IOUT ¼ 4KIO 0  K 2 ðV1  V2 Þ2 (1.239)
2

IO 0 being the biasing current of the differential structure. So, superior-order

distortions will characterize the behavior of the classical differential structure,
imposing the design of a linearization technique for removing the superior-order
terms from its transfer characteristic.
The method [30] for obtaining a linear transfer characteristic of the differential
amplifier, despite the quadratic law of its composing devices (Fig. 1.63) [30], is to
obtain the IO 0 biasing current of the entire differential structure as a sum of a main
constant term, IO and an additional term, proportional with the square of the
differential input voltage, I ¼ KðV1  V2 Þ2 =4:

K
IO 0 ¼ IO þ I ¼ IO þ ðV1  V2 Þ2 (1.240)
4
62 1 Differential Structures

Fig. 1.63 Differential

structure based on PR 1.5 IOUT1 IOUT2

V1 V2

I O’
i1

I
IO

SQ

resulting, in this case, a perfect linear behavior of the differential amplifier:

pffiffiffiffiffiffiffiffi
IOUT ¼ KIO ðV1  V2 Þ ¼ Gm ðV1  V2 Þ (1.241)
pffiffiffiffiffiffiffiffi
Gm ¼ KIO being the equivalent transconductance of the structure, that could
be very easily controlled by the biasing current, IO . The circuit implementation
is relatively simple, allowing to implement, by minor changes of the design,
a multitude of circuit functions (multiplying, amplifying and simulating a positive
or negative equivalent resistance).
In order to implement (1.240) relation, it is necessary to design a CMOS
structure able to compute the square of the V1  V2 differential input voltage.
A possible implementation of this circuit uses the arithmetical mean of the input
potentials (Fig. 1.64) [6].

K K
I ¼ I1 þ I2  I3 ¼ ðV1  VT Þ2 þ ðV2  VT Þ2
2 2
 2
V1 þ V2 K
K  VT ¼ ðV1  V2 Þ2 ð1:242Þ
2 4

1.2.6 Differential Structures Based on the Sixth

Mathematical Principle (PR 1.6)

The general linearization technique based on the sixth mathematical principle

(PR 1.6) achieves the minimization of superior-order distortions using an anti-
parallel connection of two or more differential amplifiers having controlled
asymmetries and different controlled biasing currents. Using (1.20), the expression
1.2 Analysis and Design of Differential Structures 63

VDD

IREF

V
V1 V2

VDD

I
I3
I1 I2
2K
K K

Fig. 1.64 Squaring circuit for the differential structure based on PR 1.5

of the differential output current for the classical differential amplifier from
Fig. 1.62 [31] will be:

1=2 K 3=2 K 5=2

IOUT ðVI Þ ¼ K 1=2 IO VI þ 1=2
VI3 þ 3=2
VI5 þ    (1.243)
8IO 128IO

As a consequence of the circuit symmetry, the even order terms from the
previous expansion have been cancel out:

IOUT ðVI Þ ¼ a1 VI þ a3 VI3 þ a5 VI5 þ    (1.244)

ak being constant coefficients of the expansion. For simplicity, IO 0 biasing

current from Fig. 1.62 has been renamed IO . The total harmonic distortions of the
classical differential amplifier are mainly given by the third-order term from the
previous expansion:

a3 VI3 K 2
THD ¼ ¼ V (1.245)
a1 VI IO I
64 1 Differential Structures

IOUT1 IOUT2

M3 M1 M2 M4

VI

IO1 IO2

- VDD

Fig. 1.65 Differential structure (1) based on PR 1.6

The first linear term is proportional with the differential-mode voltage gain of
the differential amplifier, while the following two terms model the third-order and
the fifth-order nonlinearities of the transfer characteristic. The most important cause
of the distortions introduced by the circuit nonlinearity is the third-order term from
the previous expansion.
The method for improving the circuit linearity uses an anti-parallel connection
of two differential amplifiers with controlled asymmetries and different controlled
biasing currents (M1–M2 and M3–M4 pairs from Fig. 1.65) [13, 31]. Because
M1–M2 differential amplifier is biased at IO1 current and M3–M4 structure is
biased at IO2 current, the differential output currents for these circuits are:

3=2 5=2
1=2 1=2 K1;2 K1;2
ðID2  ID1 Þ ðVI Þ ¼ K1;2 IO1 VI þ V3
1=2 I
þ 3=2
VI5 þ    (1.246)
8IO1 128IO1

and:

3=2 5=2
1=2 1=2 K3;4 K3;4
ðID4  ID3 Þ ðVI Þ ¼ K3;4 IO2 VI þ V3 þ
1=2 I 3=2
VI5 þ    (1.247)
8IO2 128IO2
1.2 Analysis and Design of Differential Structures 65

The differential output current for the entire anti-parallel structure from Fig. 1.65
will have the following expression:

IOUT2  IOUT1 ¼ ðID2 þ ID3 Þ  ðID1 þ ID4 Þ

¼ ðID2  ID1 Þ  ðID4  ID3 Þ ð1:248Þ

Replacing (1.257) and (1.258) in (1.259), it results:

1=2 1=2 1=2 1=2

IOUT2  IOUT1 ¼ K3;4 IO2  K1;2 IO1 VI
3=2 3=2
! 5=2 5=2
!
K1;2 K3;4 K1;2 K3;4
þ 1=2
 1=2 VI þ 3
3=2
 3=2
VI5 þ    ð1:249Þ
8IO1 8IO2 128IO1 128IO2

The linearization technique is considered to be efficient if it is able to cancel the

third-order distortion, so the condition that must be fulfilled by the design is:

3=2 3=2
K1;2 K3;4
1=2
¼ 1=2
(1.250)
8IO1 8IO2

equivalent with:
 3
IO1 K1;2
¼ (1.251)
IO2 K3;4

Imposing this condition for obtaining the minimization of the circuit nonlinear-
ity, the main distortions will be caused by the fifth-order term from the circuit
transfer characteristic. Using (1.251), relation (1.249) becomes:
"  2=3 #
1=2 1=2 IO2
IOUT2  IOUT1 ¼ K1;2 IO1 1 VI
IO1
5=2
"  2=3 #
K1;2 IO1
 5=2
1 VI5 þ    ð1:252Þ
128IO1 IO2

The total harmonic distortions of the improved linearity differential amplifier

from Fig. 1.65 are mainly given by the fifth-order term from the previous expansion:
   
VI4 K1;2 2 IO1 2=3
0
THD ¼ (1.253)
128 IO1 IO2

resulting an important increasing of the circuit linearity (THD0 is much smaller

than THD).
66 1 Differential Structures

IO4 IO3 IO2 IO1

VI M1 M2 M3 M4 M3’ M2' M1’

M4’

IOUT1 IOUT2

Fig. 1.66 Differential structure (2) based on PR 1.6

In order to further increase the differential amplifier linearity, the previous

technique can be extended for removing both third-order and fifth-order terms
from the Taylor series expansion (1.249). This is possible using a parallel connec-
tion of four differential amplifiers, having controlled asymmetries and controlled
different biasing (Fig. 1.66).
Similarly with the circuit presented in Fig. 1.65, the conditions for canceling the
third-order and the fifth-order distortions are:

 1  1
K2 IO2 3 K1 IO1 3
¼ ; ¼ (1.254)
K3 IO3 K4 IO4

 3  3
K1 IO1 5 K3 IO3 5
¼ ; ¼ (1.255)
K2 IO2 K4 IO4

K1 –K4 being model parameters for M1–M1’, M2–M2’, M3–M3’ and M4–M4’
pairs, respectively. The total harmonic distortions of the circuit presented in
Fig. 1.66 are mainly given by the fifth-order term from the Taylor series expansion
of the transfer characteristic:
  
7=2 5=2 7=2 5=2
 3 1  KK32 IO3
IO2 1  K4
K3
IO4
IO3
1 K2
THD00 ffi 15 6
VID 
1=2 1=2

1=2 1=2
 (1.256)
2 IO2
1  KK32 IO3
IO2 1  K4
K3
IO4
IO3

resulting an important improvement of the circuit linearity by applying this

technique.
An alternate implementation [32] of the previous linearization technique can be
obtained using differential amplifiers based on MOS transistors working in weak
inversion region (Fig. 1.67) [32]. This implementation of the differential amplifier
circuit allows to obtain an important reduction of the current consumption, the
structure being useful for low-power designs. The drive of these transistors is also
realized on their gates and bulks. The utilization of the bulk as active terminal
1.2 Analysis and Design of Differential Structures 67

VDD

IOUT

IOUT2 IOUT1

AaVI

AbVI
M1a M1b M2b M2a

VI

IO1 IO2

-VDD

Fig. 1.67 Differential structure (3) based on PR 1.6

avoids the utilization of large aspect ratios MOS transistors. Aa and Ab represent the
voltage gains used for computing the voltage drives of the bulks.
The drain currents of MOS transistors composing the M1a–M2a differential
amplifier from Fig. 1.67 have the following expressions:

I
ID1;2a ¼   Oa  
VGS1a  VGS2a n  1 VBS1a  VBS2a
1 þ exp  exp 
nVth n Vth
IOa
¼   (1.257)
VI
1 þ exp Ka
Vth

Similarly, for the second differential amplifier, M1b–M2b, the drain currents can
be expressed as follows:

I
ID1;2b ¼   Ob  
VGS1b  VGS2b n  1 VBS1b  VBS2b
1 þ exp  exp 
nVth n Vth
IOb
¼   (1.258)
VI
1 þ exp Kb
Vth
68 1 Differential Structures

where Ka ¼ ½1 þ ðn  1ÞAa =n and Kb ¼ ½1 þ ðn  1ÞAb =n. For evaluating the

circuit linearity, it is necessary to expand in Taylor series the following mathe-
matical function:

1 1 x x3 x5
f ðxÞ ¼ ffi  þ  þ  (1.259)
1 þ expðxÞ 2 4 48 480

Using this fifth-order limited Taylor series expansion, the drain currents of the
M1a–M2a and M1b–M2b differential pairs from Fig. 1.67 will be:
"     #
1 Ka VI 1 VI 3 1 VI 5
ID1;2a ¼ IOa   Ka  Ka   (1.260)
2 4 Vth 48 Vth 480 Vth

and:
"  3  5 #
1 Kb VI 1 VI 1 VI
ID1;2b ¼ IOb   Kb  Kb   (1.261)
2 4 Vth 48 Vth 480 Vth

The differential output current of the entire anti-parallel structure is:

IOUT ¼ IOUT2  IOUT1 ¼ ðID1a þ ID2b Þ  ðID1b þ ID2a Þ

Kb IOb  Ka IOa
¼ ðID1a  ID2a Þ  ðID1b  ID2b Þ ¼ VI
2Vth
K 3 IOa  Kb3 IOb 3 Kb5 IOb  Ka5 IOa 5
þ a VI þ VI þ    ð1:262Þ
24Vth3 240Vth5

The condition for cancellation of the third-order distortions introduced by the

circuit is:
rffiffiffiffiffiffi
Ka 3 IOb 1 þ ðn  1ÞAa
¼ ¼ (1.263)
Kb IOa 1 þ ðn  1ÞAb

resulting the following expression of the IOUT output current:

IOUT ffi a1 VI þ a5 VI5 þ    (1.264)

where a1 and a5 constants are given by:

" 2=3 #
Ka IOb
a1 ¼ IOa 1 (1.265)
2Vth IOa
1.2 Analysis and Design of Differential Structures 69

"  #
Ka5 IOb 2=3
a5 ¼ IOa 1 (1.266)
240Vth5 IOa

The total harmonic distortion coefficient for the linearized circuit will have the
following expression:
   
1 Ka VI 4 1 þ ðn  1ÞAb 2
THD ¼ (1.267)
120 nVth 1 þ ðn  1ÞAa

1.2.7 Differential Structures Based on the Seventh

Mathematical Principle (PR 1.7)

This principle is useful for obtaining a rail-to-rail operation of a differential

structure. The general method for extending the maximal range of the common-
mode input voltage is to use a parallel connection of two complementary (NMOS
and PMOS) differential amplifiers. The simple parallel connection of these stages
has the disadvantage of a variable value of the equivalent transconductance for the
resulted structure, while the utilization of a translinear loop or of a “maximum”
circuit permits to obtain an approximately constant value of the equivalent
transconductance, only slightly dependent on the value of the common-mode
input voltage (R1 ¼ R2 ¼ R3 ¼ R4 ).
A possible method for obtaining a rail-to-rail operation of a differential structure,
using two parallel-connected complementary differential amplifiers is presented in
Fig. 1.68. The NMOS differential amplifier is realized using M1–M4 transistors,
while the PMOS differential circuit is implemented using M5–M8 active devices.
Because these differential amplifiers present complementary common-mode input
ranges, their parallel connection will extend the equivalent domain of the common-
mode input voltage for the entire structure. The DIFF1 and DIFF2 blocks computes
the differential output voltages of the complementary differential amplifiers, while
the SUM block realizes the summation of these two output voltages. For medium
values of the common-mode input voltages, both NMOS and PMOS differential
amplifiers are active, so the equivalent transconductance of the parallel-connected
structure will be equal with the sum of the individual transconductances,
gTm ¼ gmn þ gmp .
The maximal range of the common-mode input voltage for the NMOS differen-
tial amplifier, M1–M4 is included between the following limits:

IO R1 IO R1
max ¼ VDD   VDS1sat þ VGS1 ¼ VDD  þ VT
NMOS
VIC (1.268)
2 2
70 1 Differential Structures

DIFF 1 VDD
R1 R2
+ M5
-

M1 M2 R5

R6 IO IO

VC VI M3 M4

R7

M8

IO

M6 M7

SUM DIFF 2
A + -
+ + R3 R4
VO RL

Fig. 1.68 Differential structure (1) based on PR 1.7

and:
rffiffiffiffiffi
pffiffiffi IO
NMOS
VIC min ¼ VGS1 þ VDS3sat ¼ VGS1 þ VGS3  VT ¼ VT þ 2þ1 (1.269)
K

while the maximal range of the common-mode input voltage for the PMOS
differential amplifier M5–M8 is included between the following limits:

max ¼ VDD  VSG6  VSD8sat ¼ VDD  VSG6  VSG8 þ VT

PMOS
VIC
rffiffiffiffiffi
pffiffiffi IO
¼ VDD  VT  2þ1 ð1:270Þ
K

and:

IO R3 IO R3
min ¼ þ VSD6sat  VSG6 ¼  VT
PMOS
VIC (1.271)
2 2
1.2 Analysis and Design of Differential Structures 71

NMOS
VICmax
VDD
Normal
operation
NMOS DA PMOS
NMOS VICmax
VICmin
Normal
operation
0 PMOS PMOS DA
VICmin

Fig. 1.69 Diagram for the range of VIC

The maximal range of the common-mode input voltage for the parallel-connection
from Fig. 1.68 is determined by superposing the individual common-mode input
ranges for the complementary NMOS and PMOS differential pairs (relations
(1.268) – (1.271)) – Fig. 1.69.
The maximal range of the common-mode input voltage for the parallel connec-
tion from Fig. 1.68 must include the supply voltage range, ½0; VDD . From Fig. 1.69,
the conditions for obtaining this goal are:

max > VDD

NMOS
VIC (1.272)

max > VIC min

PMOS NMOS
VIC (1.273)

min < 0
PMOS
VIC (1.274)

equivalent with:

IO R1 < 2VT (1.275)

and:
" rffiffiffiffiffi#
pffiffiffi IO
VDD > 2 VT þ 2þ1 (1.276)
K

The common-mode input ranges for the two parallel-connected differential

stages are complementary, existing, however, a range of the common-mode input
voltage (corresponding to medium values of this voltages), where the range of
NMOS differential structure overlaps the range of the PMOS differential stage.
Supposing gmn ¼ gmp ¼ gTm , the dependence of the circuit’s total transconductance,
gTm , on the common-mode input voltage is synthesized in Table 1.1.
The disadvantage of this parallel connection of two complementary differential
amplifiers is a value of the equivalent transconductance gTm that depends on the
common-mode input voltage.
72 1 Differential Structures

Table 1.1 Equivalent transconductance for the circuit presented in Fig. 1.68
min < VIC < VIC min min <VIC < VIC max max < VIC < VIC max
VIC range PMOS NMOS NMOS PMOS PMOS NMOS
VIC VIC VIC
NMOS DA 0 gm gm
PMOS DA gm gm 0
Parallel DA gm 2gm gm

Fig. 1.70 Transfer characteristic of the M1–M4 NMOS differential amplifier

The operation of the previous circuit is verified for the following particular
values of their components and model parameters:
R1 ¼ R2 ¼ R3 ¼ R4 ¼ R5 ¼ R6 ¼ R7 ¼ 10 k O, RL ¼ 1 M O, VT ¼ 1 V/  1 V,
l ¼ 3  103 V1 , K 0 ¼ 8  103 A/V2 , W ¼ 30 mm, L ¼ 20 mm. VDD , VI and
VC are continuous input voltages having the following values: 3 V, 1 mV and 1:5 V,
respectively.
For determination of the value of the biasing current IO , it is possible to write the
following relation:

KR5
VDD ¼ 2VGS þ ðVGS  VT Þ2 (1.277)
2

equivalent with:

2
60VGS  118VGS þ 57 ¼ 0 (1.278)

resulting VGS ¼ 1:1135 V and IO ¼ 77:3 mA, very closely to the simulated
obtained value, IO ¼ 73:3 mA.
The simulation of the transfer characteristic for the NMOS differential amplifier
M1–M4 is shown in Fig. 1.70. A similar characteristic can be obtained for the
1.2 Analysis and Design of Differential Structures 73

Fig. 1.71 Transfer characteristic of the M1–M4 NMOS differential amplifier (parametric) (1)

PMOS differential stage M5–M8. The differential-mode voltage gain is

pffiffiffiffiffiffiffiffi
ADD ¼ gm R1 ¼  KIO R1 ¼ 9:63, while the simulated value is  9:71.
Using (1.268) and (1.690), the maximal range of the common-mode input
voltage for the M1–M4 NMOS differential amplifier will be between 1:1934V
and 3:6135V. The simulation of the transfer characteristic (Fig. 1.71) of the
NMOS differential amplifier for three values of the common-mode input voltage,
VC ¼ 3:2V, VC ¼ 3:3V and VC ¼ 3:4V highlights a maximal common-mode input
voltage of about 3:3V.
Similarly, the simulation of the transfer characteristic (Fig. 1.72) of the NMOS
differential amplifier for two values of the common-mode input voltage, VC ¼ 1:1V
and VC ¼ 1:2V points out a minimal common-mode input voltage of about 1:2V.
Using (1.270) and (1.271), the maximal range of the common-mode input
voltage for the PMOS differential amplifier M5–M8 is between  0:6135V and
1:807V. The simulation of the transfer characteristic (Fig. 1.73) of the PMOS
differential amplifier for three values of the common-mode input voltage,
VC ¼ 0:5V, VC ¼ 0:4V and VC ¼ 0:3V highlights a minimal common-mode
input voltage of about  0:4V.
Similarly, the simulation of the transfer characteristic (Fig. 1.74) of the PMOS
differential amplifier for two values of the common-mode input voltage, VC ¼ 1:8V
and VC ¼ 1:9V points out a maximal common-mode input voltage of about 1:8V.
In conclusion, the maximal ranges of the common-mode input voltage are
 0:4V < VIC < 1:8V for the PMOS differential amplifier, and 1:2V < VIC < 3:3V
for the NMOS differential amplifier. The parallel connection of the complementary
circuits extends the maximal range of the common-mode input voltage to
 0:4V < VIC < 3:3V, with the disadvantage of obtaining a variable value of the
equivalent transconductance for the parallel-connected structure (a double trans-
conductance for the range of the common-mode input voltage, in which both
74 1 Differential Structures

Fig. 1.72 Transfer characteristic of the M1–M4 NMOS differential amplifier (parametric) (2)

Fig. 1.73 Transfer characteristic of the M5–M8 PMOS differential amplifier (parametric) (1)

NMOS and PMOS differential amplifiers are active, 1:2V < VIC < 1:8V). So, the
differential mode voltage gain will be not constant, having a value, ADD , for
extreme values of the common-mode input voltages (  0:4V < VIC < 1:2V and
1:8V < VIC < 3:3V) and a double value, 2ADD , for the medium values of the
common-mode input voltages, 1:2V < VIC < 1:8V. This behavior is illustrated in
Fig. 1.75, the simulation of the transfer characteristic of the parallel structure being
done for five values of the common-mode input voltages:
• Two values in the area in which only one differential amplifier (NMOS
or PMOS) is active (VC ¼ 0:5V and VC ¼ 2:5V), the characteristics being
approximately identical;
1.2 Analysis and Design of Differential Structures 75

Fig. 1.74 Transfer characteristic of the M5–M8 PMOS differential amplifier (parametric) (2)

Fig. 1.75 Transfer characteristic of the parallel differential amplifier (parametric)

• Two values near the extended interval, but outside it (VC ¼ 0:5V and
VC ¼ 3:5V), remarking a small decreasing of the differential mode voltage
gain with respect to the previous case, as a result of a fault operation of some
transistors from the circuit
• A value placed in the center of the interval (VC ¼ 1:5V), the differential-mode
voltage gain having a double value comparing with the first case, because both
PMOS and NMOS differential amplifiers are active, the equivalent trans-
conductance being the sum of each individual transconductances.
76 1 Differential Structures

VDD

IO1

VC VI

VDD

VO
IO = max(IO1, IO2)

IO2

Fig. 1.76 Differential structure (2) based on PR 1.7

An improvement of the behavior for the circuit shown in Fig. 1.68 is based on a
circuit able to select the maximal value of two currents (Fig. 1.76). The most
important advantage of this changing consists in that the equivalent trans-
conductance of the resulted circuit is approximately constant and it does not
depend on the value of the common-mode input voltage. The “maximum” circuit
is presented in Fig. 1.77.
For IO1 > IO2 , the relations between the currents from the circuit are:

ID3 ¼ ID4 ¼ ID5 ¼ IO2 (1.279)

ID1 ¼ ID2 ¼ IO1  ID3 ¼ IO1  IO2 (1.280)

IO ¼ ID1 þ ID5 ¼ ðIO1  IO2 Þ þ IO2 ¼ IO1 (1.281)

while for IO1 < IO2 :

ID4 ¼ ID5 ¼ IO2 (1.282)

1.2 Analysis and Design of Differential Structures 77

IO1 IO2

IO

M1 M2 M3 M4 M5

Fig. 1.77 The implementation of the “maximum” circuit

Table 1.2 Equivalent transconductance of the circuit presented in Fig. 1.76

min < VIC < VIC min min < VIC < VIC max max < VIC < VIC max
VIC range PMOS NMOS NMOS PMOS PMOS NMOS
VIC VIC VIC
NMOS DA 0 gm gm
PMOS DA gm gm 0
Parallel modified DA gm gm gm

ID3 ¼ IO1 ; ID1 ¼ ID2 ¼ 0 (1.283)

IO ¼ ID1 þ ID5 ¼ IO2 (1.284)

min < VIC < VIC max ,

NMOS PMOS
For medium values of the common-mode input voltages, VIC
the “maximum” circuit will select the maximal transconductance from gmn and gmp ,
so the equivalent transconductance of the modified parallel circuit from Fig. 1.76
will be approximately constant and independent on the common-mode input
voltage the results are centralized in Table 1.2.
The circuit presented in Fig. 1.78 [33] is designed with the main goal of obtaining
a rail-to-rail operation using a proper biasing of a parallel connection of two comple-
mentary classical differential amplifiers, M1–M2 and M3–M4, biased at IOn and IOp
currents, respectively. The utilization of a translinear loop, that forces a proper
relation between the biasing currents IOn and IOp , has the advantage of obtaining an
approximately constant equivalent transconductance of the entire structure.
The output current of the circuit can be expressed as follows:
 
IOUT ¼ ðIn1  In2 Þ þ ðIP1  IP2 Þ ¼ gmn þ gmp ðV1  V2 Þ (1.285)

where gmn represents the transconductance of M1–M2 NMOS differential ampli-

fier, while gmp is the transconductance of M3–M4 PMOS differential amplifier.
78 1 Differential Structures

1:1:1 1:1

In1 – In2
IOp
1:1 In1 IOUT
IO IOp IO In2
IOn
M8 M3 M4
M5 M6 M7 V1 M1 M2 V2
Ip1 Ip2

IOn Ip1 – Ip2

IO IO
1:1 1:1:1 1:1

Fig. 1.78 Differential structure (3) based on PR 1.7

Supposing a biasing in saturation region of M1–M4 transistors, it is possible

to write that:
pffiffiffiffiffiffiffiffiffiffiffiffi
gmn ¼ Kn IOn (1.286)

and:
pffiffiffiffiffiffiffiffiffiffiffiffi
gmp ¼ Kp IOp (1.287)

Considering that M1–M4 transistors are identical, it results:

pffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffi
IOUT ¼ K IOp þ IOn ðV1  V2 Þ (1.288)

The relation between IOn and IOp currents is imposed by the translinear loop
implemented using M5–M8 transistors:

VGS5 þ VGS7 ¼ VGS6 þ VGS8 (1.289)

Using the square-root dependence of the drain current on the gate-source voltage
for a MOS transistor biased in saturation, it results:
pffiffiffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffi
IOn þ IOp ¼ 2 IO (1.290)

From (1.288) and (1.290), the expression of the output current will be:
pffiffiffiffiffiffiffiffi
IOUT ¼ 2 KIO ðV1  V2 Þ (1.291)

The advantage of this circuit consists in the rail-to-rail operation that can be
obtained because of the parallel connection of two complementary differential
amplifiers (M1–M2 and M3–M4). The utilization of the M5–M8 translinear loop
eliminates the main disadvantage of this method (a variable equivalent transcon-
ductance of the parallel connection, depending on the common-mode input voltage).
1.2 Analysis and Design of Differential Structures 79

VDD
M6

M5 M7
M8 M9
IOUT1 IOUT2
M2 M3

M1 M4
V1 V2

IO
M11 M12 M13 M14

Fig. 1.79 The core of DDA

Using the same principle it is possible to design a double differential amplifier

(DDA), having an extended range of the common-mode input voltage and an
approximately constant equivalent transconductance.
The core of the DDA circuit is represented by a differential stage, having the
circuit presented in Fig. 1.79 [34]. The differential output current of this circuit can
be expressed as follows:
pffiffiffiffiffiffiffiffiffiffi
IOUT1  IOUT2 ¼ 8KIO ðV1  V2 Þ ¼ gmn ðV1  V2 Þ (1.292)

In order to extend the maximal range of the common-mode input voltage,

a parallel connection of two complementary differential amplifiers are used, the
selection of the active one being done using two “maximum” circuits. The differ-
ential amplifier with extended common-mode input range and constant equivalent
transconductance is presented in Fig. 1.80 [34].
Relation (1.305) can be rewritten for the two complementary differential
amplifiers:
pffiffiffiffiffiffiffiffiffiffiffiffi
In1  In2 ¼ 8Kn IO ðV1  V2 Þ ¼ gmn ðV1  V2 Þ (1.293)

and:
pffiffiffiffiffiffiffiffiffiffiffiffi
Ip1  Ip2 ¼ 8Kp IO ðV1  V2 Þ ¼ gmp ðV1  V2 Þ (1.294)
80 1 Differential Structures

VDD

In2 In1 IOUT

V1 V2
VC
IO

VDD

Ip1 Ip2

Fig. 1.80 Differential amplifier with extended common-mode input range

The output current has the following expression:

pffiffiffiffiffiffiffiffiffiffiffiffi
IOUT ¼ maxðIn1 ; Ip2 Þ  maxðIn2 ; IP1 Þ ¼ 8Kn IO ðV1  V2 Þ
pffiffiffiffiffiffiffiffiffiffiffiffi
¼ 8Kp IO ðV1  V2 Þ ¼ gTm ðV1  V2 Þ (1.295)

where gmn ¼ gmp ¼ gTm .

The implementation (Fig. 1.81) of the double differential amplifier is based on
the previous presented differential stage (Fig. 1.79). The output current of DDA
circuit has the following expression:

IOUT ¼ maxðIn2 þ I 0n1 ; Ip1 þ I0p2 Þ  maxðIn1 þ I 0n2 ; Ip2 þ I0p1 Þ

   
¼ gTm Vpp  Vpn  Vnp  Vnn (1.296)

Because of the utilization of the differential amplifier with extended common-

mode input range, the equivalent transconductance of the DDA, gTm , will be
approximately constant.

1.2.8 Differential Structures Based on Different

Mathematical Principle (PR 1.D)

Another possible realization of a DDA is presented in Fig. 1.81 [35], having a

relatively simple implementation comparing with the previous designs of similar
circuits.
1.2 Analysis and Design of Differential Structures 81

VDD

IOUT1 IOUT2

V1 VB VA V2
V4 VC VD V3

VO

Fig. 1.81 DDA based on PR 1.D

The expressions of IA and IB currents are:

K K K K
IOUT1 ¼ ðV1  VT Þ2 þ ðV4  VT Þ2 þ ðVC  VT Þ2 þ ðVB  VT Þ2 (1.297)
2 2 2 2

and:

K K K K
IOUT2 ¼ ðV2  VT Þ2 þ ðV3  VT Þ2 þ ðVA  VT Þ2 þ ðVD  VT Þ2 (1.298)
2 2 2 2

The differential output current of the DDA circuit will have the following
expressions:

K
IOUT1  IOUT2 ¼ ðV1  VA ÞðV1 þ VA  2VT Þ
2
K
þðV4  VD ÞðV4 þ VD  2VT Þ
2
K K
þ ðVB  V2 ÞðVB þ V2  2VT Þ þ ðVC  V3 ÞðVC þ V3  2VT Þ (1.299)
2 2

Because:

VO ¼ V1  VA ¼ V2  VB ¼ V3  VC ¼ V4  VD (1.300)

it can be obtained:

IOUT1  IOUT2 ¼ KVO ½ðV4  V3 Þ  ðV2  V1 Þ (1.301)

82 1 Differential Structures

VDD

IO IO
IOUT1 IOUT2

V1

V2 M1 M2

V3 M3 M4

VA VB
V4

IO + IOUT1 IO + IOUT2

Fig. 1.82 Differential structure (1) based on PR 1.D

A linear transfer characteristic for a differential amplifier can be obtained using

the circuit presented in Fig. 1.82 [36], the simplicity recommending it for a
multitude of analog signal processing applications.
As M1 and M2 transistors from Fig. 1.82 are biased at IO drain currents, VA and
VB potentials can be expressed as follows:
rffiffiffiffiffiffiffi
2IO
VA ¼ V2  VT  (1.302)
K

and:
rffiffiffiffiffiffiffi
2IO
VB ¼ V1  VT  (1.303)
K

The expressions of IOUT1 and IOUT2 currents will be:

K
IOUT1 ¼ ðV3  VA  VT Þ2 (1.304)
2

and:

K
IOUT2 ¼ ðV4  VB  VT Þ2 (1.305)
2

Replacing (1.302) and (1.303) in (1.304) and (1.305), it results:

rffiffiffiffiffiffiffi!2
K 2IO
IOUT1 ¼ V3  V2 þ (1.306)
2 K
1.2 Analysis and Design of Differential Structures 83

Fig. 1.83 Differential

structure (2) based on PR 1.D
IOUT1 IOUT2
VC1 VC2

V1 V2
V

IO

and:

rffiffiffiffiffiffiffi!2
K 2IO
IOUT2 ¼ V4  V1 þ (1.307)
2 K

The input potentials are chosen to have both common-mode and differential-
mode components:

V1 ¼ VC  Vi1 (1.308)

V2 ¼ VC þ Vi1 (1.309)

V3 ¼ VC þ Vi2 (1.310)

and:

V4 ¼ VC  Vi2 (1.311)

resulting that the differential output current will have the following expression:

rffiffiffiffiffiffiffi!2
K 2IO
IOUT1  IOUT2 ¼ Vi2  Vi1 þ
2 K
!
rffiffiffiffiffiffiffi 2
K 2IO pffiffiffiffiffiffiffiffiffiffi
 Vi1  Vi2 þ ¼ 8KIO ðVi2  Vi1 Þ ð1:312Þ
2 K

A differential amplifier using FGMOS transistors for cancellation of the errors

introduced by the input offset voltage is presented in Fig. 1.83 [37].
84 1 Differential Structures

The VC1 and VC2 voltages represent external applied continuous voltages.
Considering a biasing in saturation of all transistors from Fig. 1.83 and FGMOS
transistors having identical inputs, the expressions of IOUT1 and IOUT2 currents are:
 2
K V1 þ VC1
IOUT1 ¼  V  VT (1.313)
2 2

and:
 2
K V2 þ VC2
IOUT2 ¼  V  VT (1.314)
2 2

resulting:
rffiffiffiffi
2 pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffi V1  V2 VC1  VC2
IOUT1  IOUT2 ¼ þ (1.315)
K 2 2

Using the notations VID ¼ V1  V2 and DVC ¼ VC1  VC2 and replacing the
IOUT1 þ IOUT2 sum with IO , the previous relation becomes:

8h pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffii
IO  2 IOUT1 ðIO  IOUT1 Þ ¼ ðVID þ DVC Þ2 (1.316)
K

After some computations, it results the following expressions of IOUT1 and IOUT2
currents:
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
IO IO K K2
IOUT1 ¼ þ ðVID þ DVC Þ  ðVID þ DVC Þ2 (1.317)
2 2 4IO 64IO2

and:
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
IO IO K K2
IOUT2 ¼  ðVID þ DVC Þ  ðVID þ DVC Þ2 (1.318)
2 2 4IO 64IO2

So, the differential output current of the circuit presented in Fig. 1.83 will
have the following expression:
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
K K2
IOUT1  IOUT2 ¼ IO ðVID þ DVC Þ  ðVID þ DVC Þ2 (1.319)
4IO 64IO2

The expression is similar with the result obtained for the differential amplifier
based on MOS transistors biased in saturation. The advantage of using FGMOS
References 85

transistors for replacing classical MOS active devices is given by the possibility of
compensating the input offset voltage of the differential amplifier by choosing
a proper biasing voltage DVC , complementary with the intrinsic offset voltage of
the stage.

1.3 Conclusions

Chapter extensively presents a multitude of design techniques for improving the

performances of CMOS differential structures. The main goals of these design
methods are to improve the linearity of differential structures and to obtain a rail-
to-rail operation, for a more efficient utilization of the available supply voltage. The
functional mathematical principles of operation that represent the basis for design-
ing the presented linearization techniques have been used in order to minimize the
linearity error of the implemented CMOS differential structures.

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Chapter 2
Voltage and Current Multiplier Circuits

2.1 Mathematical Analysis for Synthesis of Multipliers

The synthesis of multiplier circuits [1–60] is based on the utilization of some

elementary principles, each of them representing the starting point for designing a
class of multiplier circuit.
Referring to the input variables, it can be identified two important classes of
multiplier circuits:
– Voltage multipliers, having as input variables two single or differential voltages
and generating an output current proportional with the product of these input
voltages;
– Current multipliers, receiving as inputs two currents and producing an output
current proportional with the product of the input currents.
Because the multiplying function uses the characteristic of MOS transistors
biased in saturation region, most of mathematical principles are derived from a
linear relation between squaring terms (having voltages or currents as variables).
The notations used for revealing these principles are: V1 , V2 , V3 and V4 represent
the input potentials, while, usually, a constant voltage, VO , is introduced for
modeling a voltage shifting; for current multipliers, I1 , I2 and I3 are the input
currents and IO represents a reference current. In both cases, IOUT denotes the
output current of the multiplier circuit.

C.R. Popa, Synthesis of Computational Structures for Analog Signal Processing, 89

DOI 10.1007/978-1-4614-0403-3_2, # Springer Science+Business Media, LLC 2011
90 2 Voltage and Current Multiplier Circuits

2.1.1 Mathematical Analysis of Voltage Multiplier Circuits

2.1.1.1 First Mathematical Principle (PR 2.1)

The first mathematical principle used for implementing voltage multiplier circuits
is based on the following identity:

ðV1 þ V2 þ VO Þ2  ðV1  V2 þ VO Þ2 þ ðV1  V2 þ VO Þ2

 ðV1 þ V2 þ VO Þ2 ¼ 2V2 ð2V1 þ 2VO Þ  2V2 ð2V1 þ 2VO Þ ¼ 8V1 V2 (2.1)

The voltage multipliers based on the previous relation computes a current

proportional with the product of two input voltages, V1 and V2 .

2.1.1.2 Second Mathematical Principle (PR 2.2)

The mathematical relation that models this principle is

ðV1 þ V3 þ VO Þ2  ðV2 þ V3 þ VO Þ2 þ ðV2 þ V4 þ VO Þ2

 ðV1 þ V4 þ VO Þ2 ¼ ðV1  V2 ÞðV1 þ V2 þ 2V3 þ 2VO Þ
 ðV1  V2 ÞðV1 þ V2 þ 2V4 þ 2VO Þ ¼ 2ðV1  V2 ÞðV3  V4 Þ (2.2)

The circuits that use this principle generates a current proportional with the
product between two differential input voltages, V1  V2 and V3  V4 .

2.1.1.3 Third Mathematical Principle (PR 2.3)

This principle is illustrated by the following mathematical relation:

ðV1  V3 þ VO Þ2  ðV1  V4 þ VO Þ2 þ ðV2  V4 þ VO Þ2

 ðV2  V3 þ VO Þ2 ¼ ðV4  V3 Þð2V1  V3  V4 þ 2VO Þ
 ðV4  V3 Þð2V2  V3  V4 þ 2VO Þ ¼ 2ðV1  V2 ÞðV4  V3 Þ (2.3)

The multiplier circuits that implement this principle compute, also, an output
current proportional with the product between two differential input voltages,
V1  V2 and V4  V3 .
2.1 Mathematical Analysis for Synthesis of Multipliers 91

2.1.1.4 Fourth Mathematical Principle (PR 2.4)

The fourth mathematical principle is based on the following mathematical relation:

pffiffiffiffiffi
IOUT ¼ a IO ðV1  V2 Þ pffiffiffi
) IOUT ¼ a bðV1  V2 ÞðV3  V4 Þ (2.4)
IO ¼ bðV3  V4 Þ2

or
pffiffiffiffi pffiffiffiffi
IOUT ¼ a I1  I2 ðV1  V2 Þ pffiffiffi
pffiffiffiffi pffiffiffiffi2 ) IOUT ¼ a bðV1  V2 ÞðV3  V4 Þ (2.5)
I1  I2 ¼ bðV3  V4 Þ2

a and b represent constant coefficients, depending on the particular implementation

of the multiplier circuit based on this mathematical principle.

2.1.1.5 Fifth Mathematical Principle (PR 2.5)

The fifth mathematical principle represents the cancellation of a nonlinear depen-

dence of an output current, IOUT , on the input voltage, V1 :
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
IO þ KV12 =4 V12 pffiffiffiffiffiffiffiffi
IOUT ¼ KV1  ¼ KIO V1 (2.6)
K 4

2.1.1.6 Sixth Mathematical Principle (PR 2.6)

The mathematical relation that models this principle is

 2  2  2
V 1 þ V2 V1 V2
 VO þ VO2   VO   VO ¼ V1 V2 (2.7)
2 2 2

2.1.1.7 Seventh Mathematical Principle (PR 2.7)

The identity representing the basis of this mathematical relation is

ðV1 þ V2 Þ2  ðV1  V2 Þ2 ¼ 4V1 V2 (2.8)

92 2 Voltage and Current Multiplier Circuits

2.1.1.8 Different Mathematical Principles for Voltage

Multipliers (PR 2.Da)

A class of multipliers can be designed starting from different mathematical

principles, that are useful for linearizing the behavior of the multiplier circuits.

2.1.2 Mathematical Analysis of Current Multiplier Circuits

2.1.2.1 Ninth Mathematical Principle (PR 2.9)

The ninth mathematical principle uses two square-rooting circuits in order to

implement the multiplying function:
pffiffiffiffiffiffiffiffiffiffiffiffiffi
IO1 ¼ a IO IOUT
pffiffiffiffiffiffiffiffi I1 I2
IO2 ¼ a I1 I2 ) IOUT ¼
IO
IO1 ¼ IO2 ð2:9Þ

2.1.2.2 Tenth Mathematical Principle (PR 2.10)

The identity representing the basis of this mathematical relation is

" # " #
ðI1 þ I2 Þ2 ðI1 þ I2 Þ2 4I1 I2
IO þ  IO  ¼ (2.10)
aIO aIO aIO

2.1.2.3 Eleventh Mathematical Principle (PR 2.11)

In order to implement the eleventh mathematical principle, the circuits use only
MOS transistors biased in weak inversion region, the translinear loops that contain
gate-source voltages generating the product between the input currents.

2.1.2.4 Different Mathematical Principles for Current

Multipliers (PR 2.Db)

A class of multipliers can be designed starting from different mathematical

principles that are useful for linearizing the behavior of the current multiplier
circuits.
2.2 Analysis and Design of Multiplier Circuits 93

VDD

IO IO
IOUT2 IOUT1

M1 M7 M8 M4
-V1 -V2 M5 M2 M3 M6 V2 -V1
V
V1

IO
IO

-VDD

Fig. 2.1 Multiplier circuit (1) based on PR 2.1

2.2 Analysis and Design of Multiplier Circuits

2.2.1 Design of Voltage Multiplier Circuits

Based on the previous presented mathematical analysis, the voltage multipliers

can be clustered in eight important functional classes: circuits using PR 2.1–PR
2.7 elementary principle and a class containing multipliers based on different
functional relations.

2.2.1.1 Multiplier Circuits Based on the First Mathematical

Principle (PR 2.1)

The multiplier structures using as functional basis PR 2.1 present the important
advantage of using a symmetrical structure that minimizes the intrinsic linearity
error of the designed circuits.
A circuit that implements the product between two input voltages using the PR
2.1 mathematical principle is presented in Fig. 2.1 [1].
The output current of the voltage multiplier can be expressed as a linear function
of the currents, IOUT1 and IOUT2 :

IOUT ¼ IOUT1  IOUT2 ¼ ðID2 þ ID4 Þ  ðID1 þ ID3 Þ (2.11)

The drain current of M1 transistor is

K
ID1 ¼ ðV1  V  VT Þ2 (2.12)
2
94 2 Voltage and Current Multiplier Circuits

The V potential is imposed by V2 potential and by the gate-source of M5

transistor (that is biased at a constant current, IO ) to be equal with:

rffiffiffiffiffiffiffi
2IO
V ¼ V2  VGS5 ¼ V2  VT  (2.13)
K

Replacing (2.13) in (2.12), it results the following dependence of ID1 current on

V1 , and V2 input potentials:

rffiffiffiffiffiffiffi!2
K 2IO
ID1 ¼ V1 þ V2 þ (2.14)
2 K

Similarly, the drain currents of M2–M4 transistors can be expressed as

rffiffiffiffiffiffiffi!2
K 2IO
ID2 ¼ V1 þ V2 þ (2.15)
2 K

rffiffiffiffiffiffiffi!2
K 2IO
ID3 ¼ V1  V2 þ (2.16)
2 K

rffiffiffiffiffiffiffi!2
K 2IO
ID4 ¼ V1  V2 þ (2.17)
2 K

The expression of the output current as a function of input potentials can be

obtained using relations (2.11) and (2.14)–(2.17):

rffiffiffiffiffiffiffi! rffiffiffiffiffiffiffi!
K 2IO K 2IO
IOUT ¼ 2V1 2V2 þ 2 þ ð2V1 Þ 2V2 þ 2 ¼ 4KV1 V2 (2.18)
2 K 2 K

Another multiplier structure based on the first mathematical principle (PR 2.1) is
presented in Fig. 2.2 [2]. Its output current can be expressed as

IOUT ¼ ðID1 þ ID3 Þ  ðID2 þ ID4 Þ ¼ ðID1  ID2 Þ þ ðID3  ID4 Þ (2.19)

For M1–M4 transistors, the gate potentials are imposed by the common-mode
voltage VC and by the differential components  V1 =2 and  V2 =2.
2.2 Analysis and Design of Multiplier Circuits 95

IOUT1 IOUT2

M1 M2 M3 M4

V1/2 -V1/2 -V1/2 V1/2

V2/2 V2/2 -V2/2 -V2/2

VC VS

Fig. 2.2 Multiplier circuit (2) based on PR 2.1

Replacing the expressions of the previous drain currents with their quadratic
dependence on the gate-source voltages, it results:
 2
K V 1 þ V2
IOUT ¼ IOUT1  IOUT2 ¼ þ VC  VS  VT
2 2
 2  2
K V1 þ V2 K V1  V2
þ  þ VC  VS  VT  þ VC  VS  VT
2 2 2 2
 2
K V2  V1
 þ VC  VS  VT ð2:20Þ
2 2

So, the output current will be proportional with the product between the differ-
ential-mode input voltages:

K
IOUT ¼ V1 ðV2 þ 2VC  2VS  2VT Þ
2
K
þ ðV1 ÞðV2 þ 2VC  2VS  2VT Þ ¼ KV1 V2 ð2:21Þ
2
An alternate realization of a voltage multiplier circuit based on the first
mathematical principle (PR 2.1) is presented in Fig. 2.3. In order to reduce the
96 2 Voltage and Current Multiplier Circuits

VDD

IOUT

M1 M2 M3 M4

V1
- V1
V2
- V2

Fig. 2.3 Multiplier circuit (3) based on PR 2.1

circuit complexity, a part of classical MOS transistors have been replaced by

FGMOS active devices with identical inputs.
The output current can be expressed as follows:
 2
K V1 þ V2
IOUT ¼ ðID1  ID2 Þ þ ðID4  ID3 Þ ¼  VT
2 2
 2  2
K V1  V2 K V1 þ V2
  VT þ   VT
2 2 2 2
 2
K V2  V1 K K
  VT ¼ V2 ðV1  2VT Þ V2 ðV1  2VT Þ ¼ KV1 V2 ð2:22Þ
2 2 2 2

2.2.1.2 Multiplier Circuits Based on the Second Mathematical

Principle (PR 2.2)

The multipliers based on PR 2.2 can be used in a large area of applications that
require the implementation of the product between two differential voltages.
A voltage multiplier having as functional relation the second mathematical
principle (PR 2.2) is presented in Fig. 2.4 [3].
All MOS transistors are biased in saturation region and VO represents a constant
voltage that is summed with V3 and V4 voltages. The expression of differential
output current is

IOUT1  IOUT2 ¼ ðID5 þ ID16 Þ  ðID8 þ ID13 Þ (2.23)

2.2 Analysis and Design of Multiplier Circuits 97

VDD

M2 M10
IOUT1 IOUT2

M3 M11

M6 M14
VX M5 M8 M16 M13 VY
VW VZ
V3 + VO V1 V2 V2 V1 V 4 + VO
M1 M4 M7 M15 M12 M9
-VDD

Fig. 2.4 Multiplier circuit (1) based on PR 2.2

where the previous drain currents can be expressed as follows:

K
ID5 ¼ ðVX þ VDD  VT Þ2 (2.24)
2
K
ID16 ¼ ðVZ þ VDD  VT Þ2 (2.25)
2

K
ID8 ¼ ðVW þ VDD  VT Þ2 (2.26)
2

K
ID13 ¼ ðVY þ VDD  VT Þ2 (2.27)
2

As a consequence of the circuit configuration, the gate-source voltages of M2

and M3 transistors are equal, resulting ID2 ¼ ID3 . But ID3 ¼ ID4 and ID1 ¼ ID2 , so
ID1 ¼ ID4 . In conclusion, because M1 and M4 transistors are identical, it results
VGS1 ¼ VSG4 , equivalent with:

V3 þ VO þ VDD ¼ VX  V1 (2.28)

Thus, the expression of VX potential will be

VX ¼ V1 þ V3 þ VO þ VDD (2.29)

Replacing (2.29) in (2.24), the drain current of M5 transistor will have the
following expression:

K
ID5 ¼ ½ðV1 þ V3 Þ þ ð2VDD þ VO  VT Þ2 (2.30)
2

Similarly, the expression of drain currents of M8, M13 and M16 transistor will be
K
ID8 ¼ ½ðV2 þ V3 Þ þ ð2VDD þ VO  VT Þ2 (2.31)
2
98 2 Voltage and Current Multiplier Circuits

IOUT1 IOUT2

V3
V1

V2 V4

Fig. 2.5 Multiplier circuit (2) based on PR 2.2

K
ID13 ¼ ½ðV1 þ V4 Þ þ ð2VDD þ VO  VT Þ2 (2.32)
2

K
ID16 ¼ ½ðV2 þ V4 Þ þ ð2VDD þ VO  VT Þ2 (2.33)
2

Replacing (2.30)–(2.33) in (2.23), it results:

K
IOUT1  IOUT2 ¼ ðV1  V2 ÞðV1 þ V2 þ 2V3 þ 4VDD þ 2VO  2VT Þ
2
K
 ðV1  V2 ÞðV1 þ V2 þ 2V4 þ 4VDD þ 2VO  2VT Þ ð2:34Þ
2

So

IOUT1  IOUT2 ¼ K ðV1  V2 Þ ðV3  V4 Þ (2.35)

A possible implementation of a voltage multiplier based on the second mathemat-

ical principle (PR 2.2), using FGMOS transistors is presented in Fig. 2.5 [4].
Considering identical inputs for all FGMOS transistors, the differential output
current of the voltage multiplier presented in Fig. 2.5 can be expressed as follows:

 2  2
K V1 þ V2 K V3 þ V4
IOUT ¼ IOUT1  IOUT2 ¼  VT þ  VT
2 2 2 2
 2  2
K V2 þ V3 K V1 þ V4 K
  VT   VT ¼ ðV1  V3 ÞðV2  V4 Þ
2 2 2 2 4
(2.36)
2.2 Analysis and Design of Multiplier Circuits 99

IOUT1 IOUT2

V3
V1

V2 V4

VS

IO

Fig. 2.6 Multiplier circuit (3) based on PR 2.2

An alternate implementation of a voltage multiplier using the second mathemati-

cal principle is presented in Fig. 2.6 [4].
The differential output current of the voltage multiplier shown in Fig. 2.6 will
have the following expression:
 2
K V1 þ V2
IOUT ¼ IOUT1  IOUT2 ¼  VS  VT
2 2
 2  2
K V3 þ V4 K V 2 þ V3
þ  VS  VT   VS  VT
2 2 2 2
 2
K V1 þ V4 K
  VS  VT ¼ ðV1  V3 Þ ðV2  V4 Þ ð2:37Þ
2 2 4

The multiplier circuit presented in Fig. 2.7 [5] is based on the second mathematical
principle (PR 2.2).
The output current of the voltage multiplier is implemented (using an additional
current mirror, not shown in Fig. 2.7) to be the difference between IOUT2 and IOUT1
currents and it can be expressed as follows:

IOUT ¼ IOUT2  IOUT1 ¼ ðI1 þ I4 Þ  ðI2 þ I3 Þ

 2  2
K V1 þ V3 þ VG K V2 þ V4 þ VG
¼  VT þ  VT
2 3 2 3
 2  2
K V 1 þ V4 þ VG K V2 þ V3 þ VG
  VT   VT ð2:38Þ
2 3 2 3
100 2 Voltage and Current Multiplier Circuits

IOUT1 IOUT2

I1 I2 I3 I4

V1 V2
V3 M1 M2 M3 M4 V4
VG

Fig. 2.7 Multiplier circuit (4) based on PR 2.2

resulting:
 
K V3  V4 2V1 þ V3 þ V4 þ 2VG
IOUT ¼  2VT
2 3 3
 
K V3  V4 2V2 þ V3 þ V4 þ 2VG
  2VT ð2:39Þ
2 3 3

So, the output current is proportional with the product between the differential
input voltages:

K
IOUT ¼ ðV3  V4 Þ ðV1  V2 Þ (2.40)
9

2.2.1.3 Multiplier Circuits Based on the Third Mathematical

Principle (PR 2.3)

Alternative implementations of multiplier circuits designed for differential input

voltages uses the mathematical relations described by PR 2.3.
A combination of two differential amplifiers, M1–M2 and M3–M4, can implement
the multiplying function (Fig. 2.8), the functional equations of this circuit being
obtained using the third mathematical principle (PR 2.3) [6].
The gate-source voltages of M1 and M5 transistors are equal because they are
identical and biased at the same drain current, resulting:

VDD  V3 ¼ V  V1 (2.41)

equivalent with:

V ¼ V1  V3 þ VDD (2.42)
2.2 Analysis and Design of Multiplier Circuits 101

VDD

M13 M14
IOUT

V3 V4 V4 V3
M1 M2 M3 M4

V1 V2
M9 V M10 M11 M12

M5 M6 M11 M12

Fig. 2.8 Multiplier circuit (1) based on PR 2.3

The drain current of M9 transistor can be expressed as follows:

K K K
ID9 ¼ ðVGS9  VT Þ2 ¼ ðV  VT Þ2 ¼ ½ðV1  V3 Þ þ ðVDD  VT Þ2 (2.43)
2 2 2

Similarly, the expressions of drain currents for M10, M11 and M12 transistors are:

K
ID10 ¼ ½ðV1  V4 Þ þ ðVDD  VT Þ2 (2.44)
2

K
ID11 ¼ ½ðV2  V4 Þ þ ðVDD  VT Þ2 (2.45)
2

K
ID12 ¼ ½ðV2  V3 Þ þ ðVDD  VT Þ2 (2.46)
2

The output current IOUT of the multiplier will be expressed by

IOUT ¼ ID9 þ ID11  ID10  ID12 (2.47)

resulting:

K
IOUT ¼ ðV4  V3 Þð2V1  V3  V4 þ 2VDD  2VT Þ
2
K
þ ðV3  V4 Þð2V2  V3  V4 þ 2VDD  2VT Þ ð2:48Þ
2

or

IOUT ¼ K ðV2  V1 Þ ðV3  V4 Þ (2.49)

102 2 Voltage and Current Multiplier Circuits

VDD

M13 M14
IOUT

V1 V2
M1 M2 M3 M4

M9 M10 V4 M11 M12

V5 V6 V7 V8
V3 V3
M5 M6 M7 M8

Fig. 2.9 Multiplier circuit (2) based on PR 2.3

The voltage multiplying function can be implemented using the third mathematical
principle (PR 2.3) by the structure presented in Fig. 2.9 [7].
The circuit contains four pairs of transistors (M1–M5, M2–M6, M3–M7 and
M4–M8) that implement voltage subtraction functions. Because M1 and M5
transistors are identical and biased at the same drain current, their gate-source
voltages will be equal, so that:

VDD  V1 ¼ V5  V3 (2.50)

resulting that V5 potential is given by the differential input voltage, V3  V1 :

V5 ¼ VDD þ ðV3  V1 Þ (2.51)

The V5 potential is applied on the gate of M9 transistor, its drain current

being expressed using the squaring characteristic of the MOS transistor biased
in saturation:

K K
ID9 ¼ ðV5  VT Þ2 ¼ ½ðVDD  VT Þ þ ðV3  V1 Þ2 (2.52)
2 2

Similarly, the drain currents of M10, M11 and M12 transistors are

K K
ID10 ¼ ðV6  VT Þ2 ¼ ½ðVDD  VT Þ þ ðV4  V2 Þ2 (2.53)
2 2

K K
ID11 ¼ ðV7  VT Þ2 ¼ ½ðVDD  VT Þ þ ðV4  V1 Þ2 (2.54)
2 2

K K
ID12 ¼ ðV8  VT Þ2 ¼ ½ðVDD  VT Þ þ ðV3  V2 Þ2 (2.55)
2 2
2.2 Analysis and Design of Multiplier Circuits 103

VDD

M13 M14
IOUT

V1 M1 V3 M5 M7 M9 M11 V4 M3 V2

VM M8 M4 VN
M6 M10
VO M2 M12 VO
I1 I2 I3 I4

Fig. 2.10 Multiplier circuit (3) based on PR 2.3

The output current of the voltage multiplier presented in Fig. 2.9 can be
expressed as a linear relation using the previous currents:

IOUT ¼ ID9 þ ID10  ID11  ID12 (2.56)

resulting:

K
IOUT ¼ ðV3  V4 Þð2VDD  2VT þ V3 þ V4  2V1 Þ
2
K
þ ðV4  V3 Þð2VDD  2VT þ V3 þ V4  2V2 Þ ð2:57Þ
2

So, the circuit implements the voltage multiplying function:

IOUT ¼ K ðV3  V4 Þ ðV2  V1 Þ (2.58)

A multiplier circuit using exclusively MOS transistors biased in saturation region,

based on the third mathematical principle (PR 2.3), is presented in Fig. 2.10 [8].
The M1 and M2 transistors form a difference circuit that generates VM
potential. Considering identical transistors and because they are biased at the
same drain current, it results equal gate-source voltages for these transistors.
Thus, VM potential will have the following expression:

VM ¼ V1  VGS1 ¼ V1  VGS2 ¼ V1  VO (2.59)

104 2 Voltage and Current Multiplier Circuits

The gate-source voltage of M5 transistor can be obtained using the equality

between gate-sources of M5 and M6 transistors:

V3  VM ¼ 2VGS5 (2.60)

resulting:

V3  VM V3  V1 þ VO
VGS5 ¼ ¼ (2.61)
2 2
Thus, the expression of I1 current will be
 2
K K V3  V1 þ VO
I1 ¼ ðVGS5  VT Þ2 ¼  VT (2.62)
2 2 2

Similarly, it is possible to determine the expressions of I2 , I3 and I4 currents:

 2
K V4  V1 þ VO
I2 ¼  VT (2.63)
2 2
 2
K V3  V2 þ VO
I3 ¼  VT (2.64)
2 2
 2
K V4  V2 þ VO
I4 ¼  VT (2.65)
2 2

The output current can be expressed as a linear function of the previous currents:

IOUT ¼ I1 þ I4  I2  I3 (2.66)

resulting:
 
K V2  V1 2V3  V1  V2 þ 2VO
IOUT ¼  2VT
2 2 2
 
K V2  V1 2V4  V1  V2 þ 2VO
  2VT ð2:67Þ
2 2 2

So

K
IOUT ¼ ðV2  V1 Þ ðV3  V4 Þ (2.68)
4

The multiplier circuit presented in Fig. 2.11 [9] implements the same mathematical
principle PR 2.3 and it is composed from two differential amplifiers, M1–M4
2.2 Analysis and Design of Multiplier Circuits 105

VDD

M4 M8
V2
V V’
V1 V1
M1 M2 M5 M6

V3 V4
M3 M7

IOUT1 IOUT2
IO IO

Fig. 2.11 Multiplier circuit (4) based on PR 2.3

and M5–M8. For obtaining a low impedance in the common-source points,

each differential amplifier uses a flipped voltage follower (M3–M4 and, M7–M8,
respectively). The M4 and M8 transistors absorb current variations of M1–M2
differential pairs and M5–M6.
The differential output current of the first differential amplifier, M1–M2 can be
expressed using the squaring law of MOS transistors biased in saturation region:

K K
ID1  ID2 ¼ ðV  V1  VT Þ2  ðV  V2  VT Þ2
2 2
K
¼ ðV2  V1 Þ ð2V  V1  V2  2VT Þ ð2:69Þ
2

Similarly, the expression of the differential output current for the second
differential amplifier, M5–M6 is

K
ID5  ID6 ¼ ðV1  V2 Þ ð2V 0  V1  V2  2VT Þ (2.70)
2

The differential output current of the entire multiplier circuit presented in

Fig. 2.11 will have the following expression:

IOUT1  IOUT2 ¼ ðID1 þ ID5 Þ  ðID2 þ ID6 Þ ¼ ðID1  ID2 Þ þ ðID5  ID6 Þ (2.71)

Replacing (2.69) and (2.70) in (2.71), it results:

IOUT1  IOUT2 ¼ K ðV2  V1 Þ ðV  V 0 Þ (2.72)

106 2 Voltage and Current Multiplier Circuits

VDD

IOUT

I2 I3
I4 M4 I1 M1 M2 M3
V1 V2
V 3’
V3
M5
V4’
V4 M6

IO IO

Fig. 2.12 Multiplier circuit (5) based on PR 2.3

Because M3 and M7 transistors are biased at a constant current, IO , imposed by

external current generators, the V and V 0 potentials can be expressed as follows:
rffiffiffiffiffiffiffi
2IO
V ¼ V3 þ VSG3 ¼ V3 þ VT þ (2.73)
K

and
rffiffiffiffiffiffiffi
0 2IO
V ¼ V4 þ VSG7 ¼ V4 þ VT þ (2.74)
K

From (2.72), (2.73) and (2.74), it results the multiplying function implemented
by the circuit from Fig. 2.11:

IOUT1  IOUT2 ¼ K ðV2  V1 Þ ðV3  V4 Þ (2.75)

A possible realization of a voltage multiplier, based on the third mathematical

principle (PR 2.3) is presented in Fig. 2.12 [10]. The core of the circuit is
represented by the group of M1–M4 transistors. Using identical devices, their
drain currents will have the following expressions:

K
I1 ¼ ðV1  V3 0  VT Þ2 (2.76)
2

K
I2 ¼ ðV2  V3 0  VT Þ2 (2.77)
2
2.2 Analysis and Design of Multiplier Circuits 107

K
I3 ¼ ðV2  V4 0  VT Þ2 (2.78)
2

K
I4 ¼ ðV1  V4 0  VT Þ2 (2.79)
2

As a result of using additional current mirrors, the output current of the

differential structure will have a linear variation with respect to I1  I4 currents:

IOUT ¼ ðI2  I1 Þ þ ðI4  I3 Þ (2.80)

resulting:

K
IOUT ¼ ðV2  V1 Þ ðV1 þ V2  2V3 0  2VT Þ
2
K
þ ðV1  V2 Þ ðV1 þ V2  2V4 0  2VT Þ ¼ K ðV1  V2 Þ ðV3 0  V4 0 Þ ð2:81Þ
2
Because M5 and M6 transistors are biased at the constant current, IO , they will
introduce a voltage shifting between V3 and V3 0 and, respectively, between V4 and V4 0
potentials, as follows:
rffiffiffiffiffiffiffi
0 2IO
V3 ¼ V3 þ VSG5 ¼ V3 þ VT þ (2.82)
K
and
rffiffiffiffiffiffiffi
0 2IO
V4 ¼ V4 þ VSG6 ¼ V 4 þ VT þ (2.83)
K

From the previous relations, it results the following expression of the output
current:

IOUT ¼ KðV1  V2 Þ ðV3  V4 Þ (2.84)

A voltage multiplier can be designed using 4 v squaring circuits (Fig. 2.13).

Considering that the output current of the voltage squaring circuits is equal with
KDV 2 =2 DV being its differential input voltage, the differential output current of
the multiplier presented in Fig. 2.13 will have the following expression:

K K
IOUT1  IOUT2 ¼ ðV1  V4 Þ2 þ ðV2  V3 Þ2
2 2
K K
 ðV1  V2 Þ  ðV3  V4 Þ2
2
ð2:85Þ
2 2
108 2 Voltage and Current Multiplier Circuits

V1 V2 V3 V4

SQ I SQ II SQ III SQ IV

IOUT1 IOUT2

Fig. 2.13 Multiplier circuit (6) based on PR 2.3 – block diagram

IOUT1
IOUT2

V3
M2b M2a M2a’ M2b’
M1b M1a V4 M1a’ M1b’

M3b M3b’
M3a V1 V2 M3a’

Fig. 2.14 Multiplier circuit (7) based on PR 2.3

resulting:

IOUT1  IOUT2 ¼ K ðV1  V3 Þ ðV2  V4 Þ (2.86)

A voltage multiplier that illustrates the third mathematical principle PR 2.3 can
be implemented using the symmetrical structure presented in Fig. 2.14 [11].
The circuit is derived from the core shown in Fig. 2.15 [11].
For this circuit core, the ID1  ID2 differential output current can be com-
puted replacing the expressions of drain currents by their squaring dependencies
on the gate-source voltages (all MOS transistors are supposed to be biased in
saturation region).

K K
ID1  ID2 ¼ ðVGS1  VT Þ2  ðVGS3  VT Þ2 (2.87)
2 2
2.2 Analysis and Design of Multiplier Circuits 109

Fig. 2.15 The core of the

multiplier circuit (7) based on
PR 2.3 ID1 ID2

M2 V3
M1

M3 V1

The expression of the gate-source voltage of M1 transistor can be obtained using

the equality between the gate-source voltages (if M2 and M3 transistors are
identical and biased at the same drain current), resulting:

VGS1 ¼ V3  VGS2 ¼ V3  VGS3 ¼ V3  V1 (2.88)

Replacing (2.88) in (2.87), the expression of the output differential current for
the circuit presented in Fig. 2.14 can be expressed as follows:

K K
ID1  ID2 ¼ ðV3  V1  VT Þ2  ðV1  VT Þ2
2 2
K
¼ ðV3  2VT ÞðV 3  2V1 Þ ð2:89Þ
2

In order to implement a voltage multiplier circuit, two identical cores from

Fig. 2.15 have to be used (Fig. 2.16 [11]), the input voltages for each of them
being V1 and V3 and, respectively, V2 and V3 .
For simplifying the analysis of the circuit presented in Fig. 2.16, (2.89) relation
can be used, the differential output current of the circuit from Fig. 2.16 being,
practically, the difference between two differential output currents of two identical
cores, excited using different input voltages:
 0
IL  IR ¼ ID1 0 þ ID2  ðID2 þ ID1 0 Þ ¼ ðID1  ID2 Þ  ðID1 0  ID2 0 Þ (2.90)

Particularizing (2.89) relation for each circuit core, it results:

K K
IL  IR ¼ ðV3  2VT Þ ðV 3  2V1 Þ  ðV3  2VT Þ ðV 3  2V2 Þ
2 2
¼ K ðV2  V1 Þ ðV3  2VT Þ ð2:91Þ
110 2 Voltage and Current Multiplier Circuits

IL IR

V3
M2 M2’
M1 M1’

M3 V1 V2 M3’

Fig. 2.16 Half-circuit of the multiplier circuit (7) based on PR 2.3

So, for the voltage multiplier presented in Fig. 2.14, the expression of the
differential output current will be

IOUT1  IOUT2 ¼ ID1b þ ID2a þ ID1a 0 þ ID2b 0  ID2b  ID1a

 ID2a 0  ID1b 0 ¼ ½ðID1b  ID2b Þ  ðID1b 0  ID2b 0 Þ
 ½ðID1a  ID2a Þ  ðID1b 0  ID2a 0 Þ ¼ ðIL  IR Þa  ðIL  IR Þb
¼ K ðV2  V1 ÞðV4  2VT Þ  K ðV2  V1 ÞðV3  2VT Þ ¼ K ðV2  V1 ÞðV4  V3 Þ
(2.92)

A modified circuit that implements the multiplication of two differential input

voltages is presented in Fig. 2.17 [12] (a four-quadrant multiplier that does not
require balanced inputs).
The difference between the gate-source voltages of M2 and M9 transistors can
be expressed as follows:
rffiffiffiffi
2 pffiffiffiffi pffiffiffiffiffi
VGS2  VGS9 ¼ V4  V3 ¼ I2  IO (2.93)
K
It results
K pffiffiffiffiffiffiffiffiffiffi
I2 ¼ IO þ ðV4  V3 Þ2 þ 2KIO ðV4  V3 Þ (2.94)
2
Similarly, for M3–M5, M1–M4, M6–M9, M5–M7 and M1–M8 differential pairs,
the differences between their gate-source voltages have the following expressions:
rffiffiffiffi
2 pffiffiffiffi pffiffiffiffiffi
VGS3  VGS5 ¼ V3  V2 ¼ I3  IO (2.95)
K
2.2 Analysis and Design of Multiplier Circuits 111

VDD

IO
IOUT1 IOUT2

M4 V1 M8
M2 M3 V3 M6 M7 V4

V4 M1 V2 M5 M9 V3
I2 I3 I4 I6 I7 I8

- VDD

Fig. 2.17 Multiplier circuit (8) based on PR 2.3

rffiffiffiffi
2 pffiffiffiffi pffiffiffiffiffi
VGS4  VGS1 ¼ V1  V4 ¼ I4  IO (2.96)
K
rffiffiffiffi
2 pffiffiffiffi pffiffiffiffiffi
VGS6  VGS9 ¼ V1  V3 ¼ I6  IO (2.97)
K
rffiffiffiffi
2 pffiffiffiffi pffiffiffiffiffi
VGS7  VGS5 ¼ V 4  V2 ¼ I7  IO (2.98)
K

and
rffiffiffiffi
2 pffiffiffiffi pffiffiffiffiffi
VGS8  VGS1 ¼ V 3  V4 ¼ I8  IO (2.99)
K

resulting:

K pffiffiffiffiffiffiffiffiffiffi
I3 ¼ I O þ ðV3  V2 Þ2 þ 2KIO ðV3  V2 Þ (2.100)
2

K pffiffiffiffiffiffiffiffiffiffi
I4 ¼ IO þ ðV1  V4 Þ2 þ 2KIO ðV1  V4 Þ (2.101)
2

K pffiffiffiffiffiffiffiffiffiffi
I6 ¼ IO þ ðV1  V3 Þ2 þ 2KIO ðV1  V3 Þ (2.102)
2

K pffiffiffiffiffiffiffiffiffiffi
I7 ¼ IO þ ðV4  V2 Þ2 þ 2KIO ðV4  V2 Þ (2.103)
2
112 2 Voltage and Current Multiplier Circuits

Fig. 2.18 Multiplier circuit

CM
(1) based on PR 2.4 – general
block diagram IOUT

IOUT1 IOUT2

V1 V2
DA

IO

V3 V4
SQ

and

K pffiffiffiffiffiffiffiffiffiffi
I8 ¼ IO þ ðV3  V4 Þ2 þ 2KIO ðV3  V4 Þ (2.104)
2

The differential output current for the multiplier circuit presented in Fig. 2.17
will have the following expression:

IOUT ¼ IOUT1  IOUT2 ¼ I2 þ I3 þ I4  I6  I7  I8

¼ K ðV1  V2 ÞðV3  V4 Þ ð2:105Þ

2.2.1.4 Multiplier Circuits Based on the Fourth Mathematical

Principle (PR 2.4)

This class of multiplier circuits presents the important advantage of generating,

using the same circuit core, multiple circuit functions: amplifying, multiplying,
squaring or simulating both positive and negative equivalent resistances.
A method for designing a voltage multiplier using the fourth mathematical
principle (PR 2.4) is illustrated by the block diagram presented in Fig. 2.18,
the biasing current of the first differential amplifier (with V1  V2 differential
input voltage) being generated by a voltage squaring circuit having as input
another differential voltage V3  V4 . Supposing that the Gm transconductance of
the differential core is proportional with the square-root of the biasing current,
IO (an usual relation for a large class of differential amplifiers), the output current
of the multiplier circuit will be proportional with the product between the input
voltages of the differential amplifier and voltage squarer circuit.
2.2 Analysis and Design of Multiplier Circuits 113

Fig. 2.19 Multiplier circuit

CM
(1) based on PR 2.4 – block
diagram with SQ circuit IOUT
implementation
IOUT1 IOUT2

V1 V2
DA I

IO’

2IO

IOUT1’ IOUT2’

V3 V4
DA II

IO

The implementation of a voltage multiplier circuit can be simplified for a

particular realization of the differential amplifier, having the transfer characteristic
linearized using the method of constant sum of gate-source voltages. In this case,
the squarer circuit from Fig. 2.18 can be implemented using the same differential
amplifier, the sum of its output currents being proportional with the square of
the differential voltage applied on the input pins. The block diagram presented in
Fig. 2.18 can be re-drawn replacing the general voltage squarer with its particular
implementation based on a differential amplifier (Fig. 2.19). The IO current from
Fig. 2.18 has been replaced with a IO 0 current, linearly dependent on the output
current of a squaring circuit from Fig. 2.19, having as input the V3  V4 differential
voltage, as follows:

IO 0 ¼ IOUT1 0 þ IOUT2 0  2IO (2.106)

A possible realization of the differential amplifier linearized using the previous

principle is shown in Fig. 2.20 [13].
Considering a biasing in saturation of MOS transistors, the IOUT1 and IOUT2
output currents of the differential amplifier from Fig. 2.20 can be expressed as
follows:

K
IOUT1 ¼ ðVGS1  VT Þ2 (2.107)
2
114 2 Voltage and Current Multiplier Circuits

IOUT1 IOUT2

M1 M2
V1 IO IO V2

IOUT1 VO VO I
- + + - OUT2

IO IO
IO IO

Fig. 2.20 Multiplier circuit (1) based on PR 2.4 – principle implementation of DA block

K
IOUT2 ¼ ðVGS2  VT Þ2 (2.108)
2

The expression of the V1  V2 differential input voltage is

V1  V2 ¼ VO  VGS2 ¼ VGS1  VO (2.109)

resulting:

VGS1 ¼ VO þ ðV1  V2 Þ (2.110)

and

VGS2 ¼ VO  ðV1  V2 Þ (2.111)

Replacing (2.110) and (2.111) in (2.107) and (2.108), it results:

K
IOUT1 ¼ ½ðVO  VT Þ þ ðV1  V2 Þ2 (2.112)
2

and

K
IOUT2 ¼ ½ðVO  VT Þ  ðV1  V2 Þ2 (2.113)
2

So, the differential output current of the circuit presented in Fig. 2.20 will be

IOUT ¼ IOUT1  IOUT2 ¼ 2K ðVO  VT Þ ðV1  V2 Þ (2.114)

2.2 Analysis and Design of Multiplier Circuits 115

In the particular case of implementing each VO voltage source from Fig. 2.20
using a gate-source voltage of a MOS transistor biased in saturation region,
it results:
rffiffiffiffiffiffiffi
2IO
VO ¼ VT þ (2.115)
K

so
pffiffiffiffiffiffiffiffiffiffi
IOUT ¼ 8KIO ðV1  V2 Þ (2.116)

The sum of the output currents of the differential amplifier will have the
following expression:

IOUT1 þ IOUT2 ¼ K ðVO  VT Þ2 þ K ðV1  V2 Þ2 ¼ 2IO þ K ðV1  V2 Þ2 (2.117)

In conclusion, using in the block diagram of the voltage multiplier from Fig. 2.19
the particular implementation of the differential amplifier shown in Fig. 2.20, it is
possible to write:
pffiffiffiffiffiffiffiffiffiffiffiffi
IOUT ¼ IOUT1  IOUT2 ¼ 8KIO 0 ðV1  V2 Þ (2.118)

where IO 0 current is linearly dependent on the sum of the output currents of the
second differential amplifier:

IO 0 ¼ IOUT1 0 þ IOUT2 0  2IO ¼ K ðV3  V4 Þ2 (2.119)

Replacing (2.119) in (2.118), it results:

pffiffiffi
IOUT ¼ 8K ðV1  V2 Þ ðV3  V4 Þ (2.120)

The complete implementation of the principle illustrated in the block diagram

presented in Fig. 2.19 and the utilization of the method of realization shown in
Fig. 2.20 allows many possible configurations.
The differential amplifier presented in Fig. 2.21 [14] is realized using M1 and M2
transistors and implements the VO voltage sources from Fig. 2.20 using the gate-
source voltages of M3 and M5 transistors, biased at the same constant current, IO .
So, the differential output current of the differential structure from Fig. 2.21,
IOUT ¼ IOUT1  IOUT2 , will be expressed by (2.116).
The realization of the multiplier circuit based on the block diagram from Fig. 2.19,
using the differential amplifier presented in Fig. 2.21 [14] is shown in Fig. 2.22,
the expression of the output current of the voltage multiplier shown in Fig. 2.22 being
given by (2.120).
116 2 Voltage and Current Multiplier Circuits

VDD

M7 M8
IO IO
IOUT1 IO IOUT2

V1 M1 M3 M5 M2
V2
VO VO
IO+iO1 IO + iO2
M4 M6

-VDD

Fig. 2.21 Multiplier circuit (1) based on PR 2.4 – first implementation of DA block

VDD

IO’
I O’ IO’ IOUT
IOUT1 IOUT2
M1 M2 V2
V1

-VDD
VDD

2IO IO IO
IO
IOUT1’ IOUT2’
V3 M3 M4 V4

-VDD

Fig. 2.22 Complete circuit of the multiplier from Fig. 2.19 using the first implementation of
DA block
2.2 Analysis and Design of Multiplier Circuits 117

VDD

IO IO

IOUT1 IOUT2

M1 M2

M3
V1 M4 V2
VO VO

Fig. 2.23 Multiplier circuit (1) based on PR 2.4 – second implementation of DA block

The second possible implementation of the previous presented principle uses as

differential amplifier the circuit presented in Fig. 2.23 [14], the VO voltage sources
from Fig. 2.20 being realized using the gate-source voltages of M3 and M4
transistors, biased at the same constant current, IO , while the differential amplifier
is realized with M1 and M2 transistors. The output current of this differential
amplifier is expressed by (2.116).
The complete realization of the voltage multiplier is shown in Fig. 2.24,
the expression of its output current being given by (2.120).
The third implementation of a differential amplifier based on the principle
shown in Fig. 2.20 is presented in Fig. 2.25 [13, 15], the VO voltage sources from
Fig. 2.20 being realized using the gate-source voltages of M3 and M4 transistors,
biased at the same constant current, IO . The output current of this differential
amplifier (which is implemented using M1 and M2 transistors) is expressed
by (2.116). The disadvantage of this realization of the differential amplifier
comparing with the other proposals consists in a biasing of transistors M3 and
M4 at variable currents.
The complete realization of the voltage multiplier is shown in Fig. 2.26 [15],
the expression of its output current being also given by (2.120).
The fourth implementation of a differential amplifier based on the principle
shown in Fig. 2.20 is presented in Fig. 2.27 [16], the VO voltage sources from
Fig. 2.20 being realized using the gate-source voltages of M3a and M3b transistors,
biased at the same constant current IO (because I and I 0 currents are zero as a result
of the circuit configuration). The output current of this differential amplifier is
expressed by (2.116).
118 2 Voltage and Current Multiplier Circuits

VDD

IO’ IOUT IO’

IO’
IOUT1 IOUT2

V1 V2

-VDD

VDD

I O’
IO 2IO IO
IO
IOUT1’ IOUT2’

V3 V4

-VDD

Fig. 2.24 Complete circuit of the multiplier from Fig. 2.19 using the second implementation of
DA block

The fifth implementation of a differential amplifier based on the principle

shown in Fig. 2.20 is presented in Fig. 2.28 [17], the VO voltage sources from
Fig. 2.20 being realized using the gate-source voltages of M3 and M4 transistors,
biased at the same constant current, IO (because I and I0 currents are zero as a
result of the circuit configuration). The output current of this differential amplifier
(realized with M1 and M2 transistors) is expressed by (2.116).
 IOUT1 IOUT2

M1 M2 V2
V1

VO VO

M3 M4 IO

M5 M6 M7

Fig. 2.25 Multiplier circuit (1) based on PR 2.4 – third implementation of DA block

VDD

IOUT1 IOUT2 2IO IOUT1’ IOUT2’

M1 M2 V2 M3 M4 V4
V1 V3

IO’

M8 M9 M10 M11 IO

M5 M6 M7 M12 M13 M14

Fig. 2.26 Complete circuit of the multiplier from Fig. 2.19 using the third implementation of
DA block

VDD

M5a M6a M7a M7b M6b M5b

IOUT1 IOUT1 IOUT2 IOUT2

M1a M2a M3a M3b M2b M1b

V1 V2

IO IO
A I VO VO B
I’
IOUT1 2IOUT1 2IOUT1
2IOUT2 2IOUT2 IOUT2
IO IO
M10a M9a M8a M8b M9b M10b

Fig. 2.27 Multiplier circuit (1) based on PR 2.4 – fourth implementation of DA block
120 2 Voltage and Current Multiplier Circuits

VDD

IOUT1 IO IO IOUT2

V1 M1 M3 M4 M2 V2
VO VO

I
I’

IO IO

Fig. 2.28 Multiplier circuit (1) based on PR 2.4 – fifth implementation of DA block

ID1 ID1
IOUT1

M1 M2 V2
V1

M3

Fig. 2.29 The core of the multiplier circuit (2) based on PR 2.4

Both fourth and fifth implementations of voltage multipliers (derived from

differential amplifiers presented in Fig. 2.27 and Fig. 2.28) are based on the principle
illustrated in Fig. 2.19.
The core of another voltage multiplier using the fourth mathematical principle is
presented in Fig. 2.29 [18] and it is represented by a self-biased differential amplifier.
The V1  V2 differential input voltage of the multiplier core can be expressed as
a function of the difference between the gate-source voltages of M1 and M2
transistors:

V1  V2 ¼ VGS1  VGS2 (2.121)

2.2 Analysis and Design of Multiplier Circuits 121

Fig. 2.30 Replicated core of

the multiplier circuit (2) ID3 ID3
based on PR 2.4 IOUT2

M3 M4 V2
V1

M5

Replacing the square-root dependence of the gate-source voltage on the drain

current for a MOS transistor biased in saturation and considering identical
transistors, it results:
rffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffi
2ID1 2ID2
V1  V2 ¼  (2.122)
K K

equivalent with:
rffiffiffiffi
pffiffiffiffiffiffi pffiffiffiffiffiffi K
ID2 ¼ ID1  ðV1  V2 Þ (2.123)
2

Squaring the previous relation, it can be obtained that:

pffiffiffiffiffiffiffiffiffiffiffiffi K
ID2 ¼ ID1  2KID1 ðV1  V2 Þ þ ðV1  V2 Þ2 (2.124)
2

Thus, the output current of the differential core presented in Fig. 2.29, IOUT1 , will
have the following expression:

pffiffiffiffiffiffiffiffiffiffiffiffi K
IOUT1 ¼ ID2  ID1 ¼  2KID1 ðV1  V2 Þ þ ðV1  V2 Þ2 (2.125)
2

In order to implement the multiplying function, the first linear dependent on

the differential input voltage term from the previous relation will be used. The
same core permits to realize also the squaring function using the second term from
the same relation. The simplest way to remove the last quadratic term is to use a
similar structure with the circuit from Fig. 2.29 (presented in Fig. 2.30) [18]
and having the ID1 current replaced with another current, ID3 . As the quadratic
term from (2.125) does not depend on ID1 and ID3 currents, the consideration
122 2 Voltage and Current Multiplier Circuits

Fig. 2.31 Differential VDD

amplifier for generating ID3
and ID1 currents
V3 V4
M5 M6

ID3 ID1

of the difference between the output currents of these similar structures will
cancel out the undesired term.
Similarly with the previous analysis, the output current of the circuit from
Fig. 2.30 will have the following expression:

pffiffiffiffiffiffiffiffiffiffiffiffi K
IOUT2 ¼ ID4  ID3 ¼  2KID3 ðV1  V2 Þ þ ðV1  V2 Þ2 (2.126)
2

The difference between the output currents IOUT1 and IOUT2 will be
pffiffiffiffiffiffipffiffiffiffiffiffi pffiffiffiffiffiffi
IOUT ¼ IOUT1  IOUT2 ¼ 2K ID3  ID1 ðV1  V2 Þ (2.127)

The ID3 and ID1 currents are generated by another differential amplifier M5–M6,
having V3  V4 as differential input voltage (Fig. 2.31).
For this structure, considering that its composing transistors are biased in
saturation, it is possible to write:
rffiffiffiffi rffiffiffiffi
pffiffiffiffiffiffi pffiffiffiffiffiffi K K
ID3  ID1 ¼ ½ðVDD  V3  VT Þ  ðVDD  V4  VT Þ ¼ ðV4  V3 Þ (2.128)
2 2

Replacing (2.128) in (2.127) it results the multiplying function:

IOUT ¼ K ðV1  V2 Þ ðV4  V3 Þ (2.129)

The complete circuit of the multiplier is presented in Fig. 2.32 [18]. The differen-
tial amplifier from Fig. 2.31 is replaced with two parallel-connected differential
amplifiers M5, M50 –M6, M60 because ID1 and ID3 currents must be duplicated for
biasing the differential amplifiers, M1–M2 and M3–M4.
Another possible implementation of a voltage multiplier uses the symmetrical
structure presented in Fig. 2.33.
The multiplier is composed from two self-biased differential amplifiers
(M5–M6 and M8–M9, respectively), their active loads being represented by
2.2 Analysis and Design of Multiplier Circuits 123

VDD

V4 V3
M6 M6’ M5’ M5 M7 M8
ID1 ID3 ID3 IOUT2 IOUT1
ID1
IOUT
IOUT1

V1 M3 M1 M2 M4
V2

Fig. 2.32 The complete implementation of the multiplier circuit (2) based on PR 2.4

VDD

M7 M10

V4
V3 V3
M5 M6 M9 M8
IOUT1 IOUT IOUT2

V1 M11 M12 V2
M1 M2 M3 M4

-VDD

Fig. 2.33 Multiplier circuit (3) based on PR 2.4

M1–M2 and M3–M4 current mirrors. Analyzing the M5–M6 differential amplifier,
the V3  V4 differential voltage can be expressed as a difference between two gate-
source voltages:

V3  V4 ¼ VSG6  VSG5 (2.130)

Replacing the square-root dependence of the gate-source voltage on the drain

current for a MOS transistor biased in saturation and considering identical
transistors, it results:
rffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffi
2ID6 2ID1
V3  V4 ¼  (2.131)
K K
124 2 Voltage and Current Multiplier Circuits

The ID6 current can be expressed from the previous relation as follows:
rffiffiffiffi
pffiffiffiffiffiffi pffiffiffiffiffiffi K
ID6 ¼ ID1 þ ðV3  V4 Þ (2.132)
2

resulting:

pffiffiffiffiffiffiffiffiffiffiffiffi K
ID6 ¼ ID1 þ 2KID1 ðV3  V4 Þ þ ðV3  V4 Þ2 (2.133)
2

The differential output current of the M5–M6 differential amplifier will be:

pffiffiffiffiffiffiffiffiffiffiffiffi K
IOUT1 ¼ ID6  ID1 ¼ 2KID1 ðV3  V4 Þ þ ðV3  V4 Þ2 (2.134)
2

Similarly, the differential output current of the M8–M9 differential amplifier

will have the following expression:

pffiffiffiffiffiffiffiffiffiffiffiffi K
IOUT2 ¼ 2KID4 ðV3  V4 Þ þ ðV3  V4 Þ2 (2.135)
2

The M11–M12 current mirror computes the IOUT output current of the entire
multiplier structure from Fig. 2.33:
pffiffiffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffi
IOUT ¼ IOUT2  IOUT1 ¼ 2K ðV3  V4 Þ ID4  ID1 (2.136)

Using the squaring dependence of the drain current on the gate-source voltage
for a MOS transistor biased in saturation, it is possible to write:
"rffiffiffiffi rffiffiffiffi #
pffiffiffiffiffiffi K K
IOUT ¼ 2K ðV3  V4 Þ ðV2 þ VDD  VT Þ  ðV1 þ VDD  VT Þ
2 2 (2.137)
¼ KðV3  V4 ÞðV2  V1 Þ

A voltage multiplier based on the compensation of the squaring characteristic

of the MOS transistor biased in saturation region using two square-root circuits is
presented in Fig. 2.34 [19].
The differential input voltage can be expressed as follows:
rffiffiffiffi
2 pffiffiffiffi pffiffiffiffiffi0 
V1  V2 ¼ VGS3  VGS4 ¼ I 2  I2 (2.138)
K
2.2 Analysis and Design of Multiplier Circuits 125

VDD

M5 M6

M9 M10
I1 I2 IOUT1
I2 I1 I2 I1 I1’ I2' IOUT2
V3 M2 M1 V4 M3 M7 M8 M4
V1 V2

IO IO IO

Fig. 2.34 Multiplier circuit (4) based on PR 2.4

resulting:

K pffiffiffiffiffiffi pffiffiffiffi
I2 0 ¼ I2 þ ðV1  V2 Þ2  2K ðV1  V2 Þ I2 (2.139)
2

The output current of the square-rooting circuit is:

K pffiffiffiffiffiffi pffiffiffiffi
IOUT2 ¼ I2  I2 0 ¼  ðV1  V2 Þ2 þ 2K ðV1  V2 Þ I2 (2.140)
2

Similarly:

K pffiffiffiffiffiffi pffiffiffiffi
IOUT1 ¼ I1  I1 0 ¼  ðV1  V2 Þ2 þ 2K ðV1  V2 Þ I1 (2.141)
2

so:
pffiffiffiffiffiffi pffiffiffiffi pffiffiffiffi
IOUT ¼ IOUT2  IOUT1 ¼ 2K ðV1  V2 Þ I2  I1 (2.142)

The differential input voltage of M1–M2 differential amplifier will have the
following expression:
rffiffiffiffi
2 pffiffiffiffi pffiffiffiffi
V3  V4 ¼ VGS2  VGS1 ¼ I2  I1 (2.143)
K
126 2 Voltage and Current Multiplier Circuits

V1 M V2

IO IO
T T
V
V1T V2T
DA

IOUT

V3 SQ V4

Fig. 2.35 Multiplier circuit (5) based on PR 2.4 – block diagram

resulting:

IOUT ¼ K ðV1  V2 Þ ðV3  V4 Þ (2.144)

A possible implementation of a voltage multiplier has the block diagram

presented in Fig. 2.35. The “DA” block represents a classical active-load differ-
ential amplifier, having the common-sources point biased at a V potential fixed by
the circuit “M”. This circuit computes the arithmetical mean of input potentials,
having the goal of obtaining a very good linearity of the entire structure, with the
contribution of “T” blocks (which are used for introducing a translation of input
potentials). A squaring circuit, “SQ”, is used for generating the biasing current of
the two translation blocks, IO .

The “DA” (Differential Amplifier) block

The “DA” block is implemented as a classical active-load differential amplifier,

having the concrete realization presented in Fig. 2.36 [20].
Considering a biasing in saturation of the MOS devices from Fig. 2.36, the output
current of the differential amplifier can be expressed as follows:

K K
IOUT ¼ I2  I1 ¼ ðVSG2  VT Þ2  ðVSG1  VT Þ2 (2.145)
2 2
2.2 Analysis and Design of Multiplier Circuits 127

Fig. 2.36 Multiplier circuit V

(5) based on PR 2.4 –
implementation of DA block

V1T V2T
M1 M2
I1 I2 IOUT

M3 M4

equivalent with:

K
IOUT ¼ ðVSG2  VSG1 Þ ðVSG1 þ VSG2  2VT Þ (2.146)
2

Because:

VSG1 ¼ V  V1T (2.147)

and:

VSG2 ¼ V  V2T (2.148)

it results:

K
IOUT ¼ ðV1T  V2T Þ ð2V  V1T  V2T  2VT Þ (2.149)
2

In order to obtain a linear transfer characteristic IOUT ðV1T  V2T Þ, it is necessary

that the second parenthesis from (2.149) to be constant with respect to the differen-
tial input voltage, V1T  V2T :

2V  V1T  V2T  2VT ¼ A ¼ ct: (2.150)

resulting the necessity of implementing a V voltage equal with:

V1T þ V2T A
V¼ þ VT þ (2.151)
2 2
128 2 Voltage and Current Multiplier Circuits

Fig. 2.37 Multiplier circuit

(5) based on PR 2.4 –
implementation of T block IO IO

M9 M9’
V1 V2

V1T V2T

The “T” (Translation) Block

The translation of the V potential by VT þ A=2 (relation (2.151)) can be obtained

using “T” block, having the implementation presented in Fig. 2.37 [20].
Because the same IO current is passing through all transistors from Fig. 2.37, it is
possible to write that:
rffiffiffiffiffiffiffi
2IO
V1 ¼ V1T þ VT þ (2.152)
K

and:
rffiffiffiffiffiffiffi
2IO
V2 ¼ V2T þ VT þ (2.153)
K

So, both V1 and V2 input potentials are DC shifted with the same amount,
pffiffiffiffiffiffiffiffiffiffiffiffiffi
VT þ 2IO =K .

The “M” (Arithmetic Mean) Block

In order to obtain the arithmetic mean of input potentials expressed by relation

(2.151), the circuit from Fig. 2.38 [20] can be used, having the advantage of using
only MOS transistors, biased in saturation region.
The expression of the V potential is:

V1 þ V2
V¼ (2.154)
2

Replacing (2.152) and (2.153) in (2.156), it can be obtained:

rffiffiffiffiffiffiffi
V1T þ V2T 2IO
V¼ þ VT þ (2.155)
2 K
2.2 Analysis and Design of Multiplier Circuits 129

IO /2 IO /2

V1 M14 M15 M15’ M14’ V2

IO IO
V

Fig. 2.38 Multiplier circuit (1) based on PR 2.4 – implementation of M block

pffiffiffiffiffiffiffiffiffiffiffiffiffi
Comparing relations (2.151) and (2.157), it results that A ¼ 2 2IO =K , so:
rffiffiffiffiffiffiffi
K 2IO
IOUT ¼ ðV1T  V2T Þ2 (2.156)
2 K

or:
pffiffiffiffiffiffiffiffiffiffi
IOUT ¼ 2KIO ðV1T  V2T Þ (2.157)

equivalently (using (2.152) and (2.153)) with:

pffiffiffiffiffiffiffiffiffiffi
IOUT ¼ 2KIO ðV1  V2 Þ ¼ Gm ðV1  V2 Þ (2.158)

resulting:
pffiffiffiffiffiffiffiffiffiffi
IOUT ¼ 2KIO ðV1  V2 Þ ¼ Gm ðV1  V2 Þ (2.159)
pffiffiffiffiffiffiffiffiffiffi
Gm ¼ 2KIO being the equivalent transconductance of the differential
amplifier.
Because IO biasing currents of the translation blocks “T” from Fig. 2.37 are
generated by a voltage squaring circuit having as input a differential voltage,
V3  V4 , it results a multiplier circuit with a very good linearity. So, replacing in
(2.159) the expression of IO current:

K
IO ¼ ðV3  V4 Þ2 (2.160)
4

it results:

K
IOUT ¼ pffiffiffi ðV1  V2 Þ ðV3  V4 Þ (2.161)
2
130 2 Voltage and Current Multiplier Circuits

Fig. 2.39 Multiplier circuit

(1) based on PR 2.5 IOUT1 IOUT2

M3 M4 M5 M6
V1

IO IO
M1 M2

V2

ISS

2.2.1.5 Multiplier Circuits Based on the Fifth Mathematical

Principle (PR 2.5)

A method for linearizing the characteristic of a voltage multiplier using the

fifth mathematical principle consists in the extension of the linearization tech-
nique designed for the CMOS differential amplifier, based on the biasing of the
differential structure at a current that is the sum between a constant current and a
component proportional with the square of the differential input voltage. The
relatively simple implementation of multiplier circuits based on this mathematical
principle impose them for a large area of applications in VLSI designs.
The expression of the differential output current of the classical CMOS differen-
tial amplifier is:

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
ISS VI2
IOUT ¼ KVI  (2.162)
K 4

VI representing the differential input voltage and ISS being the biasing current of
the differential amplifier.
The multiplier with linear characteristic based on the previous presented
principle is presented in Fig. 2.39 [21].
2.2 Analysis and Design of Multiplier Circuits 131

The output current of the previous voltage multiplier can be expressed as:

IOUT ¼ IOUT1  IOUT2 ¼ ðID3 þ ID5 Þ  ðID4 þ ID6 Þ

¼ ðID3  ID4 Þ  ðID6  ID5 Þ (2.163)

The differential output currents of the differential amplifiers M3–M4 and

M5–M6 can be obtained using the general relation (2.162):
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
ID1 þ IO V12
ID3  ID4 ¼ KV1  (2.164)
K 4

and:
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
ID2 þ IO V12
ID6  ID5 ¼ K V1  (2.165)
K 4

The linearization technique is based on the utilization of a current IO propor-

tional with the squaring of the differential input voltage V1 :

KV12
IO ¼ (2.166)
4

Replacing (2.164), (2.165) and (2.166) in (2.163), it results the following

expression of the output current of the voltage multiplier:
pffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffi
IOUT ¼ K V1 ID1  ID2 (2.167)

Analyzing M1–M2 differential amplifier, the V2 differential input voltage can be

expressed as follows:

rffiffiffiffiffiffiffiffiffi! rffiffiffiffiffiffiffiffiffi!
2ID1 2ID2
V2 ¼ VGS1  VGS2 ¼ VT þ  VT þ
K K
rffiffiffiffi
2 pffiffiffiffiffiffi pffiffiffiffiffiffi
¼ ID1  ID2 (2.168)
K

From (2.168) and (2.167), it results the expression of the IOUT output current as a
function on the differential input voltages, V1 and V2 :

K
IOUT ¼ pffiffiffi V1 V2 (2.169)
2
132 2 Voltage and Current Multiplier Circuits

A similar method, useful for low-voltage operation, is presented in Fig. 40 [21].

In order to reduce the minimal value of the supply voltage, the stacked architecture
is replaced with a folded structure.
The IOUT1  IOUT2 differential output current of the folded voltage multiplier is:

IOUT1  IOUT2 ¼ ðID3 þ ID5 Þ  ðID4 þ ID6 Þ

(2.170)
¼ ðID3  ID4 Þ  ðID6  ID5 Þ

The differential output currents of the differential amplifiers M3–M4 and

M5–M6 can be obtained using the general relation (2.162):
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
ISS þ IO  ID1 V12
ID3  ID4 ¼ KV1  (2.171)
K 4

and:
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
ISS þ IO  ID2 V12
ID6  ID5 ¼ KV1  (2.172)
K 4

The linearization technique is based on the utilization of a IO current, propor-

tional with the square of the differential input voltage V1 :

KV12
IO ¼ (2.173)
4

Replacing (2.171), (2.172) and (2.173) in (2.170), it results the following

expression of the output current of the voltage multiplier:

pffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

IOUT ¼ K V1 ISS  ID1  ISS  ID2 (2.174)

The M1–M2 differential amplifier is biased at the constant current, ISS , so

ID1 þ ID2 ¼ ISS . The previous relation can be rewritten as:
pffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffi
IOUT ¼ K V1 ID2  ID1 (2.175)

Similarly with the previous voltage multiplier, it results the following expression
of the IOUT output current as a function on V1 and V2 differential input voltages:

K
IOUT ¼ pffiffiffi V1 V2 (2.176)
2
2.2 Analysis and Design of Multiplier Circuits 133

VDD

ISS IOUT2
IOUT1

M1 M2 M3 M4 M5 M6
V2
V1

IO ISS IO ISS

Fig. 2.40 Multiplier circuit (1) based on PR 2.5 – circuit core of the folded version

VDD

M2 M4 M6 M8 M12 M14

M1 M3 M5 M7 M11 M13
IOUT1 IOUT2
ISS’
ISQ

MQ5 MQ1 MQ3

V2 MQ6 MQ2 MQ4 MS1
V1A
M9 MS2

ΔV V1
V1B
ISQ ISQ M10
MS3 M15
VC1 M19 M17
MS4

M20 M18 M16

Fig. 2.41 Multiplier circuit (1) based on PR 2.5 – complete implementation of the folded version

The complete implementation of the folded voltage multiplier from Fig. 2.40 is
presented in Fig. 2.41 [21].
The M1 and M2 transistors from Fig. 2.40 have been replaced in Fig. 2.41 with
MQ5 and MQ6, while the differential amplifiers, M3–M4 and M5–M6 from Fig. 2.40
were renamed MQ1–MQ2 and MQ3–MQ4, respectively. Noting with ISQ the drain
134 2 Voltage and Current Multiplier Circuits

currents of transistors M11–M20 and considering that the cascode current mirrors
implemented using M11–M20 transistors are not affected by the channel-length
modulation, the ISQ current will have the following expression:

ISQ ¼ IDMS1 þ IDMS2 (2.177)

For simplifying the computations, the differential input voltage V1 ¼ V1A  V1B ,
can be expressed using a linear relation between the common-mode and the
differential-mode input voltages, VC1 and v1 :

v1
V1A ¼ VC1  (2.178)
2

and:

v1
V1B ¼ VC1 þ (2.179)
2

Using this expression of V1 voltage, the ISQ current can be expressed as follows:

K K
ISQ ¼ ðV1A  VT Þ2 þ ðV1B  VT Þ2
2 2
K v1 2 K  v1 2
¼ VC1   VT þ VC1 þ  VT (2.180)
2 2 2 2

resulting:

K 2
ISQ ¼ K ðVC1  VT Þ2 þ v (2.181)
4 1

Comparing Fig. 2.40 with Fig. 2.41, it results that ISQ current from Fig. 2.41 must
be equal with a sum between a constant current, ISS and a IO current, proportional
with the squaring of the input voltage:

ISS ¼ K ðVC1  VT Þ2 (2.182)

and:

K 2
IO ¼ v (2.183)
4 1

For a proper operation of the folded multiplier, the ISS 0 biasing current of
the differential amplifier MQ5–MQ6 must be equal with ISS . This ISS 0 current is
2.2 Analysis and Design of Multiplier Circuits 135

IO /2 IO /2

V1A T14 T15 T15’ T14’ V1B

IO IO
VO

Fig. 2.42 Arithmetical mean circuit

generated by the MS3–MS4 pair, each transistor being biased at the common-mode
component of the input voltage V1 :

ISS 0 ¼ IDMS3 þ IDMS4 (2.184)

resulting:

K
ISS 0 ¼ 2 ðVC1  VT Þ2 ¼ K ðVC1  VT Þ2 ¼ ISS (2.185)
2

The M9 and M10 transistors are used for transferring the differential input
voltage, V1 , on the input of cross-connected differential amplifiers MQ1–MQ2
and MQ3–MQ4:

DV ¼ ðV1B þ VSG9 Þ  ðV1A þ VSG10 Þ (2.186)

The M9 and M10 transistors being identical and working at the same drain
current, it results VSG9 ¼ VSG10 . So:

DV ¼ V1B  V1A ¼ V1 (2.187)

Concluding that the circuits presented in Fig. 2.40 and Fig. 2.41 are functionally
identical, the IOUT output current of the complete implementation of the folded
voltage multiplier circuit can be obtained replacing in (2.176) V1 with  V1 :

K
IOUT ¼ IOUT1  IOUT2 ¼  pffiffiffi V1 V2 (2.188)
2

An arithmetical mean circuit (Fig. 2.42) [22] must be used for extracting the
common-mode component VC1 of the input voltage V1 .
The VO output voltage for this circuit will be:

V1A þ V1B
VO ¼ ¼ VC1 (2.189)
2
136 2 Voltage and Current Multiplier Circuits

Fig. 2.43 Multiplier circuit

(2) based on PR 2.5 IOUT1 IOUT2

V1 V2

IO
I34 I12

SQ II

V3 SQ I V4

The voltage multiplier presented in Fig. 2.43 [23], using the fifth mathematical
principle (PR 2.5) is derived from a differential amplifier with linear transfer
characteristic.
The differential output current, IOUT , for the circuit presented in Fig. 2.43 will
present a strong nonlinear dependence on the V1  V2 differential input voltage,
that can be expressed as:
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
KðV1  V2 Þ2 K 2 ðV1  V2 Þ4
IOUT ¼ IOUT1  IOUT2 ¼ IO  (2.190)
IO 4IO 2

equivalent with:
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
V1  V2
IOUT ¼ 4KIO  K 2 ðV1  V2 Þ2 (2.191)
2

IO being the biasing current of the differential structure. So, superior-order

distortions will characterize the behavior of this structure, imposing the design
of a linearization technique for removing the superior-order terms from the transfer
characteristic. The method for obtaining a linear transfer characteristic is to obtain
the IO bias current of the entire differential structure as a sum of two terms: I12 ,
proportional with the squaring of the V1  V2 differential input voltage and
I34 , proportional with the squaring of another differential voltage, V3  V4 :

K K
IO ¼ I12 þ I34 ¼ ðV1  V2 Þ2 þ ðV3  V4 Þ2 (2.192)
4 4
2.2 Analysis and Design of Multiplier Circuits 137

VDD

IOUT
M1a M2a
V1 V2

I3 I4 I1 I2
M1b M1c M2c
M2b 2VT

Fig. 2.44 Multiplier circuit (1) based on PR 2.6

resulting, in this case, a perfect proportionality of the output current on the

differential input voltages:

K
IOUT ¼ ðV1  V2 Þ ðV3  V4 Þ (2.193)
2

2.2.1.6 Multiplier Circuits Based on the Sixth Mathematical

Principles (PR 2.6)

The area of applications of multiplier structures based on PR 2.6 is restricted to the

circuits that do not require the multiplication of differential input voltages.
The following voltage multiplier circuit is based on the sixth mathematical
principle. In order to obtain a linear characteristic of the circuit, a perfect
symmetrical structure with respect to the two input potentials is presented in
Fig. 2.44 [24, 25].
Considering an operation in saturation for all MOS devices, the output current
can be expressed as:

IOUT ¼ ðI1 þ I2 Þ  ðI3 þ I4 Þ (2.194)

where:
 2
K V1 þ V2
I1 ¼  VT (2.195)
2 2
K 2
I2 ¼ V (2.196)
2 T
 2
K V1
I3 ¼  VT (2.197)
2 2
138 2 Voltage and Current Multiplier Circuits

VDD

IOUT

V2
M1 M2 M3 M4
V1

Fig. 2.45 Multiplier circuit (2) based on PR 2.6

 2
K V2
I4 ¼  VT (2.198)
2 2

For the previous mathematical relations, it results a perfect linear dependence of

the output current on the input voltages:

K
IOUT ¼ V1 V2 (2.199)
2

Another possible implementation of a voltage multiplier circuit using the sixth

mathematical principle (PR 2.6) is presented in Fig. 2.45.
The output current of the voltage multiplier can be expressed as follows:

IOUT ¼ ðID1 þ ID2 Þ  ðID3 þ ID4 Þ (2.200)

where:
 2
K V1 þ V2
ID1 ¼  VT (2.201)
2 2

K 2
ID2 ¼ V (2.202)
2 T
 2
K V1
ID3 ¼  VT (2.203)
2 2
 2
K V2
ID4 ¼  VT (2.204)
2 2
2.2 Analysis and Design of Multiplier Circuits 139

V1 SQ I V2 V1 SQ II -V2

IOUT1 IOUT2 IOUT

CM

Fig. 2.46 Multiplier circuit (1) based on PR 2.7 – block diagram

From the previous mathematical relations it results a perfect linear dependence

of the output current on the input voltages:

K
IOUT ¼ V1 V2 (2.205)
2

2.2.1.7 Multiplier Circuits Based on the Seventh Mathematical

Principles (PR 2.7)

Practically derived from the implementation of voltage squaring circuits, the

multiplier structures that use as functional basis PR 2.7 find many applications in
analog signal processing.
A similar approach of a voltage multiplier uses 2 v squaring circuit, connected as
it is shown in Fig. 2.46.
Considering that the squaring circuits have an output current proportional with
KDV 2 =2, DV being the differential input voltage, the output current of the circuit
presented in Fig. 2.46 will have the following expression:

K K
IOUT ¼ IOUT2  IOUT1 ¼ ðV1 þ V2 Þ2  ðV1  V2 Þ2 ¼ 2KV1 V2 (2.206)
2 2

In order to obtain the multiplying function using two squaring circuits, a similar
method is proposed in Fig. 2.47. The squaring circuits from Fig. 2.46 have been
replaced in Fig. 2.47 with two particular implementations of a differential amplifier
(presented in Fig. 2.20).
The implementation of the voltage multiplier is shown in Fig. 2.28 [13].
The IOUT output current will have the following expression:
h i h i
IOUT ¼ 2IO þ K ðV1 þ V2 Þ2  2IO þ K ðV1  V2 Þ2 ¼ 4KV1 V2 (2.207)
140 2 Voltage and Current Multiplier Circuits

CM
IOUT

V1 DA I -V2 V1 DA II V2

IO IO

Fig. 2.47 Multiplier circuit (2) based on PR 2.7 – block diagram

Two complete realizations of the previous circuit, using specific

implementations of VO sources from Fig. 2.48, are shown in Fig. 2.49 [13] and
Fig. 2.50 [13], respectively.
A multiplier circuit can be designed starting from a squaring characteristic
implemented using a classical differential amplifier (Fig. 2.51) [18].
The differential input voltage for the circuit presented in Fig. 2.51 can be
expressed as follows:

rffiffiffiffi
2 pffiffi pffiffiffiffiffi
V1  V2 ¼ I  IO (2.208)
K

resulting:

K pffiffiffiffiffiffiffiffiffiffi
I ¼ IO þ ðV1  V2 Þ2 þ 2KIO ðV1  V2 Þ (2.209)
2

In order to obtain the multiplying function, four differential amplifiers from

Fig. 2.51 can be connected as it is shown in Fig. 2.52.
The output current of the multiplier circuit will have the following expression:

IOUT ¼ I1 þ I2  I3  I4 (2.210)

resulting:

K K
ðV1  V2 Þ2 þ ðV1 þ V2 Þ2
IOUT ¼
2 2
K K
 ðV1 þ V2 Þ  ðV1  V2 Þ2 ¼ 4KV1 V2
2
(2.211)
2 2
2.2 Analysis and Design of Multiplier Circuits 141

CM

IOUT1 IOUT2

M1 M2 -V2
V1 IO IO

IOUT1 VO VO IOUT2
- + + -

IO IO
IO IO

IOUT

I OUT1’ IOUT2’

M3 M4
V1 IO IO V2

IOUT1’ V- O + +
VO
-
IOUT2’

IO IO
IO IO

Fig. 2.48 Multiplier circuit (2) based on PR 2.7 – principle implementation

VDD

IOUT
IO
IOUT1 IOUT2 IOUT1’ IOUT2’
V1 -V2 V1 V2

-VDD

Fig. 2.49 Multiplier circuit (2) based on PR 2.7 – first implementation

The circuit presented in Fig. 2.53 [12] represents a four-quadrant multiplier with
balanced inputs.
The difference between the gate-source voltages of M1 and M3 transistors can
be expressed as follows:

V1  V2 ¼ VGS1  VGS3 (2.212)

142 2 Voltage and Current Multiplier Circuits

VDD

IO
IOUT

IOUT1 IOUT2 IOUT1’ IOUT2’

-V2 V1 V2
V1

-VDD

Fig. 2.50 Multiplier circuit (2) based on PR 2.7 – second implementation

a b

I IO

I IO
V1 V2

I + IO V1 DA V2

Fig. 2.51 Multiplier circuit (3) based on PR 2.7 – circuit core

CM

IOUT

I1 IO I2 IO I3 IO I4 IO
- V1 V2 V1 -V2 - V1 - V2 V1 V2
DA I DA II DA III DA IV

Fig. 2.52 Multiplier circuit (3) based on PR 2.7 – block diagram

For a biasing in saturation of all MOS transistors from Fig. 2.53, it results:
rffiffiffiffi
2 pffiffiffiffi pffiffiffiffiffi
V1  V2 ¼ I 1  IO (2.213)
K
2.2 Analysis and Design of Multiplier Circuits 143

VDD

IOUT2 IOUT1

I1 I2 I4 I5

V1 M1 V2 M3 M2 M4 - V2 M6 M5 V1

- V1
IO

- VDD

Fig. 2.53 Multiplier circuit (4) based on PR 2.7

So, the expression of I1 current will be:

K pffiffiffiffiffiffiffiffiffiffi
I1 ¼ IO þ ðV1  V2 Þ2 þ 2KIO ðV1  V2 Þ (2.214)
2
Similarly, computing the difference between the gate-source voltages of M2–M3
transistors, it results:

K pffiffiffiffiffiffiffiffiffiffi
I2 ¼ IO þ ðV1  V2 Þ2 þ 2KIO ðV1  V2 Þ (2.215)
2
The I1  I2 differential current will have the following expression:
pffiffiffiffiffiffiffiffiffiffi
I1  I2 ¼ 2V1 2KIO  2KV1 V2 (2.216)

Similarly, for the structure implemented using M4–M6 transistors, the differen-
tial output current can be expressed as follows:
pffiffiffiffiffiffiffiffiffiffi
I4  I5 ¼ 2V1 2KIO  2KV1 V2 (2.217)

The differential output current for the entire multiplier structure presented in
Fig. 2.53 will be:

IOUT ¼ IOUT1  IOUT2 ¼ I2 þ I5  I1  I4 ¼ 4KV1 V2 (2.218)

2.2.1.8 Multiplier Circuits Based on Different Mathematical

Principles (PR 2.Da)

Alternate implementations of the previous presented multiplier circuits are based on

different mathematical principles. The utilization of the bulk as an active terminal
144 2 Voltage and Current Multiplier Circuits

Fig. 2.54 Multiplier circuit

(1) based on PR 2.Da – circuit IL V3 IR
core

V1 V2

gives the possibility of reducing the complexity of a multiplier circuit. The core of
the following presented multiplier is presented in Fig. 2.54 [11].
A model of the MOS transistor biased in saturation that includes the dependence
of the drain current on the bulk-source voltage is expressed by the following relation:
K 2 2

ID ¼ VGS  VT  AVBS  BVBS (2.219)
2
A and B being constants. The differential output current of the multiplier core
from Fig. 2.54, IL  IR , will be:

K 2 K  2
IL  IR ¼ V1  VT  AV3  BV32  V2  VT  AV3  BV32 (2.220)
2 2

resulting:

K  
IL  IR ¼ ðV1  V2 Þ V1 þ V2  2VT  2AV3  2BV32 (2.221)
2

In order to obtain the multiplying function, two circuits from Fig. 2.54 can be
cross-connected, resulting the multiplier presented in Fig. 2.55 [11].
For this circuit, the differential output current can be expressed as the difference
between the differential output currents of each core:

IOUT1  IOUT2 ¼ ðIL2 þ IR1 Þ  ðIL1 þ IR2 Þ ¼ ðIL2  IR2 Þ  ðIL1  IR1 Þ (2.222)

Replacing (2.221) in (2.222), it results:

K  
IOUT1  IOUT2 ¼ ðV1  V2 Þ V1 þ V2  2VT  2AV4  2BV42
2
K  
 ðV1  V2 Þ V1 þ V2  2VT  2AV3  2BV32 (2.223)
2

equivalent with:
 
IOUT1  IOUT2 ¼ K ðV1  V2 Þ AðV3  V4 Þ þ B V32  V42
¼ K ðV1  V2 ÞðV3  V4 Þ½A þ BðV3 þ V4 Þ (2.224)
2.2 Analysis and Design of Multiplier Circuits 145

IOUT1 IOUT2

IL1 V3 IR1 IL2 V4 IR2

V1 V2

Fig. 2.55 Multiplier circuit (1) based on PR 2.Da – complete implementation

If the V1 , V2 , V3 and V4 input voltages contain common-mode terms (V12 and V34 )
and differential-mode terms (v12 and v34 ) as follows:
v12
V1 ¼ V12 þ (2.225)
2
v12
V2 ¼ V12  (2.226)
2
v34
V3 ¼ V34 þ (2.227)
2
v34
V4 ¼ V34  (2.228)
2

it results:

IOUT1  IOUT2 ¼ Kv12 v34 ðA þ 2BV34 Þ (2.229)

so, the differential output current of the voltage multiplier presented in Fig. 2.55
will be proportional with the product of the differential-mode components of
input voltages.
An alternate approach of a voltage multiplier, based on bulk-driven MOS
devices using another model for the dependence of the threshold voltage VT on
the biasing of the bulk (VBS ), is shown in Fig. 2.56 [26].
The differential output current of this multiplier can be expressed as follows:

IOUT1  IOUT2 ¼ ðID1 þ ID3 Þ  ðID2 þ ID4 Þ ¼ ðID1  ID2 Þ þ ðID3  ID4 Þ (2.230)

where it is considered that the drain current of a MOS transistor depends on the
gate-source voltage following a quadratic law (2.231) and on the bulk-source
voltage as a consequence of the bulk effect using the mathematical relation (2.232):

K
ID ¼ ðVGS  VT Þ2 (2.231)
2
146 2 Voltage and Current Multiplier Circuits

IOUT1 IOUT2

V3 V4
V2
M1 M2 M3 M4
V1 V1

Fig. 2.56 Multiplier circuit (2) based on PR 2.Da

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffi
VT ¼ VT0 þ g 2FF  VBS  2FF (2.232)

VT being the threshold voltage of the MOS transistor biased at a bulk-source

voltage equal with VBS , g is a model parameter and FF represents the
Fermi potential. Replacing (2.232) in (2.231) and using the fact that VT1 ¼ VT2
and VT3 ¼ VT4 (because VBS1 ¼ VBS2 ¼ V3 and VBS3 ¼ VBS4 ¼ V4 ), it results the
following expression of the output current:

K K
IOUT1  IOUT2 ¼ ðV1  V2 Þ ðV1 þ V2  2VT1 Þ þ ðV2  V1 Þ ðV1 þ V2  2VT3 Þ
2 2
(2.233)

so:

IOUT1  IOUT2 ¼ K ðV1  V2 Þ ðVT3  VT1 Þ (2.234)

Using the (2.232) relation that models the bulk effect, the previous expression of
the output current can be rewritten as follows:
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
IOUT1  IOUT2 ¼ K ðV1  V2 Þg 2FF  V4  2FF  V3
r ffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
pffiffiffiffiffiffiffiffiffi V4 V3
¼ K ðV1  V2 Þg 2FF 1  1 (2.235)
2FF 2FF

For V3 and V4 input signals much smaller than theffi Fermi potential, it is
pffiffiffiffiffiffiffiffiffiffi
possible to use the first-order Taylor expansion 1 þ x ffi 1 þ x=2, for x<<1,
the expression of the output current becoming proportional with the product
between the differential input voltages:
 
pffiffiffiffiffiffiffiffiffi V3 V4
IOUT1  IOUT2 ¼ K ðV1  V2 Þg 2FF 
4FF 4FF
gK
¼ pffiffiffiffiffiffiffiffiffi ðV1  V2 ÞðV3  V4 Þ (2.236)
2 2FF
2.2 Analysis and Design of Multiplier Circuits 147

VDD

V1 + v1/2 V1- v1/2

M1 M2
ID1 ID2

V2 + v2/2 M3 M5 M6 M4 V2- v2/2

M13 M12
M11 M14
VP1 VP2

VQ1 VQ2
I I’ I I’

M7 M9 M10 M8
IOUT1 IOUT2

Fig. 2.57 Multiplier circuit (3) based on PR 2.Da

A symmetrical implementation of a voltage multiplier circuit is presented in

Fig. 2.57 [27]. In order to improve the frequency response, all MOS transistors are
biased in saturation region.
The differential output current of the voltage multiplier can be expressed as
follows:

IOUT ¼ IOUT1  IOUT2 ¼ ðID11 þ ID12 Þ  ðID13 þ ID14 Þ (2.237)

resulting:

K K 2
IOUT ¼ ðVDD  VP1  VT Þ2  VDD  VQ1  VT
2 2
K 2 K 2
þ ðVDD  VP2  VT Þ  VDD  VQ2  VT (2.238)
2 2
or:

K  
IOUT ¼ VQ2  VP1 2VDD  VP1  VQ2  2VT
2
K  
þ VQ1  VP2 2VDD  VP2  VQ1  2VT (2.239)
2
As a result of the connections between circuit transistors, the gate-source
voltages of M7 and M10 transistors are equal. Additionally, because the same
current I is passing through M3, M6, M7 and M10 transistors, all their gate-source
voltages will be also equal. The identity VGS3 ¼ VGS6 can be written as:
v2 v2
V2 þ  VP1 ¼ V2   V Q2 (2.240)
2 2
148 2 Voltage and Current Multiplier Circuits

It results:

VP1  VQ2 ¼ v2 (2.241)

and, similarly:

VQ1  V P2 ¼ v2 (2.242)

Replacing (2.241) and (2.242) in (2.239), the expression of the output current
becomes:

K  
IOUT ¼ v2 VP1  VP2 þ VQ2  VQ1 (2.243)
2

For evaluating the linear expression VP1  VP2 þ VQ2  VQ1 , it is necessary to
consider the squaring dependence of the drain current on the gate-source voltage for
M3 and M5 transistors:

K K v2 2
I¼ ðVGS3  VT Þ2 ¼ V2 þ  VP1  VT (2.244)
2 2 2

and:

K K v2 2
I0 ¼ ðVGS5  VT Þ2 ¼ V2 þ  VQ1  VT (2.245)
2 2 2

resulting:
rffiffiffiffiffi
v2 2I
V2 þ  VP1  VT ¼ (2.246)
2 K

and:
rffiffiffiffiffiffi
v2 2I 0
V2 þ  VQ1  VT ¼ (2.247)
2 K

Summing (2.246) and (2.247), it results:

rffiffiffiffi
2 pffiffi pffiffiffi0 
2V2 þ v2  VP1  VQ1  2VT ¼ Iþ I (2.248)
K

A similar analysis for M4 and M6 transistors will conclude to:

rffiffiffiffi
2 pffiffi pffiffiffi0 
2V2  v2  VP2  VQ2  2VT ¼ Iþ I (2.249)
K
2.2 Analysis and Design of Multiplier Circuits 149

Because ID1 ¼ ID3 þ ID6 and ID3 ¼ ID6 ¼ I, it results ID1 ¼ 2I and, similarly,
ID2 ¼ 2I 0 . So:
rffiffiffiffi rffiffiffiffi rffiffiffiffirffiffiffiffi
2 pffiffi pffiffiffi0  1 pffiffiffiffiffiffi pffiffiffiffiffiffi 1 K
Iþ I ¼ ID1 þ ID2 ¼ ðVSG1 þ VSG2  2VT Þ (2.250)
K K K 2

The source-gate voltages of M1 and M2 transistors can be expressed as

VSG1 ¼ VDD  V1  v1 =2, and VSG2 ¼ VDD  V1 þ v1 =2, so:
rffiffiffiffi
2 pffiffi pffiffiffi0  pffiffiffi
I þ I ¼ 2ðVDD  V1  VT Þ (2.251)
K

Replacing (2.251) in (2.248) and (2.249), it results:

2V2 þ v2  VP1  VQ1  2VT ¼ 2V2  v2  VP2  VQ2  2VT

pffiffiffi
¼ 2ðVDD  V1  VT Þ (2.252)

The M1 and M2 transistors form a differential amplifier, its differential output

current having the following expression:

K v1 2 K  v1 2
ID1  ID2 ¼ VDD  V1   VT  VDD  V1 þ  VT
2 2 2 2
¼ Kv1 ðVDD  V1  VT Þ (2.253)

As function on V2 and v2 input voltages, ID1 and ID2 currents could be expressed
as follows:

K v2 2 K  v2 2
ID1 ¼ ID3 þ ID6 ¼ V2 þ  VP1  VT þ V2   VQ2  VT (2.254)
2 2 2 2

and:

K v2 2 K  v2 2
ID2 ¼ ID4 þ ID5 ¼ V2   VP2  VT þ V2 þ  VQ1  VT (2.255)
2 2 2 2

resulting:

K  
ID1  ID2 ¼ VQ1  VP1 2V2 þ v2  VP1  VQ1  2VT
2
K  
þ VP2  VQ2 2V2  v2  VP2  VQ2  2VT (2.256)
2
150 2 Voltage and Current Multiplier Circuits

VDD

M7a M7b

VB1 IA IB IOUT1
VB1
M5a M6a M6b M5b
M2a VB2= M2b
VC2+v2 /2

M3a M3b

M4a M4b

VC1+v1/2 M1a M1b VC1-v1/2

Fig. 2.58 Multiplier circuit (4) based on PR 2.Da – half circuit

Replacing (2.252) in (2.250), it results:

K  
ID1  ID2 ¼ pffiffiffi ðVDD  V1  VT Þ VQ1  VP1 þ VP2  VQ2 (2.257)
2
Comparing (2.253) with (2.257), it can write:
pffiffiffi
VQ1  VP1 þ VP2  VQ2 ¼  2v1 (2.258)

Replacing (2.258) in (2.243), the output current of the multiplier will depend on
the product between v1 and v2 voltages:

K
IOUT ¼ pffiffiffi v1 v2 (2.259)
2
A voltage multiplier using MOS transistors biased in linear region is presented
in Fig. 2.58 [28].
The symmetrical structure shown in Fig. 2.58 has the following expression of the
output current:

K
IOUT1 ¼ IA  IB ¼ 2ðVGS1a  VT ÞVDS1a  VDS1a
2
2
K
 2ðVGS1b  VT ÞVDS1b  VDS1b
2
(2.260)
2
Drain-source voltages of M1a and M1b transistors are equal because
M3a–M3b and M4a–M4b pairs contains identical transistors, biased at equal
drain currents (for each pair):

not:
VDS1a ¼ VDS1b ¼ VDS1 ¼ VGS3a  VSG4a ¼ VGS3b  VSG4b (2.261)
2.2 Analysis and Design of Multiplier Circuits 151

VB1L=VB1 VB1R=VB1
VB2 = IOUT1 IOUT2
VB2 =
VC1 + v1/2 VC2 + v2/2 VC2 - v2/2 VC1 - v1/2

Fig. 2.59 Multiplier circuit (4) based on PR 2.Da – block diagram

As M3a and M5a and, respectively, M4a and M6a transistors are identical and
biased at the same drain current, their gate-source voltages are equal, VGS3a ¼ VSG5a
and VSG4a ¼ VSG6a , so:

VDS1 ¼ VSG5a  VSG6a ¼ ðVDD  VB1 Þ  ðVDD  VB2 Þ

v2
¼ VB2  VB1 ¼ VC2 þ  VB1 (2.262)
2

From (2.260), (2.261) ad (2.262), it results the following expression of the output
current for the circuit presented in Fig. 2.58:
 v2 
IOUT1 ¼ K ðVGS1a  VGS1b Þ VDS1 ¼ Kv1 VDS1 ¼ Kv1 VC2 þ  VB1 (2.263)
2

because VGS1a ¼ VC1 þ v1 =2, VGS1b ¼ VC1  v1 =2.

In order to obtain the multiplying function, two similar circuits from
Fig. 2.58 must be used, the difference between them being the value of VB2 potential:
VB2 ¼ VC2 þ v2 =2 for the left structure from Fig. 2.59 [28] and VB2 ¼ VC2  v2 =2
for the right structure.
The expression of the output current of the multiplier circuit presented in
Fig. 2.59 will be:
 v2   v2 
IOUT1  IOUT2 ¼ Kv1 VC2 þ  VB1  Kv1 VC2   VB1 ¼ Kv1 v2 (2.264)
2 2

Another possible realization of the voltage multiplier circuit is designed with the
main goal of reducing the total harmonic distortions coefficient (THD).
Because of the quadratic characteristic of a MOS transistor biased in satura-
tion, the linearity of the basic multiplier presented in Fig. 2.60 [29, 31] is rather
poor. The core of this circuit is a modified Gilbert cell, extended to implement
with good linearity the multiplication function.
152 2 Voltage and Current Multiplier Circuits

VDD

IOUT

I1 I2 I’1 I’2

V1 M1 M2 M3 M4

I I’
M5 M6

V2
IO

VC M7
-VDD

Fig. 2.60 Multiplier circuit (5) based on PR 2.Da

Considering a biasing in saturation of all transistors from Fig. 2.60,

the expressions of the drain currents for M1–M4 transistors are:
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi! sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi!
I KV12 K 2 V14 I0 KV12 K 2 V14
I1;2 ¼ 1  ; I 02;1 ¼ 1  (2.265)
2 I 4I 2 2 I0 4ðI 0 Þ2

The output current expression is:

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi!
  K2 K2 2
IOUT ¼ ðI1  I2 Þ þ I01  I02 ¼ V1 KI  V12  KI 0  V (2.266)
4 4 1

Similarly, the drain currents of M5 and M6 transistors will have the

following expressions:
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi!
IO KV22 K 2 V24
I¼ 1þ  2 (2.267)
2 IO 4IO

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi!
0 IO KV22 K 2 V24
I ¼ 1  2 (2.268)
2 IO 4IO
2.2 Analysis and Design of Multiplier Circuits 153

All transistors from Fig.ffi 2.60 are supposed to be identical. Considering the
pffiffiffiffiffiffiffiffiffiffi
limited expansion 1 þ x ffi 1 þ x=2, from the previous relations, it results
the approximate expression of the basic multiplier output current:

K K2
IOUT ffi pffiffiffi V1 V2  pffiffiffi V1 V23 (2.269)
2 8 2IO

Thus, the total harmonic distortions coefficient introduced by the circuit

(approximated with the third-order one) will be expressed as:

 2
KV22 1 V2
THD3 ffi ¼ (2.270)
8IO 4 VC þ VDD  VT

In conclusion, THD3 is directly proportional with the ratio between V2 input

signal amplitude and the effective gate-source voltage of the biasing transistor.
In order to improve the circuit linearity, the modified multiplier presented in
Fig. 2.61 [29] replaces the differential amplifier M5–M6 from Fig. 2.60 with a
cross-connected one, M5–M8 from Fig. 2.61. The output current expression for the
multiplier with improved linearity has the same form (2.266), but the expressions of
I and I 0 currents become:

I ¼ Ip1 þ I 0p1 (2.271)

I0 ¼ Ip2 þ I0p2 (2.272)

where:
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi!
IO1 K1 V22 K12 V24
Ip1;2 ¼ 1  2 (2.273)
2 IO1 4IO1

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi!
IO2 K2 V22 K22 V24
I 0p1;2 ¼ 1  2 (2.274)
2 IO2 4IO2

Similarly
pffiffiffiffiffiffiffiffiffiffiffi with the basic circuit analysis, considering the more accurate expan-
sion 1 þ x ffi 1 þ x=2  x2 =4, the output current of the multiplier from Fig. 2.61
will have the following expression:
rffiffiffiffi
K 
IOUT ffi V1 bV2 þ cV23 þ dV25 (2.275)
a
154 2 Voltage and Current Multiplier Circuits

VDD

IOUT

I1 I2 I’1 I’2

V1 M1 M2 M3 M4
K K K K

I I’

Ip1 Ip2 I’p1 I’p2

V2 M5 M6 M7 M8
K1 K1 K2 K2

IO1 IO2
KO1 KO2
VC

-VDD

Fig. 2.61 Multiplier circuit (6) based on PR 2.Da

where b, c and d are constants, expressed as follows:

1=2 1=2 1=2 1=2

K1 IO1  K2 IO2
b¼ (2.276)
2

3=2 1=2 3=2 1=2

K2 IO2  K1 IO1
c¼ (2.277)
16
5=2 3=2 5=2 3=2
K1 IO1  K2 IO2
d¼ (2.278)
128

Because the main nonlinearity from the output current expression is caused by
the third-order term of relation (2.242), the proposed linearization technique is
2.2 Analysis and Design of Multiplier Circuits 155

referring to the cancellation of the third-order distortions (c ¼ 0), equivalent with

the following design condition:
 3
IO2 K2
¼ (2.279)
IO1 K1

and, in consequence:
"  2 #
ðK1 IO1 Þ1=2 K2
b¼ 1 (2.280)
2 K1

5=2 3=2
"  2 #
K I K1
d ¼ 1 O1 1 (2.281)
128 K2

The total harmonic distortions for the multiplier circuit with improved linearity
(Fig. 2.61), approximated with the fifth-order one, will be:
 2  2  4
K12 K12 V2
THD5 ¼ V24 ¼ (2.282)
8K2 IO1 4K2 KO1 VC þ VDD  VT

Considering the particular case that K2 ¼ KO1 and K1 =K2 ¼ 1=2, it results:
 4
1 V2
THD5 ¼ (2.283)
256 VC þ VDD  VT

Thus, the linearity improvement from the circuit presented in Fig. 2.61 with
respect to the basic multiplier presented in Fig. 2.60 is about two orders of magnitude:
 
THD3 VC þ VDD  VT 2
¼ 64 (2.284)
THD5 V2

For the multiplier circuit presented in Fig. 2.62 [32], the expression of the output
current is:

IOUT ¼ I1 þ I2  I3  I4 (2.285)

or:

K K
IOUT ¼ ðV4  VX  VT Þ2 þ ðV3  VY  VT Þ2
2 2
K K
 ðV3  VX  VT Þ  ðV4  VY  VT Þ2
2
(2.286)
2 2
156 2 Voltage and Current Multiplier Circuits

VDD
IO

I2 I1
I3 I1 I5 I6 I4 I2
IOUT
V3 V4 V1 VS V2 V4 V3
I7 I8
VX VY
IA IB I4 I3
IO IO

-VDD

Fig. 2.62 Multiplier circuit (7) based on PR 2.Da

resulting:

K
IOUT ¼ ðV4  V3 ÞðV3 þ V4  2VX  2VT Þ
2
K
þ ðV3  V4 ÞðV3 þ V4  2VY  2VT Þ (2.287)
2

So:

IOUT ¼ K ðV3  V4 Þ ðVX  VY Þ (2.288)

Because of the current mirrors from the circuit, IA ¼ IB ¼ 0, so between the

currents from the circuit will exist the following linear relations:

I7 þ I5 ¼ IO (2.289)

I7 þ I8 ¼ IO (2.290)

and:

I8 þ I6 ¼ IO (2.291)

resulting I5 ¼ I8 and I6 ¼ I7 . So:

V1  VX ¼ VS  VY (2.292)

and:

V2  VY ¼ VS  VX (2.293)

equivalent with:

VX  VY ¼ V1  VS (2.294)
2.2 Analysis and Design of Multiplier Circuits 157

Fig. 2.63 Asymmetrical

differential structure I1 I2

M1 M2
V1 K nK V2

IO

and:

VX  VY ¼ VS  V2 (2.295)

It results:

V1 þ V2
VS ¼ (2.296)
2
and:

V1 þ V2 V1  V2
VX  VY ¼ V1  ¼ (2.297)
2 2
Replacing (2.297) in (2.288), the output current will be proportional with the
square of the differential input voltage:

K
IOUT ¼ ðV1  V2 Þ ðV3  V4 Þ (2.298)
2

A possible realization of a voltage multiplier circuit is based on a particular

implementation of a voltage squaring circuit. The method for designing such a
voltage squaring circuit uses a differential amplifier (Fig. 2.63) [17, 33] having a
controllable asymmetry between the geometries of its two composing transistors.
This difference between the aspect ratios of MOS transistors will introduce in
the output currents of the differential amplifier a term proportional with the square
of the differential input voltage.
Noting with V ¼ V1  V2 the differential input voltage, it can be expressed
as follows:
rffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2I1 2ðIO  I1 Þ
V ¼ VGS1  VGS2 ¼  (2.299)
K nK
158 2 Voltage and Current Multiplier Circuits

resulting:

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
K 2 IO  I1 I1 ðIO  I1 Þ
V ¼ I1 þ 2 (2.300)
2 n n

The expression of the unknown current, I1 , can be obtained solving the following
second-order equation, derived from (2.300):
" 2 #    2
n1 4 n  1 IO KV 2 4IO IO KV 2
I12 þ þ I1 2   þ  ¼ 0 (2.301)
n n n n 2 n n 2

So:

IO nðn  1Þ nV pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
I1 ¼ þ KV 2 þ 2KIO ðn þ 1Þ  K 2 nV 2 (2.302)
n þ 1 2ðn þ 1Þ 2
ðn þ 1Þ2

and:

nIO nð n  1Þ nV pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
ffi
I2 ¼ IO  I1 ¼  KV 2  2KIO ðn þ 1Þ  K 2 nV 2 (2.303)
n þ 1 2ð n þ 1Þ2
ð n þ 1Þ 2

The complete realization of a voltage squaring circuit uses a cross-coupling of

two differential amplifier having controllable asymmetries between their
geometries, M1–M2 and M3–M4 (Fig. 2.64) [17, 33].
Using (2.302) and (2.303), it results:
" #
nIO nðn  1Þ nV pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
IOUT ¼ ID2 þ ID4 ¼  KV 2  2KIO ðn þ 1Þ  K 2 nV 2
n þ 1 2ðn þ 1Þ 2
ðn þ 1Þ2
" #
nIO nðn  1Þ nV pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
þ  KV þ
2
2KIO ðn þ 1Þ  K nV 2 2
n þ 1 2ðn þ 1Þ2 ðn þ 1Þ2
2nIO nðn  1Þ 2
¼  KV ð2:304Þ
n þ 1 ð n þ 1Þ 2

An application of the previous presented voltage squarer circuit is represented by

a voltage multiplier with linear characteristic (Fig. 2.65).
The method of designing the multiplying function is to use two cross-connected
M1–M2 and M3–M4 differential amplifiers, each of them being biased at a drain
2.2 Analysis and Design of Multiplier Circuits 159

VDD

IOUT

M1 M2 M3 M4
K nK K nK
V

IO IO

Fig. 2.64 Voltage squaring circuit

VDD

aIO aIO
IOUT1 IOUT2 ISQ

I I V1
M7 M8 M9 M10
M1 M2 M3 M4
K nK K nK

I5 I6
IO IO
M5 M6

V2

ISS

-VDD

Fig. 2.65 Multiplier circuit (8) based on PR 2.Da

current equal with the difference between a drain current of another differential
amplifier, M5–M6 (I5 and, respectively, I6 ) and a current, I, which must have a term
proportional with the square of the first differential input voltage, in order
to compensate the intrinsic nonlinearity of the differential amplifiers. Because
M1–M4 transistors are identical, the dependencies of their drain currents on
160 2 Voltage and Current Multiplier Circuits

V1 differential input voltage, can be obtained particularizing relations (2.302)

and (2.303) for n ¼ 1:
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
I5  I KV1 4ðI5  I Þ
ID1 ¼   V12 (2.305)
2 4 K
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
I5  I KV1 4ðI5  I Þ
ID2 ¼ þ  V12 (2.306)
2 4 K
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
I6  I KV1 4ðI6  I Þ
ID3 ¼ þ  V12 (2.307)
2 4 K
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
I6  I KV1 4ðI6  I Þ
ID4 ¼   V12 (2.308)
2 4 K

The expression of the differential output current of the entire structure will be:

IOUT1  IOUT2 ¼ ðID1 þ ID3 Þ  ðID2 þ ID4 Þ ¼ ðID1  ID2 Þ  ðID4  ID3 Þ (2.309)

resulting:
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
KV1 4ðI5  I Þ 2 þ KV1 4ðI6  I Þ
IOUT1  IOUT2 ¼  V1  V12 (2.310)
2 K 2 K

In order to cancel the nonlinear dependence of the differential output current on the
differential input voltage, the I current must be proportional with the squaring of
the differential input voltage:

K 4
I¼ V (2.311)
4 1

For this particular current, I, the expression of the differential output

current becomes:
pffiffiffiffi pffiffiffiffi pffiffiffiffi
IOUT1  IOUT2 ¼ K V1 I6  I5 (2.312)

Considering the squaring dependencies of the drain currents of M5–M6

differential amplifier on the gate-source voltages of their composing transistors,
it results:
"rffiffiffiffi #
pffiffiffiffi K 1
IOUT1  IOUT2 ¼ K V1 ðVGS6  VGS5 Þ ¼ pffiffiffi KV1 V2 (2.313)
2 2
2.2 Analysis and Design of Multiplier Circuits 161

VDD

VC
M3 M4

I1 I2

M5 M6

VB + V1/2 VB - V1/2
M1 M7 M8 M2

Fig. 2.66 Multiplier circuit (9) based on PR 2.Da – circuit core

So, the differential output current is proportional with the product between the
input voltages. The implementation of the I current having the (2.311) expression is
realized using M7–M10 transistors, representing a voltage squaring circuit, similar
with the structure presented in Fig. 2.64. Comparing (2.304) with (2.311), it results
the following condition that must be imposed to the constant n:

nðn  1Þ 1
¼ (2.314)
ðn þ 1Þ2 4

So n ¼ 2:15 and:

K 2
ISQ ¼ 1:36IO  V (2.315)
4 1
Because I ¼ ISQ  aIO , the expression (2.311) of I current can be obtained for
a ¼ 1:36.
Another possible implementation of a multiplier circuit is based on the
differential amplifier presented in Fig. 2.66 [34].
The expression of the first output current is:

K K
I1 ¼ ðVGS5  VT Þ2 þ ðVGS8  VT Þ2 (2.316)
2 2
162 2 Voltage and Current Multiplier Circuits

Fig. 2.67 Multiplier circuit

(9) based on PR 2.Da – I1 I2
symbolic representation of
the circuit core
VB + V1/2 DA VB - V1/2

VC

equivalently with:

K K
I1 ¼ ðVC  VGS3  VT Þ2 þ ðVGS8  VT Þ2 (2.317)
2 2
Because M1 and M3 transistors are identical and biased at the same drain
current, their gate-source voltages will be equal, so:

K K
I1 ¼ ðVC  VGS1  VT Þ2 þ ðVGS8  VT Þ2 (2.318)
2 2
or:
 2  2
K V1 K V1
I1 ¼ VC  VB þ V  VT  þ VB  V  VT  (2.319)
2 2 2 2

Similarly, the second output current, IOUT2 , will have the following expression:
   
K V1 2 K V1 2
I2 ¼ VC  VB þ V  VT þ þ VB  V  VT þ (2.320)
2 2 2 2

The differential output current can be expressed as follows:

I2  I1 ¼ KV1 ðVC  VB þ V  VT Þ þ KV1 ðVB  V  VT Þ ¼ K ðVC  2VT ÞV1 (2.321)

The symbolic representation of the circuit is shown in Fig. 2.67.

A voltage multiplier can be realized using two previous presented differential
amplifiers having the VC voltage sources replaced by two voltages that are depen-
dent on a second input voltage, V2 . The complete multiplier circuit is shown in
Fig. 2.68.
The differential output current of the voltage multiplier presented in Fig. 2.68
can be expressed as follows:

IOUT1  IOUT2 ¼ ðI1 þ I3 Þ  ðI2 þ I4 Þ ¼ ðI1  I2 Þ þ ðI3  I4 Þ (2.322)

2.2 Analysis and Design of Multiplier Circuits 163

IOUT1 IOUT2

I1 I2 I3 I4

VB + V1/2 DA I DA II VB + V1/2

VB - V1/2

VC + V2/2 VC - V2/2

Fig. 2.68 Multiplier circuit (9) based on PR 2.Da – block diagram

VDD

M8 M13
VC2
M9 M14
IOUT2 IOUT1

V1 M1 M2 M3 M4
V4 M7 M12 V3
V2

VA VB

M11 M16
VC1
M10 M15

-VDD

Fig. 2.69 Multiplier circuit (10) based on PR 2.Da

resulting, using (2.321):

 
V2
IOUT1  IOUT2 ¼ K VC þ  2VT V1
2
 
V2
þ K VC   2VT ðV1 Þ ¼ KV1 V2 (2.323)
2

A possible realization of a voltage multiplier circuit is presented in Fig. 2.69 [35].

164 2 Voltage and Current Multiplier Circuits

The differential output current of the structure is:

IOUT1  IOUT2 ¼ ID2 þ ID4  ID1  ID3 (2.324)

equivalent with:

K K
IOUT1  IOUT2 ¼ ðV2  VA  VT Þ2 þ ðV1  VB  VT Þ2
2 2
K K
 ðV1  VA  VT Þ  ðV2  VB  VT Þ2
2
(2.325)
2 2

So:

IOUT1  IOUT2 ¼ K ðV1  V2 Þ ðVA  VB Þ (2.326)

The VA  VB differential voltage can be expressed as follows:

VA  VB ¼ ðV4  VGS7 Þ  ðV3  VGS12 Þ ¼ ðV4  V3 Þ þ ðVGS12  VGS7 Þ (2.327)

Because ID7 ¼ ID8 and ID12 ¼ ID13 , it results VGS7 ¼ VSG8 and VGS12 ¼ VSG13 .
So:

VA  VB ¼ ðV4  V3 Þ þ ðVSG13  VSG8 Þ ¼ V4  V3 (2.328)

Replacing (2.328) in (2.326), it results:

IOUT1  IOUT2 ¼ K ðV1  V2 ÞðV4  V3 Þ (2.329)

2.2.2 Design of Current Multiplier Circuits

Another class of multiplier circuits is represented by the current multipliers,

the output current of these circuits being proportional with the product
between two input currents. The current-mode operation of the multiplier circuits
has the important advantage of increasing the frequency response of the
designed structures.

2.2.2.1 Multiplier Circuits Based on the Ninth Mathematical

Principle (PR 2.9)

A possibility of designing a current multiplier uses as circuit cores two current

square-root circuits (Fig. 2.70) [36].
2.2 Analysis and Design of Multiplier Circuits 165

Fig. 2.70 CMOS square-root VDD

circuit for the multiplier
circuit (1) based on PR 2.9

IA IB IOUT1

4K

4K
IB
I

For a biasing in saturation of all the MOS transistors from Fig. 2.70, it is possible
to write that:
rffiffiffiffiffiffiffi! rffiffiffiffiffiffiffi! rffiffiffiffiffiffi!
2IA 2IB 2I
VT þ þ VT þ ¼ 2 VT þ (2.330)
K K 4K

equivalent with:
pffiffiffiffiffiffiffiffi
I ¼ IA þ IB þ 2 IA IB (2.331)

Implementing the following linear relation between the previous current of the
square-root circuit:

IOUT1 ¼ I  IA  IB (2.332)

the output current of the circuit from Fig. 2.70 will be proportional with the square-
root of the input current:
pffiffiffiffiffiffiffiffi
IOUT1 ¼ 2 IA IB (2.333)

The multiplier circuit can be obtained using two square-root circuits from
Fig. 2.70 connected as it is shown in Fig. 2.71. The computed functions are
pffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffi
IOUT1 ¼ 2 IOUT IO and IOUT2 ¼ 2 I1 I2 . Because IOUT1 ¼ IOUT2 , the function
implemented by the circuit from Fig. 2.71 [36] will be:

I1 I2
IOUT ¼ (2.334)
IO
166 2 Voltage and Current Multiplier Circuits

VDD

IO IOUT I1 I2

IOUT1 IOUT2

IREF IREF

Fig. 2.71 Multiplier circuit (1) based on PR 2.9

VDD

IOUT1 IOUT2 I3 + I4

I1 I1 I I4
I2 I3 I’
I3 I4

IO IO IO IO

IO IO

- VDD

Fig. 2.72 Multiplier circuit (2) based on PR 2.9

The design of a multiplier/divider circuit can be done using two square-root

circuits, as it is shown in Fig. 2.72 [37].
The square-root circuits have the implementation presented in Fig. 2. The output
currents of these circuits have the following expressions:
pffiffiffiffiffiffiffiffi
IOUT1 ¼ 2 I1 I2 (2.335)

and:
pffiffiffiffiffiffiffiffi
IOUT2 ¼ 2 I3 I4 (2.336)

Imposing by design IOUT1 ¼ IOUT2 , it results:

I1 I2
I4 ¼ (2.337)
I3
2.2 Analysis and Design of Multiplier Circuits 167

VDD

M1 M3
IOUT
IIN

M2 M4 2:1

IO

Fig. 2.73 CMOS squaring circuit for the multiplier circuit (1) based on PR 2.10

2.2.2.2 Multiplier circuits based on the tenth mathematical

principle (PR 2.10)

The following multiplier structure (Fig. 2.74) is derived from the squaring circuit
presented in Fig. 2.73 [38].
The characteristic equation of the translinear loop including M1–M4 transistors is:

VSG1 þ VSG2 ¼ VSG3 þ VSG4 (2.338)

resulting:
pffiffiffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffi
2 ID1 ¼ ID3 þ ID4 (2.339)

equivalent with:
pffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 IO ¼ IOUT þ IIN þ IOUT  IIN (2.340)

The expression of the output current will be:

2
IIN
IOUT ¼ IO þ (2.341)
4IO

Using the squaring circuit presented in Fig. 2.73, it is possible to design a current
multiplier structure (Fig. 2.74) [38].
The output current of the multiplier circuit can be expressed as follows:
" # " #
ðI1 þ I2 Þ2 ðI1 þ I2 Þ2 I1 I2
IOUT ¼ IOUT2  IOUT1 ¼ IO þ  IO  ¼ (2.342)
4IO 4IO IO
168 2 Voltage and Current Multiplier Circuits

VDD

IOUT
IO
IOUT1 IOUT2 I1 - I2
I 1 + I2

M1 M3 M5

2(I1 + I2) 2(I1 - I2)

M2 M4 M6

- VDD

Fig. 2.75 Multiplier circuit (2) based on PR 2.10

VDD

IOUT1 IOUT2

I1 - I2 I1 + I2

IO IO

Fig. 2.74 Multiplier circuit (1) based on PR 2.10

The multiplier/divider circuit presented in Fig. 2.75 [39] uses two translinear
loops implemented with M1–M4 and M3–M6 transistors, respectively.
The characteristic equation of the first translinear loop is:

VGS3 þ VSG4 ¼ VGS1 þ VSG2 (2.343)

Considering a biasing in saturation of all MOS transistors from Fig. 2.75,

it results:
pffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 IO ¼ IOUT1 þ ðI1 þ I2 Þ þ IOUT1  ðI1 þ I2 Þ (2.344)
2.2 Analysis and Design of Multiplier Circuits 169

VDD

IOUT

I1 + I2 I1 + I2 I1 - I2 I1 - I2
IA IB IC ID

Fig. 2.76 Multiplier circuit (2) based on PR 2.10

The IOUT1 current will be expressed as follows:

ðI1 þ I2 Þ2
IOUT1 ¼ IO þ (2.345)
4IO

Similarly, analyzing the characteristic equation for the second translinear loop,
it results:
pffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 IO ¼ IOUT1 þ ðI1  I2 Þ þ IOUT1  ðI1  I2 Þ (2.346)

So, the expression of IOUT2 current will be:

ðI1  I2 Þ2
IOUT2 ¼ IO þ (2.347)
4IO

The output current of the multiplier/divider circuit presented in Fig. 2.75 will
have the following expression:

I1 I2
IOUT ¼ IOUT1  IOUT2 ¼ (2.348)
IO

The most important advantage of the multiplier is the independence of the circuit
performances on technological errors.
A current multiplier circuit (Fig. 2.76) [40] can be designed using four current
squaring circuits.
Because:

VDD ¼ VGS ðIA Þ þ VGS ðIA  I1  I2 Þ (2.349)

it results:
rffiffiffiffi
pffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi K
IA þ IA  ðI1 þ I2 Þ ¼ ðVDD  2VT Þ (2.350)
2
170 2 Voltage and Current Multiplier Circuits

Thus, IA current can be expressed as follows:

I1 þ I2 KðVDD  2VT Þ2 ðI1 þ I2 Þ2

IA ¼ þ þ (2.351)
2 8 2KðVDD  2VT Þ2

Similarly:

I1 þ I2 KðVDD  2VT Þ2 ðI1 þ I2 Þ2

IB ¼  þ þ (2.352)
2 8 2KðVDD  2VT Þ2

I1  I2 KðVDD  2VT Þ2 ðI1  I2 Þ2

IC ¼ þ þ (2.353)
2 8 2KðVDD  2VT Þ2

I1  I2 KðVDD  2VT Þ2 ðI1  I2 Þ2

ID ¼  þ þ (2.354)
2 8 2KðVDD  2VT Þ2

The output current of the multiplier circuit presented in Fig. 2.76 will have the
following expression:

4I1 I2
IOUT ¼ IA þ IB  IC  ID ¼ (2.355)
KðVDD  2VT Þ2

Comparing with the previous circuit, the operation of this multiplier structure is
affected by technological errors (both K and VT technological parameters appear
in the expression of the output current).
The current multiplier circuit presented in Fig. 2.77 [41] contains two current
squaring circuits.
The expressions of the output current for these circuits are:

ðI1 þ I2 Þ2
IOUT1 ¼ 2IO þ (2.356)
8IO

and:

ðI1  I2 Þ2
IOUT2 ¼ 2IO þ (2.357)
8IO

The output current of the multiplier circuit presented in Fig. 2.77 will have the
following expression:

I1 I2
IOUT ¼ IOUT1  IOUT2 ¼ (2.358)
2IO
2.2 Analysis and Design of Multiplier Circuits 171

VDD

IOUT
IO
IOUT1 IOUT2

I2

I1 I1

- VDD

Fig. 2.77 Multiplier circuit (4) based on PR 2.10

2.2.2.3 Multiplier Circuits Based on the Eleventh Mathematical

Principle (PR 2.11)

The following multiplier structures are designed for low-power applications, the
reducing of their current consumptions being obtained by a biasing in weak inversion
of all MOS active devices.
A current multiplier/divider using bulk-driven subthreshold-operated
MOS transistors is presented in Fig. 2.78 [42, 43]. The double drive of the MOS
devices (on gate and on bulk) allows the reduction of the computational circuit
complexity. Unfortunately, the possibility of implementation in silicon is limited to
CMOS technologies with independent wells. Imposing a weak inversion of all MOS
transistors from Fig. 2.78, it is possible to write:
 
VGS1 þ ðn  1ÞVBS1
IOUT1 ¼ IDO exp (2.359)
nVth
 
VGS2 þ ðn  1ÞVBS2
IOUT2 ¼ IDO exp (2.360)
nVth

So:
 
IOUT1 VX2  VY2 n1
¼ exp exp ðVX1  VY1 Þ (2.361)
IOUT2 nVth nVth
172 2 Voltage and Current Multiplier Circuits

VDD

IO (IZ1) IO IO IO

M3 M7 M8 M4

IOUT1 IOUT2

VX1 M1 VX2 VY2 M2 VY1 V

M5 M9 M10 M6

IX1 IX2 IY2 IY1

-VDD

Fig. 2.78 Multiplier circuit (1) based on PR 2.11

pffiffiffiffiffiffiffiffiffiffiffiffiffi
Because VGS3 ¼ VSG5 and VGS4 ¼ VSG6 , where VSG5 ¼ VSG6 ¼ VT þ 2IO =K
it results VGS3 ¼ VGS4 , so:

IX1 n1
¼ exp ðVBS3  VBS4 Þ (2.362)
IY1 nVth

Similarly, because VGS7 ¼ VGS8 , it results:

IX2 n1
¼ exp ðVBS7  VBS8 Þ (2.363)
IY2 nVth

Knowing that VX1  VY1 ¼ VBS4  VBS3 , VX2  VY2 ¼ VBS8  VBS7 and using
(2.361) and (2.362), it can write that:
  1
IOUT1 IY1 IY2 n1
¼ (2.364)
IOUT2 IX1 IX2

A generalization of (2.364) relation for different values of IO current sources

(IZ1 ; IW1 and IZ2 ; IW2 , respectively) allows to obtain a more complex relation
between the circuit currents:
  1
IOUT1 IY1 IZ1 IY2 IZ2 n1
¼ (2.365)
IOUT2 IX1 IW1 IX2 IW2

Another implementation of a current-mode multiplier/divider is referred to

a bulk-driven active-load differential amplifier from Fig. 2.79 [42]. Considering a
weak inversion operation of all transistors from Fig. 2.79, the ratio of I1 and I2
currents will be:
 
IOUT1 VGS1  VGS2
¼ exp (2.366)
IOUT2 nVth
2.2 Analysis and Design of Multiplier Circuits 173

VDD

IOUT1 IOUT2

M1 M2

IO

-VDD
VDD

IX1 IX2

M3 M4

VX1 VX2
M5 M6

IY1 IY2

-VDD

Fig. 2.79 Multiplier circuit (2) based on PR 2.11

For the active-load differential amplifier, it can write:

 
ID1 VGS1  VGS2 n1
¼ 1 ¼ exp exp ðVBS1  VBS2 Þ (2.367)
ID2 nVth nVth
174 2 Voltage and Current Multiplier Circuits

From the two previous relations, it results:

IOUT1 1n
¼ exp ðVX1  VX2 Þ (2.368)
IOUT2 nVth

Similarly, the ratios of IX1 ; IX2 and IY1 ; IY2 are, respectively:
   
IX1 VSG6  VSG5 VGS3  VGS4
¼ exp ¼ exp (2.369)
IX2 nVth nVth

and:
 
IY1 VGS3  VGS4 n1
¼ exp exp ðVBS3  VBS4 Þ (2.370)
IY2 nVth nVth

So:
 
nVth IY1 IX2
VBS3  VBS4 ¼ ln (2.371)
n1 IY2 IX1

From (2.368) and (2.371), using that VX1  VX2 ¼ VBS4  VBS3 , the relation
between the currents from Fig. 2.79 will be:

IOUT1 IY1 IX2

¼ (2.372)
IOUT2 IY2 IX1

The current multiplier circuit presented in Fig. 2.80 [44–46] uses MOS
transistors biased in weak inversion region. The translinear loop containing
M1–M4 transistors has the following characteristic equation:

VGS1 þ VGS2 ¼ VGS3 þ VGS4 (2.373)

The biasing currents of these transistors are: I1 for M1, I2 for M2, IO for M3
and IOUT for M4. The previous relation can be written as:

I1 I2
nVth ln þ nVth ln
ðW=LÞID0 ðW=LÞID0
IO IOUT
¼ nVth ln þ nVth ln (2.374)
ðW=LÞID0 ðW=LÞID0

resulting:

I1 I2
IOUT ¼ (2.375)
IO
2.2 Analysis and Design of Multiplier Circuits 175

Fig. 2.80 Multiplier circuit VDD

(3) based on PR 2.11

I2

M6 M8 M9

IOUT

M1 M5 M3 M7

M2 M4

I1 IO

A four-quadrant multiplier derived from the circuit presented in Fig. 2.80 is

shown in Fig. 2.81 [44].
Similarly with the previous circuit:

ðIO þ I1 ÞðIO þ I2 Þ I1 I2
ID7 ¼ ¼ IO þ I1 þ I2 þ (2.376)
IO IO

resulting the following expression of the output current:

I1 I2
IOUT ¼ ID7  IO  I1  I2 ¼ (2.377)
IO

The circuit presented in Fig. 2.82 [47, 48] represents a current multiplier
implemented using MOS transistors biased in weak inversion region. Using the
exponential dependence of the drain current on the gate-source and bulk-source
voltages for a subthreshold-operated MOS device, the ratio between I2 and IOUT
currents can be expressed as follows:

VSG2 þ ðn  1ÞVSB2
IDO exp  
I2 nVth VSG2  VSG4
¼ ¼ exp (2.378)
IOUT VSG4 þ ðn  1ÞVSB4 nVth
IDO exp
nVth
176 2 Voltage and Current Multiplier Circuits

VDD

I1 + IO

M6 M8 M9
IOUT + I1 +
I2 + IO

M1 M5 M3 M7

M2 M4

I2 + IO IO

Fig. 2.81 Multiplier circuit (4) based on PR 2.11

VDD

M1 M3
M4 M2

IOUT I1 IO I2

Fig. 2.82 Multiplier circuit (5) based on PR 2.11

Using the exponential dependence of the drain current on the gate-source voltage
for a MOS transistor biased in weak inversion region, it can be obtained:
 
IO
VSG2 ¼ VSG3 ¼ nVth ln  ðn  1ÞVSB3 (2.379)
IDO

and:
 
I1
VSG1 ¼ VSG4 ¼ nVth ln  ðn  1ÞVSB1 (2.380)
IDO
2.2 Analysis and Design of Multiplier Circuits 177

VDD

IX
M3 M4 M5
M1 M2 M6 M7

I1 I2
IO IOUT1 IOUT2
M11

M8 M9 M10 M12

Fig. 2.83 Multiplier circuit (6) based on PR 2.11

Because VSB3 ¼ VSB1 , from the previous relations, it results:

I1 I2
IOUT ¼ (2.381)
IO

A four-quadrant multiplier and two-quadrant divider is presented in Fig. 2.83 [47].

The M2, M4, M5 and M6 transistors form the multiplier presented in Fig. 2.82.
The output currents IOUT1 and IOUT2 can be expressed as follows:

ID6 ID4 ðIO þ I1 Þ ðIO þ I2 Þ

IOUT1 ¼ ID1 þ ID5 ¼ IO þ ¼ IO þ (2.382)
ID2 IO

and:

IOUT2 ¼ ID3 þ ID7 ¼ ID4 þ ID6 ¼ ðIO þ I1 Þ þ ðIO þ I2 Þ (2.383)

resulting:

I1 I2
IOUT1  IOUT2 ¼ (2.384)
IO

The circuit presented in Fig. 2.84 [49] implements the current multiplying
function.
The characteristic equation of the translinear loop realized using the gate-source
voltages of M1A–M5A transistors can be written as follows:

VGS1A þ VGS2A ¼ VGS3A þ VGS4A (2.385)

For a weak inversion operation for all MOS devices, it results the following
expression of the first output current:

I2
IOUT1 ¼ ðIREF þ I1 Þ (2.386)
IO
178 2 Voltage and Current Multiplier Circuits

VDD

IREF + I1 M6A M6B

IREF - I1
IOUT
M5A M5B
VC M2A M3A M3B M2B VC
IOUT1 IOUT2

M1A M4A M4B M1B

I2 IO IO I2

Fig. 2.84 Multiplier circuit (7) based on PR 2.11

Fig. 2.85 Multiplier circuit

(8) based on PR 2.11 I1 IOUT I2 IO

M1 M2 M3 M4

I1 + IO I2 + IOUT

and, similarly, for the translinear loop implemented using the gate-source voltages
of M1B–M5B transistors:

I2
IOUT2 ¼ ðIREF  I1 Þ (2.387)
IO

The expression of the differential output current of the entire structure will be:

I1 I2
IOUT ¼ IOUT1  IOUT2 ¼ 2 (2.388)
IO

A possible realization of a current multiplier is presented in Fig. 2.85 [50].

The translinear loop implemented using M1–M4 transistors has the following
characteristic equation:

VGS1 þ VGS3 ¼ VGS2 þ VGS4 (2.389)

For a biasing in weak inversion of the circuit transistors, the previous

relation becomes:

I1 I2
IOUT ¼ (2.390)
IO
2.2 Analysis and Design of Multiplier Circuits 179

VDD

M11 M12
IOUT

IO
IA IB IC ID

M2 M4 M6 M8 M10

M1 M3 M5 M7 M9

I 1 + I2 I1 + I2 I1 - I2 I1 - I2

Fig. 2.86 Multiplier circuit (1) based on PR 2.Db

2.2.2.4 Multiplier circuits based on different mathematical

principle (PR 2.Db)

The circuit presented in Fig. 2.86 [51] represents a current multiplier, having a
principle of operation based on four translinear loops. The first loop contains
M1–M4 transistors, M1–M2 pair being biased at the reference current, IO ,
M3 transistor – at IA  I1  I2 drain current, while M3 transistor is working at
IA current.
The characteristic equation of the translinear loop can be written as follows:

VGS1 þ VGS2 ¼ VGS3 þ VGS4 (2.391)

resulting, for a biasing in saturation of all MOS transistors:

pffiffiffiffiffi pffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 IO ¼ IA þ IA  I1  I2 (2.392)

Squaring the previous relation, it can be obtained:

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
4IO ¼ 2IA  I1  I2  2 IA ðIA  I1  I2 Þ (2.393)

So, the IA current will have the following expression:

I1 I2 I1 I2 I2 I2
IA ¼ IO þ þ þ þ 1 þ 2 (2.394)
2 2 8IO 16IO 16IO
180 2 Voltage and Current Multiplier Circuits

VDD

M11 M12
IOUT
M3 M5 M9

M1 M2 V1 I1 + I2 I1 V2 M7 M8 V3 I2

M4 M6 M10

-VDD

Fig. 2.87 Multiplier circuit (2) based on PR 2.Db

Similarly, considering the translinear loops implemented using the gate-source

voltages of M1, M2, M5, M6 and M1, M2, M7, M8 and, respectively, M1, M2, M9,
M10 transistors, it results the following expressions of the other three output
currents:

I1 I2 I1 I2 I2 I2
IB ¼ IO   þ þ 1 þ 2 (2.395)
2 2 8IO 16IO 16IO

I1 I2 I1 I2 I2 I2
IC ¼ IO þ   þ 1 þ 2 (2.396)
2 2 8IO 16IO 16IO

I1 I2 I1 I2 I2 I2
ID ¼ IO  þ  þ 1 þ 2 (2.397)
2 2 8IO 16IO 16IO

The output current can be expressed as follows:

I1 I2
IOUT ¼ ðIA þ IB Þ  ðIC þ ID Þ ¼ (2.398)
2IO

The independence of the circuit performances on technological parameters and,

as a result, their immunity with respect to technological errors, represents an
important characteristic of the previously presented multiplier circuit.
The circuit presented in Fig. 2.87 [52] implements the current multiplying
function. Transistors M5 and M6 form a voltage divider with an input current, I1 ,
that will modify the divided potential V2 . The current balance in this point can be
quantitatively evaluated by the following relation:

K K
ðVDD  V2  VT Þ2 þ I1 ¼ ðV2 þ VDD  VT Þ2 (2.399)
2 2
2.3 Conclusion 181

resulting:

I1
V2 ¼ (2.400)
2K ðVDD  VT Þ

The output current of the circuit will linearly depend on the following drain
currents:

IOUT ¼ ID1 þ ID2  ID7  ID8 (2.401)

the previous currents having the following expressions:

K
ID1 ¼ ðVDD  VT Þ2 (2.402)
2
2
K K I1 þ I2
ID2 ¼ ðV1 þ VDD  VT Þ2 ¼ þ VDD  VT (2.403)
2 2 2K ðVDD  VT Þ

2
K K I1
ID7 ¼ ðV2 þ VDD  VT Þ2 ¼ þ VDD  VT (2.404)
2 2 2K ðVDD  VT Þ

and:

2
K K I2
ID8 ¼ ðV3 þ VDD  VT Þ2 ¼ þ VDD  VT (2.405)
2 2 2K ðVDD  VT Þ

So, the output current will be proportional with the product between the input
currents:

I1 I2
IOUT ¼ (2.406)
4K ðVDD  VT Þ2

The disadvantage of this circuit is represented by the dependence of the output

current on the supply voltage and on the threshold voltage.

2.3 Conclusion

Chapter describes the principle of operation of CMOS multiplier circuits and, starting
from their functional principle of operation, it presents many implementations in
CMOS technology of these computational structures. There were analyzed multiplier
182 2 Voltage and Current Multiplier Circuits

circuits having both current-input and voltage-input variables. Depending on the

power consumption imposed to the designs, two important classes of multiplier
structures have been presented. For improving the frequency response, circuits
using exclusively MOS transistors biased in saturation region have been used,
while low-power multipliers have been designed based on subthreshold-operated
MOS active devices. The linearity of multiplier circuits has been improved by
applying specific design techniques.

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Chapter 3
Squaring Circuits

3.1 Mathematical Analysis for Synthesis of Squaring Circuits

The synthesis of squaring circuits [1–55] is based on the utilization of some

elementary principle, each of them representing the starting point for designing a
class of squarers. For voltage squarers, the notations used are: V1 and V2 represent
the input potentials, while, usually, a constant voltage, VO is introduced for
modeling a voltage shifting. For current squarers, IO is a reference current and IIN
denotes the input current. The notation IOUT is used for the output current of both
voltage and current squaring circuits.

3.1.1 Mathematical Analysis of Voltage Squaring Circuits

3.1.1.1 First Mathematical Principle (PR 3.1)

The first mathematical principle used for implementing squaring circuits is based
on the following relation:

 rffiffiffiffiffiffiffiffiffiffiffiffi  rffiffiffiffiffiffiffiffiffiffiffiffi
2IOUT 2IOUT
V1
V 2 ¼ V T þ
VT þ
K1 K2
   
2
pffiffiffiffiffiffiffiffiffi 1 1 1 1
¼ IOUT pffiffiffiffiffiffi
pffiffiffiffiffiffi ) IOUT ¼ pffiffiffiffiffiffi
pffiffiffiffiffiffi ðV1
V2 Þ2 (3.1)
K1 K2 K1 K2

C.R. Popa, Synthesis of Computational Structures for Analog Signal Processing, 185
DOI 10.1007/978-1-4614-0403-3_3, # Springer Science+Business Media, LLC 2011
186 3 Squaring Circuits

3.1.1.2 Second Mathematical Principle (PR 3.2)

The mathematical relation that models this principle is:

h i h i
AðV1
V2 Þ2 þ BðV1
V2 Þ þ C þ AðV1
V2 Þ2
BðV1
V2 Þ þ C

2C ¼ 2AðV1
V2 Þ2 (3.2)

3.1.1.3 Third Mathematical Principle (PR 3.3)

The third mathematical principle is illustrated by the following relation:

 2
V1 þ V2
2
VO
ðV1
VO Þ2
ðV2
VO Þ2
2
   
V2
V1 3V1 þ V2 V1
V2 3V2 þ V1 1
¼
2VO þ
2VO ¼
ðV1
V2 Þ2 (3.3)
2 2 2 2 2

3.1.1.4 Different Mathematical Principles for Voltage Squaring

Circuits (PR 3.Da)

A class of voltage squaring circuits is based on different mathematical principles.

3.1.2 Mathematical Analysis of Current Squaring Circuits

3.1.2.1 Fifth Mathematical Principle (PR 3.5)

The mathematical relation that models this principle is:

pffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 IO ¼ aIO þ bIOUT þ cIIN þ aIO þ bIOUT
cIIN
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
) 4IO ¼ 2aIO þ 2bIOUT þ 2 ðaIO þ bIOUT Þ2
c2 IIN 2

) 4ð2
aÞ2 IO2 þ 4b2 IOUT

2

8ð2
aÞbIO IOUT
¼ 4a2 IO2 þ 4b2 IOUT
2
þ 8abIO IOUT
4c2 IIN
2

1
a c2 IIN
2
) IOUT ¼ IO þ (3.4)
b 4b IO
3.1 Mathematical Analysis for Synthesis of Squaring Circuits 187

3.1.2.2 Sixth Mathematical Principle (PR 3.6)

The utilization of MOS transistors biased in weak inversion region allows to

implement the following mathematical relation:

2
IIN
2 lnðIIN Þ ¼ lnðIO Þ þ lnðIOUT Þ ) IOUT ¼ (3.5)
IO

3.1.2.3 Seventh Mathematical Principle (PR 3.7)

The mathematical relation that models this principle is:

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi!2
9 3 pffiffiffiffiffi IO IIN
IO þ IIN þ IOUT ¼ IO þ IOUT þ þ
4 2 4 2
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
 ffi
IO IIN I2
) IO þ IIN ¼ 2 IO IOUT þ þ ) IOUT ¼ IN (3.6)
4 2 4IO

3.1.2.4 Eighth Mathematical Principle (PR 3.8)

This principle is illustrated by the following mathematical relation:

ðIO
IIN Þ2 þ ðIO þ IIN Þ2 ¼ 2IO2 þ 2IIN

2
(3.7)

3.1.2.5 Ninth Mathematical Principle (PR 3.9)

This mathematical principle uses a current square-rooting circuit for implementing

the squaring function.

3.1.2.6 Different Mathematical Principles for Current Squaring

Circuits (PR 3.Db)

A class of squaring circuits is based on different mathematical principles.

188 3 Squaring Circuits

3.2 Analysis and Design of Squaring Circuits

Based on the previous presented mathematical analysis, it is possible to design

different types of squaring circuits, concentrated in two important classes: voltage
squaring and current squaring circuits.

3.2.1 Design of Voltage Squaring Circuits

The voltage squaring circuits are grouped in four classes, corresponding to the first
four mathematical principles (PR 3.1 – PR 3.Da).

3.2.1.1 Squaring Circuits Based on the First Mathematical

Principle (PR 3.1)

A method for obtaining a voltage squaring circuit using the first mathematical
principle (PR 3.1) is based on the utilization of an unbalanced MOS differential
amplifier (M1–M7 in Fig. 3.1) [1].
All MOS transistors from Fig. 3.1 are identical, excepting M6 that has an aspect
ratio nth times greater than other transistors. This controllable asymmetry will be
equivalent with a nonzero differential input voltage in the equilibrium state.
The drain currents of M1 and M5 transistors are equal as a result of the M2–M3
and M4–M5 currents mirrors. Because ID1 þ ID7 ¼ ID5 þ ID6 , it can be obtained
ID6 ¼ ID7 . The current mirror M4–M6 with different transistors imposes
ID6 ¼ nID4 ¼ nID5 , so ID7 ¼ nID1 , equivalent with different gate-source voltages
for M1 and M7 transistors (that compose the differential stage):
rffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffi
2ID7 2nID1
VGS7 ¼ þ VT ¼ þ VT (3.8)
K K

VDD

M2 M3

IOUT
M1 M7 V2
V1

M5 M4 M6
Fig. 3.1 Squaring circuit (1)
based on PR 3.1
3.2 Analysis and Design of Squaring Circuits 189

where:

K
ID1 ¼ ðVGS1
VT Þ2 (3.9)
2

It results the following dependence of VGS7 on VGS1 :

pffiffiffi
VGS7 ¼ nðVGS1
VT Þ þ VT (3.10)

The V1
V2 differential input voltage quantitatively evaluates the asymmetry of

the differential stage:
 pffiffiffi pffiffiffi 
V1
V2 ¼ VGS1
VGS7 ¼ VGS1 1
n þ VT n
1 (3.11)

So, the gate-source voltage of M1 transistor can be expressed as a function of the

differential input voltage, as follows:

V1
V 2
VGS1 ¼ pffiffiffi þ VT (3.12)
1
n

Using the (3.9) squaring dependence, the output current of the circuit presented
in Fig. 3.1 will have the following expression:

K 2
IOUT ¼ ID1 ¼ pffiffiffi 2 ðV1
V2 Þ (3.13)
2ð1
nÞ

Based on the same mathematical principle, a stacked stage, M3–M4 (Fig. 3.2)
[2] can implement the squaring function:
rffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffi  
2IOUT 2IOUT pffiffiffiffiffiffiffiffiffiffiffiffi 1 1
V1 ¼ VGS4
VGS3 ¼
¼ 2IOUT pffiffiffiffiffiffi
pffiffiffiffiffiffi (3.14)
K4 K3 K4 K3

resulting:

V12
IOUT ¼  2 ¼ AV1
2
(3.15)
2 pffiffiffiffi
1
K

pffiffiffiffi
1
K
4 3

A being a constant that models the squaring dependence of the output current,
IOUT , on the input voltage, V1 .
190 3 Squaring Circuits

Fig. 3.2 Squaring circuit (2) VDD

based on PR 3.1

M1 M2

IOUT IOUT

- + M3

V1 M4

IOUT
2IO

IOUT1 IOUT2

M1 M2
V1 IO IO V2

IOUT1 VO VO IOUT2
- + + -

IO IO
IO IO

Fig. 3.3 Squaring circuit (1) based on PR 3.2 – principle circuit

3.2.1.2 Squaring Circuits Based on the Second Mathematical

Principle (PR 3.2)

A voltage squaring circuit can be implemented using the second mathematical

principle (PR 3.2), starting from the differential amplifier with the transfer charac-
teristic linearized using a method based on the constant sum of gate-source voltages
(Fig. 3.3) [3].
3.2 Analysis and Design of Squaring Circuits 191

Considering a biasing in saturation of MOS transistors, IOUT1 and IOUT2 output

currents of the circuit from Fig. 3.3 can be expressed as follows:

K
IOUT1 ¼ ðVGS1
VT Þ2 (3.16)
2

K
IOUT2 ¼ ðVGS2
VT Þ2 (3.17)
2

The V1
V2 differential input voltage has the following expressions:

V1
V2 ¼ VO
VGS2 ¼ VGS1
VO (3.18)

resulting:

VGS1 ¼ VO þ ðV1
V2 Þ (3.19)

and:

VGS2 ¼ VO
ðV1
V2 Þ (3.20)

Replacing (3.19) and (3.20) in (3.16) and (3.17). Thus:

K
IOUT1 ¼ ½ðVO
VT Þ þ ðV1
V2 Þ2 (3.21)
2

and:

K
IOUT2 ¼ ½ðVO
VT Þ
ðV1
V2 Þ2 (3.22)
2

So, the sum of the output currents for the circuit presented in Fig. 3.3 will be:

IOUT1 þ IOUT2 ¼ K ðVO
VT Þ2 þ K ðV1
V2 Þ2 (3.23)

In order to avoid a dependence of the output current on the threshold voltage of

the MOS devices, VO voltage sources from Fig. 3.3 are implemented using gate-
source voltages of MOS transistors biased in saturation region. Considering that the
current passing through these current-controlled voltage sources is a constant
current, IO , the VO voltage will have the following expression:
rffiffiffiffiffiffiffi
2IO
VO ¼ VT þ (3.24)
K
192 3 Squaring Circuits

VDD

2IO IO
IOUT

IOUT1 IOUT2

V1 M1 M3 M5 M2 V2

VO VO
IO + IOUT1 IO + IOUT2

M4 M6

-VDD

Fig. 3.4 Squaring circuit (1) based on PR 3.2 – first implementation

Replacing (3.24) in (3.23), it results:

IOUT1 þ IOUT2 ¼ 2IO þ K ðV1
V2 Þ2 (3.25)

The output current of the voltage squaring circuit, IOUT , can be expressed using a
linear relation between the currents from the circuit:

IOUT ¼ IOUT1 þ IOUT2
2IO ¼ K ðV1
V2 Þ2 (3.26)

It exists many possibilities of implementing this principle (Fig. 3.4–3.7) [4, 5].
The VO voltage sources are realized in Fig. 3.4 using M3 and M5 transistors, in
Fig. 3.5 and in Fig. 3.6 – using M3 and M4 transistors, while in Fig. 3.7 – using M3
and M4 transistors. The expressions of the output current are given by (3.26) for all
four squaring circuits.
Starting from the general circuit presented in Fig. 3.3, it is possible to design a
current squaring circuit, implementing proper linear relations between the currents
from the circuit and using multiple current mirrors, as it is shown in Fig. 3.8 [3]:

IOUT1 þ IOUT2 ¼ 8IA þ 8IIN þ 2IO (3.27)

The sum of the output currents of the differential amplifier (the “Linear DA” block
from Fig. 3.8 is realized using the differential amplifier presented in Fig. 3.3) is:

IOUT1 þ IOUT2 ¼ 2IO þ K ðVA
VB Þ2 (3.28)

3.2 Analysis and Design of Squaring Circuits 193

VDD

IO 2IO IOUT IO IO

IOUT1 IOUT2
M1 M2

V1 M3 M4 V2
VO VO

-VDD

Fig. 3.5 Squaring circuit (1) based on PR 3.2 – second implementation

VDD

IOUT1 2IO IOUT2

IOUT1 IO IOUT IO IOUT2

M1 M3 M4 M2
V1 V2
VO VO

I
I’

IO IO

Fig. 3.6 Squaring circuit (1) based on PR 3.2 – third implementation

The VA
VB differential voltage, that is fixed by IA and IB currents, can be

expressed as a function on the gate-source voltages as follows:

VA
VB ¼ 2VGS ðIA Þ
2VGS ðIB Þ (3.29)

194 3 Squaring Circuits

VDD

M5 M6 M7 M15 M16 M17

2IO IOUT

IOUT1 IOUT1 IOUT2 IOUT2

M1 M2 M3 M4 M13 M14
V1 V2

IO IO
A VO VO
B
I’
IOUT1 2IOUT1 2IOUT1 I
2IOUT2 2IOUT2 IOUT2
IO IO
M10 M9 M8 M12 M11 M18

Fig. 3.7 Squaring circuit (1) based on PR 3.2 – fourth implementation

CM CM

IA IA 8IA 2IO 8IIN IIN/2 IIN

IOUT IOUT1+IOUT2

IB

VA Linear
VB
DA

IB/4
IO

Fig. 3.8 Squaring circuit (2) based on PR 3.2 – block diagram

3.2 Analysis and Design of Squaring Circuits 195

Replacing (3.29) in (3.28) and using the square-root dependence of the drain
current on its gate-source voltage for a MOS transistor biased in saturation, it can be
obtained:

rffiffiffiffiffiffiffi rffiffiffiffiffiffiffi!2
2IA 2IB
IOUT1 þ IOUT2 ¼ 2IO þ K 2
2 (3.30)
K K

equivalent with:
pffiffiffiffiffiffiffiffi
IOUT1 þ IOUT2 ¼ 2IO þ 8IA þ 8IB
16 IA IB (3.31)

From (3.27) and (3.31), it results:

ðIB
IIN Þ2 IB IIN IIN

2
IA ¼ ¼
þ (3.32)
4IB 4 2 4IB

The expression of the output current of the current squaring circuit will be:

2
IIN IB IIN
IOUT ¼ IA þ
¼ (3.33)
2 4 4IB

where IIN is the input current and IB represents the reference current. For simplicity,
IB current can be considered to be equal with the other reference current, IO , that
biases the differential amplifier, resulting:

2
IIN
IOUT ¼ (3.34)
4IO

The complete implementation of the current squaring circuit, having the princi-
ple shown in Fig. 3.8 is presented in Fig. 3.9 [3]. The “Linear DA” block is realized
using the differential amplifier from Fig. 3.5.
The squaring circuit presented in Fig. 3.10 [6] is also based on the same
mathematical principles.
Noting with VGS ðIÞ the gate-source voltage of a MOS transistor having the
drain current equal with I, the differential input voltage can be expressed as
follows:
rffiffiffiffi
2 pffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffi
V1
V2 ¼ 2VGS ðIO Þ
2VGS ðIOUT1 Þ ¼ 2 IO
IOUT1 (3.35)
K

rffiffiffiffi
2 pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffi
V1
V2 ¼ 2VGS ðIOUT2 Þ
2VGS ðIO Þ ¼ 2 IOUT2
IO (3.36)
K
196 3 Squaring Circuits

VDD

IO
IO 2IO 8IIN IO
IA 8IA IIN/2
IIN
IOUT IA
IOUT1 IOUT2

IB IB/4
VA VB

-VDD

Fig. 3.9 Squaring circuit (2) based on PR 3.2 – complete implementation

VDD

IO IO

M3 M8 M6 M4

V1 V2
M1 M5 M7 M2

IOUT1 IOUT2
2IO

IOUT

Fig. 3.10 Squaring circuit (3) based on PR 3.2

resulting:
rffiffiffiffi
pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffi V1
V2 K
IOUT1 ¼ IO
(3.37)
2 2

and:
rffiffiffiffi
pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffi V1
V2 K
IOUT2 ¼ IO þ (3.38)
2 2
equivalent with:
rffiffiffiffiffiffiffiffi
KIO K
IOUT1 ¼ IO
ðV1
V2 Þ þ ðV1
V2 Þ2 (3.39)
2 8
3.2 Analysis and Design of Squaring Circuits 197

Fig. 3.11 Squaring circuit

(4) based on PR 3.2 –
principle circuit IO + IOUT2 IO + IOUT1

+ − − +

IO IO
VO VO

V1 V2
M1 M2

IO IO

IOUT1 IOUT2
2IO

IOUT

and:
rffiffiffiffiffiffiffiffi
KIO K
IOUT2 ¼ IO þ ðV1
V2 Þ þ ðV1
V2 Þ2 (3.40)
2 8

The output current for the structure presented in Fig. 3.10 will be:

K
IOUT ¼ IOUT1 þ IOUT2
2IO ¼ ðV1
V2 Þ2 (3.41)
4
Another possible realization of a voltage squaring circuit using the second
mathematical principle (PR 3.2) is illustrated in Fig. 3.11, while the complete
implementation of the circuit is shown in Fig. 3.12. The circuit represents a
complementary approach of the structure presented in Fig. 3.3. The M1 and M2
transistors from Fig. 3.11 are replaced in Fig. 3.12 [7] by M13 and M14 transistors,
VO voltage sources being implemented using the source-gate voltages of M3 and
M10 transistors. The other devices from Fig. 3.12 are used for mirroring the
currents in the circuit. As M3, M5, M10, M12 and M15 transistors are identical
and biased at the same drain current, IO , their gate-source voltages are equal, so:
rffiffiffiffiffiffiffi
2IO
VO ¼ VT þ (3.42)
K

For the circuit presented in Fig. 3.11, it is possible to write:

V1
V2 ¼ VSG2
VO (3.43)
198 3 Squaring Circuits

VDD

M1 M2 M7 M8

VO VO
M4 M9
V1 V2
M3 M10
M13 M14
2IO IOUT2 M11
M6 IOUT1
IO
IOUT
M5 M12 M15

Fig. 3.12 Squaring circuit (4) based on PR 3.2 – complete implementation

and:

V1
V2 ¼ VO
VSG1 (3.44)

resulting:

VSG1 ¼ VO
ðV1
V2 Þ (3.45)

and:

VSG2 ¼ VO þ ðV1
V2 Þ (3.46)

The output current can be expressed as follows:

K K
IOUT ¼ IOUT1 þ IOUT2
2IO ¼ ðVSG1
VT Þ2 þ ðVSG2
VT Þ2
2IO (3.47)
2 2

So:

K K
IOUT ¼ ½ðVO
VT Þ
ðV1
V2 Þ2 þ ½ðVO
VT Þ þ ðV1
V2 Þ2
2IO
2 2
¼ K ðVO
VT Þ2 þ K ðV1
V2 Þ2
2IO ð3:48Þ

Replacing (3.42) in (3.48), it results:

IOUT ¼ K ðV1
V2 Þ2 (3.49)

3.2 Analysis and Design of Squaring Circuits 199

VDD

M7 M1 M2 M8
V1 V2

M3 M6

M4 M5

IO IOUT1 IOUT2 IO

2IO IOUT

Fig. 3.13 Squaring circuit (5) based on PR 3.2

A current squaring circuit based on the same mathematical principle, using a

translinear loop, is presented in Fig. 3.13 [8].
The translinear loop containing M2, M3, M4 and M7 transistors has the following
characteristic equation:
rffiffiffiffi
2 pffiffiffiffiffi pffiffiffiffi
V1
V2 ¼ 2VGS ðIO Þ
2VGS ðI1 Þ ¼ 2 IO
I1 (3.50)
K

resulting:
rffiffiffiffiffiffiffiffi
K KIO
IOUT1 ¼ IO þ ðV1
V2 Þ2
ðV1
V 2 Þ (3.51)
8 2

Similarly, analyzing the translinear loop containing M1, M5, M6 and M8

transistors, it results:
rffiffiffiffiffiffiffiffi
K KIO
IOUT2 ¼ IO þ ðV1
V2 Þ2 þ ðV1
V 2 Þ (3.52)
8 2

The output current of the circuit presented in Fig. 3.13 will have the following
expression:

K
IOUT ¼ IOUT1 þ IOUT2
2IO ¼ ðV1
V2 Þ2 (3.53)
4
200 3 Squaring Circuits

2IO IOUT

IOUT1 IO IO IOUT2

2IO
V1 M5 M6 M7 M8 V2

IOUT1+IO IOUT2+IO

IO IO

M1 M2 M3 M4
V

2IO 2IO

Fig. 3.14 Squaring circuit (6) based on PR 3.2

A realization of a voltage squaring circuit using the computation of the input

potentials arithmetical mean is presented in Fig. 3.14.
As M1–M4 transistors implement an arithmetical mean circuit, the expression of
V potential will be:

V1 þ V2
V¼ (3.54)
2

For M5–M6 differential amplifier, the differential input voltage can be expressed
as follows:
rffiffiffiffi
2 pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffi
V1
V ¼ VGS5
VGS6 ¼ IOUT1
IO (3.55)
K

Replacing (3.54) in (3.55), it results:

rffiffiffiffiffiffiffiffi
KIO K
IOUT1 ¼ IO þ ðV1
V2 Þ þ ðV1
V2 Þ2 (3.56)
2 8
3.2 Analysis and Design of Squaring Circuits 201

2IO IOUT

IOUT1 IO IO IOUT2

V1 M1 M2 M3 M4 V2

Fig. 3.15 Squaring circuit (7) based on PR 3.2

Similarly, for M7–M8 differential amplifier, it can be obtained:

rffiffiffiffiffiffiffiffi
KIO K
IOUT2 ¼ IO
ðV1
V2 Þ þ ðV1
V2 Þ2 (3.57)
2 8

The output current of the squaring circuit presented in Fig. 3.14 will be:

K
IOUT ¼ IOUT1 þ IOUT2
2IO ¼ ðV1
V2 Þ2 (3.58)
4
A voltage squaring circuit containing two differential amplifiers is presented in
Fig. 3.15 [9].
For M1–M2 differential amplifier, the differential input voltage can be expressed
as follows:
rffiffiffiffi
2 pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffi
V1
V2 ¼ IOUT1
IO (3.59)
K

resulting:

pffiffiffiffiffiffiffiffiffiffi K
IOUT1 ¼ IO þ 2KIO ðV1
V2 Þ þ ðV1
V2 Þ2 (3.60)
2

Similarly, for M3–M4 differential amplifier, the expression of I2 current will be:

pffiffiffiffiffiffiffiffiffiffi K
IOUT2 ¼ IO
2KIO ðV1
V2 Þ þ ðV1
V2 Þ2 (3.61)
2
202 3 Squaring Circuits

VDD

2IO IOUT

IOUT1 IO IOUT2

VC + VIN M1 VC M3 M2 VC - VIN

IO

- VDD

Fig. 3.16 Squaring circuit (8) based on PR 3.2

The output current of the squaring circuit presented in Fig. 3.15 is:

IOUT ¼ IOUT1 þ IOUT2
2IO ¼ K ðV1
V2 Þ2 (3.62)

The circuit presented in Fig. 3.16 [5] is used for obtaining the squaring of a
differential input voltage, VIN .
The difference between the gate-source voltages of M1 and M3 transistors can
be expressed as follows:

VGS1
VGS3 ¼ ðVC þ VIN Þ
VC (3.63)

For a biasing in saturation of all MOS transistors from Fig. 3.16, it results:
rffiffiffiffi
2 pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffi
VIN ¼ IOUT1
IO (3.64)
K

So, the expression of IOUT1 current will be:

K 2 pffiffiffiffiffiffiffiffiffiffi
IOUT1 ¼ IO þ VIN þ 2KIO VIN (3.65)
2
Similarly, computing the difference between the gate-source voltages of M2–M3
transistors, it results:

K 2 pffiffiffiffiffiffiffiffiffiffi
IOUT2 ¼ IO þ VIN
2KIO VIN (3.66)
2
3.2 Analysis and Design of Squaring Circuits 203

2IO

V2 V1
M3 M4 2IC
IOUT

IOUT1 VDD IOUT2

IC
M1 M5 M6 M7 M8 M2
VC

M9
2IO 2IO

Fig. 3.17 Squaring circuit (9) based on PR 3.2

The output current for the circuit presented in Fig. 3.16 is:

IOUT ¼ IOUT1 þ IOUT2
2IO ¼ KVIN

2
(3.67)

The circuit presented in Fig. 3.17 [10] implements the squaring function using
PR 3.2.
The current sources and the circuit’s connections impose the following relation
between the currents from the circuit:

ID3 þ ID6 ¼ ID4 þ ID7 ¼ ID3 þ ID4 ¼ 2IO (3.68)

resulting ID6 ¼ ID4 and ID7 ¼ ID3 . The translinear loops containing M1, M5, M6
and M2, M7, M8 transistors have the following characteristic equations:

VGS1
VC ¼ VGS5
VGS6 (3.69)

and:

VGS2
VC ¼ VGS8
VGS7 (3.70)

resulting:
rffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffi
2IOUT1 2 pffiffiffiffiffiffi pffiffiffiffiffiffi
VT þ
VC ¼ ID3
ID4 (3.71)
K K

and:
rffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffi
2IOUT2 2 pffiffiffiffiffiffi pffiffiffiffiffiffi
VT þ
VC ¼ ID4
ID3 (3.72)
K K
204 3 Squaring Circuits

The IOUT1 and IOUT2 output currents can be expressed as follows:

"rffiffiffiffi #2
K 2 pffiffiffiffiffiffi pffiffiffiffiffiffi
IOUT1 ¼ ID3
ID4 þ ðVC
VT Þ (3.73)
2 K

and:

"rffiffiffiffi #2
K 2 pffiffiffiffiffiffi pffiffiffiffiffiffi
IOUT2 ¼ ID4
ID3 þ ðVC
VT Þ (3.74)
2 K

or:

pffiffiffiffiffiffi pffiffiffiffiffiffi2 pffiffiffiffiffiffipffiffiffiffiffiffi pffiffiffiffiffiffi K

IOUT1 ¼ ID3
ID4 þ 2K ID3
ID4 ðVC
VT Þ þ ðVC
VT Þ2 (3.75)
2

and:

pffiffiffiffiffiffi pffiffiffiffiffiffi2 pffiffiffiffiffiffipffiffiffiffiffiffi pffiffiffiffiffiffi K

IOUT2 ¼ ID4
ID3 þ 2K ID4
ID3 ðVC
VT Þ þ ðVC
VT Þ2 (3.76)
2

The differential input voltage of the circuit is equal with the difference between
two source-gate voltages:
rffiffiffiffi
2 pffiffiffiffiffiffi pffiffiffiffiffiffi
V1
V2 ¼ VSG3
VSG4 ¼ ID3
ID4 (3.77)
K

From (3.75), (3.76) and (3.77), the expressions of the output currents become:

K K
IOUT1 ¼ ðV1
V2 Þ2 þ K ðV1
V2 Þ ðVC
VT Þ þ ðVC
VT Þ2 (3.78)
2 2

and:

K K
IOUT2 ¼ ðV1
V2 Þ2
K ðV1
V2 Þ ðVC
VT Þ þ ðVC
VT Þ2 (3.79)
2 2

As VC voltage is equal with the gate-source voltage of M9 transistor, which is

biased at the constant current, IC , the previous relations become:

K pffiffiffiffiffiffiffiffiffiffi
IOUT1 ¼ ðV1
V2 Þ2 þ 2KIC ðV1
V2 Þ þ IC (3.80)
2
3.2 Analysis and Design of Squaring Circuits 205

Fig. 3.18 Squaring circuit VDD

(10) based on PR 3.2

2IO IOUT
IO

M
IOUT1 IO IOUT2

M1 M3 M2
V1 V2
V

-VDD

and:

K pffiffiffiffiffiffiffiffiffiffi
IOUT2 ¼ ðV1
V2 Þ2
2KIC ðV1
V2 Þ þ IC (3.81)
2
The sum of the output currents will be:

IOUT1 þ IOUT2 ¼ K ðV1
V2 Þ2 þ 2IC (3.82)

So, the output current of the circuit presented in Fig. 3.17 will be proportional
with the square of the differential input voltage:

IOUT ¼ IOUT1 þ IOUT2
2IC ¼ K ðV1
V2 Þ2 (3.83)

A simple realization of a voltage squaring circuit exploits the second mathemat-

ical principle, being based on a differential amplifier having the sources of
transistors connected to a potential fixed by a constant current. The realization of
the circuit is presented in Fig. 3.18 [11]. The “M” block represents a circuit that
computes the arithmetical mean of V1 and V2 input potentials. A possible imple-
mentation of this block is presented in Fig. 3.19 [11]. The FGMOS transistor is
functionally equivalent with the “M” block and M3 transistor
The output currents of the differential amplifier can be expressed as follows:

K
IOUT1 ¼ ðV1
V
VT Þ2 (3.84)
2
206 3 Squaring Circuits

Fig. 3.19 Squaring circuit VDD

(11) based on PR 3.2

2IO IOUT
IO

IOUT1 IO IOUT2

M1 M3 M2
V1 V2
V

-VDD

and:

K
IOUT2 ¼ ðV2
V
VT Þ2 (3.85)
2
while V potential is imposed by V1 and V2 potentials and by M3 transistor, biased at
a constant drain current, IO :
 2 rffiffiffiffiffiffiffi
K V 1 þ V2 V1 þ V2 2IO
IO ¼
V
VT )V¼
VT
(3.86)
2 2 2 K

The expressions of the differential amplifier output currents becomes:

rffiffiffiffiffiffiffi!2
K V1
V2 2IO
IOUT1 ¼ þ (3.87)
2 2 K

and:

rffiffiffiffiffiffiffi!2
K V1
V2 2IO
IOUT2 ¼
þ (3.88)
2 2 K

The sum of the output currents will contain a term proportional with the square
of the differential input voltage:

K
IOUT1 þ IOUT2 ¼ 2IO þ ðV1
V2 Þ2 (3.89)
4
3.2 Analysis and Design of Squaring Circuits 207

VDD

IOUT

M4 M6
V1 V2
I1 I2
I3
M1 M3 M2
V12 V21
K 2K K
V
I1+ I2 + I3
M5 M7
V2 V1

-VDD

Fig. 3.20 Squaring circuit (12) based on PR 3.2

The output current of the entire circuit from Fig. 3.19 will be proportional with
ðV1
V2 Þ2 :

K
IOUT ¼ IOUT1 þ IOUT2
2IO ¼ ðV1
V2 Þ2 (3.90)
4
The voltage squarer presented in Fig. 3.20 [12, 13] is based on the second
mathematical principle and uses a symmetrical structure, M1–M2.
The output current expression has a linear dependence on the drain currents of
M1, M2 and M3 transistors:

IOUT ¼ I1 þ I2
I3 (3.91)

Considering a biasing in saturation of all MOS devices from Fig. 3.20, the
previous currents will have the following expressions:

K
I1 ¼ ðV12
V
VT Þ2 (3.92)
2

K
I2 ¼ ðV21
V
VT Þ2 (3.93)
2

2K
I3 ¼ ð
V
VT Þ2 (3.94)
2
208 3 Squaring Circuits

VDD

kO kO
M4 IOUT M6
V1 V2
k k
M1 M3 M2
V12 K 2K K V21

I1 V I3 I2
VO kO kO VO
M5 M7
V2 k I1+ I2+ I3 k V1

-VDD

Fig. 3.21 Squaring circuit (13) based on PR 3.2

Because M4 and M5 transistors are identical and biased at the same drain
current, their gate-source voltages will be equal, so V1
V12 ¼ V2 , resulting:

V12 ¼ V1
V2 (3.95)

Similarly:

V21 ¼ V2
V1 (3.96)

From (3.91) – (3.96), the output current can be expressed as:

K K
IOUT ¼ ½ðV1
V2 Þ
ðV þ VT Þ2 þ ½ðV2
V1 Þ
ðV þ VT Þ2
2 2
2K 2 K

ðV þ VT Þ ¼ ðV1
V2 Þ½ðV1
V2 Þ
2ðV þ VT Þ
2 2
K
þ ðV2
V1 Þ½ðV2
V1 Þ
2ðV þ VT Þ ¼ K ðV1
V2 Þ2 (3.97)
2

An alternate implementation [14] of the voltage squaring circuit uses FGMOS

transistors for extending the range of the minimal supply voltage (Fig. 3.21). The
ground potential is replaced, in this case, with
VDD . All FGMOS transistors are
identical and they have different weights of their inputs, kO and k.
The drain currents of M4 and M5 transistors are equal, so:
 2  2
K kO VDD þ kV1 K kO VO þ kV2

V12
VT ¼ þ VDD
VT (3.98)
2 k þ kO 2 k þ kO
3.2 Analysis and Design of Squaring Circuits 209

resulting:

kðV1
V2 Þ kVDD þ kO VO
V12 ¼
(3.99)
k þ kO k þ kO

Similarly:

kðV1
V2 Þ kVDD þ kO VO
V21 ¼

(3.100)
k þ kO k þ kO

equivalent with a voltage shifting with ðkVDD þ kO VO Þ=ðk þ kO Þ of the differential

V1
V2 input voltage. In order to cancel out this shifting, the VO biasing voltage,
must be chosen to have the following expression:

k
VO ¼
VDD (3.101)
kO

resulting, in this hypothesis:

kðV1
V2 Þ
V12 ¼ (3.102)
k þ kO

and:

k ðV1
V2 Þ
V21 ¼
(3.103)
k þ kO

The expression of the output current will be:

K
IOUT ¼ I1 þ I2
I3 ¼ðV12
V
VT Þ2
2
K 2K
þ ðV21
V
VT Þ2
ð
V
VT Þ2 (3.104)
2 2

equivalent with:
2
K kðV1
V2 Þ
IOUT ¼
V
VT þ
2 k þ kO
2
K kðV1
V2 Þ 2K
þ

V
VT þ ð
V
VT Þ2 (3.105)
2 k þ kO 2
210 3 Squaring Circuits

IOUT2 IOUT1
VDD

1 2 2 1

M1 M2 M3 M4 M5 M6
V1 -V1
I V V’ I’

M7 M8
VC
-VDD

Fig. 3.22 Squaring circuit (14) based on PR 3.2

So:

K k ðV1
V 2 Þ k ðV1
V 2 Þ
IOUT ¼
2V
2VT
2 k þ kO k þ kO
(3.106)
K kðV1
V2 Þ kðV1
V2 Þ



2V
2VT
2 k þ kO k þ kO

resulting:

K k2
IOUT ¼ ðV1
V2 Þ2 (3.107)
ðk þ kO Þ2

The circuit presented in Fig. 3.22 [15] also represents a voltage squaring circuit
based on PR 3.2.
The circuit connections and the current mirrors from the circuit impose zero
values for I and I 00 currents. Thus, because M3 and M7 transistors are identical and
they are biased at the same drain current, their gate-source voltages will be equal, so
V ¼
VC
VDD and, similarly, V 0 ¼
VC
VDD . The output differential current
of the voltage squaring circuit can be expressed as follows:

IOUT1
IOUT2 ¼ ID1 þ ID6
ID3
ID4 (3.108)

resulting:

K K
ðV1
V
VT Þ2 þ ð
V1
V 0
VT Þ
2
IOUT1
IOUT2 ¼
2 2
2K K

ð
V
VT Þ2 ¼ ðV1 þ VC þ VDD
VT Þ2
2 2
K 2K
þ ð
V1 þ VC þ VDD
VT Þ2
ðVC þ VDD
VT Þ2 (3.109)
2 2
3.2 Analysis and Design of Squaring Circuits 211

VDD
VO+V1 VO-V1 VO VO
M1 M2 M3 M4

IOUT

M5 M6

Fig. 3.23 Squaring circuit (15) based on PR 3.2

resulting:
K
IOUT1
IOUT2 ¼ V1 ðV1 þ 2VC þ 2VDD
2VT Þ
2
K

V1 ð
V1 þ 2VC þ 2VDD
2VT Þ ¼ KV12 (3.110)
2
So, the output differential current will be proportional with the square of the
input voltage.
The circuit presented in Fig. 3.23 [16] computes an output current proportional
with the square of the input voltage.
The output current can be expressed as follows:

K
IOUT ¼ ID3 þ ID4
ID1
ID2 ¼ 2 ðVDD
VO
VT Þ2
2
K K

ðVDD
VO
V1
VT Þ2
ðVDD
VO þ V1
VT Þ2 (3.111)
2 2
resulting:

K
IOUT ¼ V1 ðVDD
2VO
2VT
V1 Þ
2
K

V1 ðVDD
2VO
2VT þ V1 Þ ¼
KV12 (3.112)
2
A voltage squaring circuit can be obtained using the circuit presented in
Fig. 3.24 [17].
As M1 and M2 transistors are biased at IO drain currents, VA and VB potentials
can be expressed as follows:
rffiffiffiffiffiffiffi
2IO
VA ¼ V2
VT
(3.113)
K
212 3 Squaring Circuits

VDD

IO IO
VC VC

2IO IOUT

V2 M1 M2
IOUT1 IOUT2 V1

V3 M3 M4
V4

VA VB

IO + IOUT1 IO + IOUT2

Fig. 3.24 Squaring circuit (16) based on PR 3.2

and:
rffiffiffiffiffiffiffi
2IO
VB ¼ V1
VT
(3.114)
K

The expressions of IOUT1 and IOUT2 currents will be:

K
IOUT1 ¼ ðV3
VA
VT Þ2 (3.115)
2

and:

K
IOUT2 ¼ ðV4
VB
VT Þ2 (3.116)
2

Replacing (3.113) and (3.114) in (3.115) and (3.116), it results:

rffiffiffiffiffiffiffi!2
K 2IO
IOUT1 ¼ V3
V2 þ (3.117)
2 K
3.2 Analysis and Design of Squaring Circuits 213

and:

rffiffiffiffiffiffiffi!2
K 2IO
IOUT2 ¼ V4
V1 þ (3.118)
2 K

The input potentials are chosen to have both common-mode and differential-
mode components:

V1 ¼ VC
Vi1 (3.119)

V2 ¼ VC þ Vi1 (3.120)

V3 ¼ VC þ Vi2 (3.121)

and:

V4 ¼ VC
Vi2 (3.122)

resulting that the output current of the circuit presented in Fig. 3.24 will have the
following expression:

rffiffiffiffiffiffiffi!2
K 2IO
IOUT ¼ IOUT1 þ IOUT2
2IO ¼ Vi2
Vi1 þ
2 K
rffiffiffiffiffiffiffi!2
K 2IO
þ Vi1
Vi2 þ
2IO ¼ K ðVi1
Vi2 Þ2 (3.123)
2 K

A voltage squaring circuit using FGMOS transistors is presented in Fig. 3.25 [18].
Considering that FGMOS transistors from Fig. 3.25 have different inputs, as it is
shown in the figure, the expressions of their drain currents will be:
 2
K V1 þ VPOL1
IOUT1 ¼
V
VT (3.124)
2 2
 2
K V2 þ VPOL2
IOUT2 ¼
V
VT (3.125)
2 2

and:
 2
K V1 þ V2 þ 2VPOL3
IO ¼
V
VT (3.126)
2 4
214 3 Squaring Circuits

VDD
IO
IM IOUT

IOUT2 IOUT1
VPOL2 VPOL3 VPOL1
1 1 1
M2 1/2 M3 M1 1
V2 1 1/2 V1
V

Fig. 3.25 Squaring circuit (17) based on PR 3.2

Replacing in (3.124) and (3.125) the expression of V potential from (3.126), it results:
rffiffiffiffiffiffiffi!2
K V1
V2 þ 2VPOL1
2VPOL3 2IO
IOUT1 ¼ þ (3.127)
2 4 K

and:

rffiffiffiffiffiffiffi!2
K V2
V1 þ 2VPOL2
2VPOL3 2IO
IOUT2 ¼ þ (3.128)
2 4 K

Designing a symmetrical structure (VPOL1 ¼ VPOL2 ), the output current will have
the following expression:

IOUT ¼ IOUT1 þ IOUT2
IM

"  rffiffiffiffiffiffiffi!#2
K V1
V2 VPOL1
VPOL3 2IO
¼ þ þ
2 4 2 K
"  r ffiffiffiffiffiffiffi!#2
K V1
V2 VPOL1
VPOL3 2IO
þ
þ þ
IM (3.129)
2 4 2 K

resulting:

rffiffiffiffiffiffiffi!2
K VPOL1
VPOL3 2IO
IOUT ¼ ðV1
V2 Þ2 þ K þ
IM (3.130)
16 2 K
3.2 Analysis and Design of Squaring Circuits 215

Fig. 3.26 Squaring circuit VDD

(1) based on PR 3.3

IOUT

I3
I1 I2
M1 M3 M2
V1 K 2K K V2

For obtaining an output current proportional with the square of the differential
input voltage, IM current must have the following expression:

rffiffiffiffiffiffiffi!2
VPOL1
VPOL3 2IO
IM ¼ K þ (3.131)
2 K

In this case, it results:

K
IOUT ¼ ðV1
V2 Þ2 (3.132)
16

3.2.1.3 Squaring Circuits Based on the Third Mathematical

Principle (PR 3.3)

An alternate implementation of a voltage squaring circuit using a FGMOS transis-

tor is presented in Fig. 3.26 [47].
The output current expression has a linear dependence on the drain currents of
M1, M2 and M3 transistors:

IOUT ¼ I1 þ I2
I3 (3.133)

Considering a biasing in saturation of all MOS devices from Fig. 3.26, IOUT
current will have the following dependence on the differential input voltage
V1
V 2 :
 2
K 2 K 2 2K V1 þ V2
IOUT ¼ ðV1
VT Þ þ ðV2
VT Þ

VT (3.134)
2 2 2 2
216 3 Squaring Circuits

VDD

IOUT

I3
I1 I3 I2

M1 M3 M2
V1 K 2K K V2

2K

-VDD

Fig. 3.27 Squaring circuit (2) based on PR 3.3

resulting:

K
IOUT ¼ ðV1
V2 Þ2 (3.135)
4
Another possible implementation of a voltage squarer circuit using FGMOS
transistors is based on the perfect symmetrical structure presented in Fig. 3.27 [19, 20].
The output current expression has a linear dependence on the drain currents of
M1, M2 and M3 transistors:

IOUT ¼ I1 þ I2
I3 (3.136)

For a biasing in saturation of all MOS devices from Fig. 3.27, the previous
currents will have the following expressions:

K
I1 ¼ ðV1
V
VT Þ2 (3.137)
2
K
I2 ¼ ðV2
V
VT Þ2 (3.138)
2
 2
2K V1 þ V2
I3 ¼
V
VT (3.139)
2 2

From the previous relations, it results a quadratic dependence of the IOUT output
current on the differential input voltage, V1
V2 :

K
IOUT ¼ ðV1
V2 Þ2 (3.140)
4
3.2 Analysis and Design of Squaring Circuits 217

VDD

IO
V
V1 M3 M4 V2
M1 M2

VDD

IOUT

I7
I5 I6 M7
M5 M6
2K
K K

Fig. 3.28 Squaring circuit (3) based on PR 3.3

The realization of the voltage squaring circuit presented in Fig. 3.28 [21] uses the
arithmetical mean of the input potentials, computed by M1–M4 transistors.
Because ID1 þ ID2 ¼ ID2 þ ID3 ¼ ID3 þ ID4 ¼ IO , it results that ID1 ¼ ID3 and
ID2 ¼ ID4 . So, as M1–M4 transistors are identical, it is possible to conclude that
VSG1 ¼ VSG3 and VSG2 ¼ VSG4 . So:

V
V1 ¼ VSG1
VSG2 ¼ VSG3
VSG4 ¼ V2
V (3.141)

resulting:

V1 þ V2
V¼ (3.142)
2

The output current of the voltage squaring circuit will be linearly dependent on
the drain currents of M5–M7 transistors:

IOUT ¼ I5 þ I6
I7 (3.143)
218 3 Squaring Circuits

VDD

M6 M8
1 1
VM V VN
M1 M2 M3 M4
V1 M5 M7 V2
K K
M9
2K
IOUT

-VDD

Fig. 3.29 Squaring circuit (4) based on PR 3.3

The expression of the output current will be:

 2
K 2 K 2 2K V1 þ V2
IOUT ¼ ðV1
VT Þ þ ðV2
VT Þ

VT (3.144)
2 2 2 2

In conclusion:

K
IOUT ¼ ðV1
V2 Þ2 (3.145)
4
The squaring circuit presented in Fig. 3.29 [22] is also based on the computation of
the arithmetical mean of input potentials using four MOS transistors (M1–M4). So:

VM þ VN
V¼ (3.146)
2
The gate-source voltages of M5 and M6 transistors are equal, as they are
identical and biased at the same drain current, so:

V1 þ VDD
VM ¼ (3.147)
2

and, similarly:

V2 þ VDD
VN ¼ (3.148)
2

resulting:

V1 þ V2 þ 2VDD
V¼ (3.149)
4
3.2 Analysis and Design of Squaring Circuits 219

The output differential current will have the following expression:

2K
IOUT ¼ ID9
ID5
ID7 ¼ ðVDD
V
VT Þ2
2
K K

ðVM
V1
VT Þ2
ðVN
V2
VT Þ2 (3.150)
2 2

So:
 2
2K 2VDD
V1
V2
IOUT ¼
VT
2 4
 2  2
K VDD
V1 K VDD
V2


VT

VT (3.151)
2 2 2 2

equivalent with:
 
K V1
V2 4VDD
3V1
V2
IOUT ¼
2VT
2 4 4
 
K V1
V2 4VDD
3V2
V1


2VT (3.152)
2 4 4

It results that the output current of the circuit is proportional with the square of
the differential input voltage:

K
IOUT ¼
ðV1
V2 Þ2 (3.153)
16

3.2.1.4 Squaring Circuits Based on Different Mathematical

Principles (PR 3. Da)

For the squaring circuit presented in Fig. 3.30 [23], the differential input voltage of
the circuit can be expressed as follows:
rffiffiffiffi
2 pffiffiffiffi pffiffiffiffi
V1
V2 ¼ VGS1
VGS2 ¼ I1
I2 (3.154)
K

It results:

pffiffiffiffiffiffiffiffi K
I1 þ I2 ¼ 2 I1 I2 þ ðV1
V2 Þ2 (3.155)
2
220 3 Squaring Circuits

VDD

I1 I2

V1 M1 M2 V2 I2 I2 I1 IP
I1 I2
M4
I1 M8 IOUT
M3
IP
VBIAS M5 M6 M7 M9 M10 M11

Fig. 3.30 Squaring circuit (1) based on PR 3.Da

The translinear loop containing M3, M4, M8 and M9 transistors has the follow-
ing characteristic equation:

VGS3 þ VGS4 ¼ VGS8 þ VGS9 (3.156)

equivalent with:
pffiffiffiffi pffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
I1 þ I2 ¼ I1 þ I2 þ IP (3.157)

It was considered that ðW=LÞ8 ¼ ðW=LÞ9 ¼ 4ðW=LÞ3 ¼ 4ðW=LÞ4 . So:

pffiffiffiffiffiffiffiffi
IP ¼ 2 I1 I2 (3.158)

The output current of the circuit can be expressed as follows:

K
IOUT ¼ I1 þ I2
IP ¼ ðV1
V2 Þ2 (3.159)
2

The squaring circuit presented in Fig. 3.31 is realized using a parallel connection
of two differential amplifiers, M1–M3 and M2–M4, their differential output
currents being expressed as follows:

K K
I1
I3 ¼ ðV1
VX
VT Þ2
ðV2
VX
VT Þ2
2 2
K
¼ ðV1
V2 Þ ðV1 þ V2
2VX
2VT Þ (3.160)
2
3.2 Analysis and Design of Squaring Circuits 221

VDD

IO
IOUT

VS

I1 I4 I5 I6 I2 I3
V1 M1 M4 M2 M3 V2
VY
VX
I4 I3
IO IO

-VDD

Fig. 3.31 Squaring circuit (2) based on PR 3.Da

and:

K K
I2
I4 ¼ ðV2
VY
VT Þ2
ðV1
VY
VT Þ2
2 2
K
¼ ðV2
V1 ÞðV1 þ V2
2VY
2VT Þ (3.161)
2
resulting that the output current of the differential amplifier presented in Fig. 3.31
will have the following expression:

K
IOUT ¼ ðI1
I3 Þ þ ðI2
I4 Þ ¼ ðV1
V2 Þð2VY
2VX Þ
2
¼ K ðV1
V2 ÞðVY
VX Þ (3.162)

Between the currents from the circuit it exists the following linear relations:

I1 þ I5 ¼ IO (3.163)

I2 þ I6 ¼ IO (3.164)

and:

I5 þ I6 ¼ IO (3.165)

resulting I1 ¼ I6 and I2 ¼ I5 . So:

V1
VX ¼ VS
VY (3.166)
222 3 Squaring Circuits

Fig. 3.32 Asymmetrical

differential structure I1 I2

M1 M2
V1 K nK V2

IO

and:

V2
VY ¼ VS
VX (3.167)

equivalent with:

VX
VY ¼ V1
VS (3.168)

and:

VX
VY ¼ VS
V2 (3.169)

So:

V1 þ V2
VS ¼ (3.170)
2

and:

V1 þ V2 V1
V2
VX
VY ¼ V1
¼ (3.171)
2 2

Replacing (3.171) in (3.162), the output current will be proportional with the
square of the differential input voltage:

K
IOUT ¼
ðV1
V2 Þ2 (3.172)
2

A method for designing a voltage squaring circuit is based on a differential

amplifier (Fig. 3.32) [24, 25] having a controllable asymmetry between the
geometries of two composing transistors. This difference between the aspect ratios
of MOS transistors will introduce in the output currents of the differential amplifier
a term proportional with the squaring of the differential input voltage.
3.2 Analysis and Design of Squaring Circuits 223

Noting with V ¼ V1
V2 the differential input voltage, it can be expressed as

follows:
rffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2I1 2ðIO
I1 Þ
V ¼ VGS1
VGS2 ¼
(3.173)
K nK

resulting:
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
K 2 IO
I1 I1 ðIO
I1 Þ
V ¼ I1 þ
2 (3.174)
2 n n

The expression of the I1 unknown current can be obtained solving the following
second-order equation, derived from (3.174):
" 2 #    2
n
1 4 n
1 IO KV 2 4IO IO KV 2
2
I1 þ þ I1 2

þ
¼0
n n n n 2 n n 2
(3.175)

So:

IO nðn
1Þ nV pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
I1 ¼ þ KV 2 þ 2KIO ðn þ 1Þ
K 2 nV 2 (3.176)
n þ 1 2ðn þ 1Þ 2
ðn þ 1Þ2

and:

nIO nð n
1Þ nV pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
ffi
I2 ¼ IO
I1 ¼
KV 2
2KIO ðn þ 1Þ
K 2 nV 2 (3.177)
n þ 1 2ð n þ 1Þ2
ð n þ 1Þ 2

The complete realization of a voltage squaring circuit uses a cross-coupling of

two differential amplifiers having controllable asymmetries between their
geometries, M1–M2 and M3–M4 (Fig. 3.33) [24, 25].
Using (3.176) and (3.177), it results:

nIO nðn
1Þ
IOUT 0 ¼ ID2 þ ID4 ¼
KV 2
n þ 1 2ðn þ 1Þ2
nV pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi nIO nðn
1Þ

2KIO ðn þ 1Þ
K 2 nV 2 þ
KV 2
ð n þ 1Þ 2 n þ 1 2ðn þ 1Þ2
nV pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2nIO nðn
1Þ
þ 2KIO ðn þ 1Þ
K 2 nV 2 ¼
KV 2 (3.178)
ðn þ 1Þ 2 n þ 1 ðn þ 1Þ2

So:

2nIO nðn
1Þ
IOUT ¼
IOUT 0 ¼ KV 2 (3.179)
nþ1 ð n þ 1Þ 2
224 3 Squaring Circuits

VDD IOUT
2nIO /(n+1)

IOUT’

M1 M2 M3 M4
K nK K nK
V

IO IO

Fig. 3.33 Squaring circuit (3) based on PR 3.Da

3.2.2 Design of Current Squaring Circuits

The current squaring circuits are grouped in five classes, corresponding to the last
five mathematical principles (PR 3.5 – PR 3.Db).

3.2.2.1 Squaring Circuits Based on the Fifth Mathematical

Principle (PR 3.5)

A realization of a current squaring circuit using the fifth mathematical principle is

presented in Fig. 3.34 [26]. The equation on the translinear loop containing M1–M4
transistors can be written as:

VGS1 þ VGS2 ¼ VGS3 þ VGS4 (3.180)

Because M1 and M2 transistors are biased at IO drain current, M3 – at I þ IIN

current, while M4 is working at I
IIN drain current, for a biasing in saturation of
all MOS transistors from the circuit, the previous relation becomes:
rffiffiffiffiffiffiffi! rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi! rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi!
2IO 2ðI þ IIN Þ 2ðI
IIN Þ
2 VT þ ¼ VT þ þ VT þ (3.181)
K K K
pffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffi
So, 2 IO ¼ I þ IIN þ I
IIN , resulting:
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
4IO ¼ 2I þ 2 I2
IIN 2 (3.182)
3.2 Analysis and Design of Squaring Circuits 225

VDD

4IO

I
M3 IOUT

M1
M4
IO
IIN IIN IIN I I 4I
M2

Fig. 3.34 Squaring circuit (1) based on PR 3.5

equivalent with:

4IO2 þ I2
4IO I ¼ I2
IIN

2
(3.183)

The I current can be expressed as follows:

2
IIN
I ¼ IO þ (3.184)
4IO

The output current linearly depends on the currents from the circuit as follows:

2
IIN
IOUT ¼ 4I
4IO ¼ (3.185)
IO

An alternative implementation of a current squaring circuit using the same

principle is presented in Fig. 3.35.
The translinear loop containing M1–M4 transistors has the following character-
istic equation:

VGS1 þ VGS4 ¼ VGS2 þ VGS3 (3.186)

resulting:
pffiffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 IO ¼ IO1 þ IIN þ IO1 (3.187)
226 3 Squaring Circuits

Fig. 3.35 Squaring circuit

(2) based on PR 3.5 IO IIN + IO1

M1 M2

IO + IIN + IO1

IO1 IO

M3 M4

IO + IO1

equivalent with the following dependence of IO1 current on the IIN input current and
on the reference current, IO :

IIN I2
IO1 ¼ IO
þ IN (3.188)
2 16IO

The entire implementation in CMOS technology of the previous current squaring

circuit is presented in Fig. 3.36.
Designing a linear relation between the currents from the previous circuit:

IOUT ¼ 16IO1
16IO þ 8IIN (3.189)

it results that the output current will be proportional with the square of the input current:
2
IIN
IOUT ¼ (3.190)
IO

The circuit presented in Fig. 3.37 [27, 28] implements the current squaring
function. The core of the circuit is represented by the translinear loop realized
using M1–M4 transistors. The characteristic equation of the loop is:

VGS1 þ VGS2 ¼ VGS3 þ VGS4 (3.191)

3.2 Analysis and Design of Squaring Circuits 227

VDD

K
8K K
IIN
K 16K
IO IIN
IO1 16 IO1 8IIN

IOUT
16 IO

Fig. 3.36 Squaring circuit (3) based on PR 3.5

VDD

IO
M3

M1 IIN
IOUT IIN /2

IO
M2 M4 M5

Fig. 3.37 Squaring circuit (4) based on PR 3.5

resulting:
rffiffiffiffiffiffiffi! rffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2IO 2ID5 2ðID5
IIN Þ
2 VT þ ¼ VT þ þ VT þ (3.192)
K K K

equivalent with:
pffiffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 IO ¼ ID5 þ ID5
IIN (3.193)
228 3 Squaring Circuits

IOUT1 IOUT2

M1 M4
VC VC

I
IIN

M2 M3 M6 M5

Fig. 3.38 Squaring circuit (5) based on PR 3.5

Squaring the previous relation, it results:

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
4IO ¼ 2ID5
IIN þ 2 ID5 ðID5
IIN Þ (3.194)

After computations, it can be obtained:

IIN I2
ID5 ¼ IO þ þ IN (3.195)
2 16IO

The output current can be expressed as follows:

IIN I2
IOUT ¼ ID5
IO
¼ IN (3.196)
2 16IO

A current squaring circuit dependent on technological parameters is presented in

Fig. 3.38 [29].
For the left part of the circuit, it can write that:

VC ¼ VGS1 þ VGS2 (3.197)

or:
rffiffiffiffiffi! rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi!
2I 2ðI
IIN Þ
VC ¼ VT þ þ VT þ (3.198)
K K
3.2 Analysis and Design of Squaring Circuits 229

resulting:
rffiffiffiffi
pffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffi K
I þ I
IIN ¼ ðVC
2VT Þ (3.199)
2

So:
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2I
IIN þ 2 IðI
IIN Þ ¼ A (3.200)

where:

K
A¼ ðVC
2VT Þ2 (3.201)
2
It results:

2
A IIN IIN
I¼ þ þ (3.202)
4 4A 2

The IOUT1 current will have the following expression:

2
A IIN
IOUT1 ¼ 2I
IIN ¼ þ (3.203)
2 2A
The expression of IOUT2 current can be obtained from (3.177) for IIN ¼ 0, so:

IOUT2 ¼ A=2 (3.204)

In conclusion, the differential output current can be expressed as follows:

2
IIN
IOUT1
IOUT2 ¼ (3.205)
2A

The disadvantage of this implementation of the current squarer consists in the

dependence of the output current on technological parameters. In order to avoid this
inconvenient, the VC voltage can be generated using two gate-source voltages of
MOS transistors, biased at a reference current IO . In this particular case, VC voltage
will have the following expression:
rffiffiffiffiffiffiffi!
2IO
VC ¼ 2 VT þ (3.206)
K

resulting the particular expression of A:

A ¼ 4IO (3.207)
230 3 Squaring Circuits

IO IOUT’ + IIN + IOUT’

+ IO
IOUT’ + IIN IO

M5 M1 M4 M6

M2 M3

Fig. 3.39 Squaring circuit (6) based on PR 3.5

So:
2
IIN
IOUT ¼ (3.208)
8IO

The current squarer presented in Fig. 3.39 [30] uses a translinear loop for
implementing the relation between the currents from the circuit. The characteristic
equation of the loop is:

V SG2 þ VGS4 ¼ VGS1 þ VSG3 (3.209)

As M2 and M4 transistors are biased at IO drain current, M1 is working at

IOUT 0 þ IIN current, while M3 – at IOUT 0 current, the previous relation becomes:
pffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 IO ¼ IOUT 0 þ IOUT 0 þ IIN (3.210)

resulting:
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
4IO ¼ 2IOUT 0 þ IIN þ 2 IOUT 0 ðIOUT 0 þ IIN Þ (3.211)

So:

IIN I2
IOUT 0 ¼ IO
þ IN (3.212)
2 16IO

It is possible to implement the following linear relation between currents from

the circuit, resulting:

IIN I2
IOUT ¼ IOUT 0
IO þ ¼ IN (3.213)
2 16IO
3.2 Analysis and Design of Squaring Circuits 231

Fig. 3.40 Squaring circuit

(7) based on PR 3.5 IO ID3

M1 M3

IIN

M2 M4

IO ID4

The circuit presented in Fig. 3.40 [31] represents a class AB amplifier.

The relation between the gate-source voltages from the translinear loop is:

VGS1 þ VSG2 ¼ VGS3 þ VSG4 (3.214)

For a biasing in saturation of all MOS transistors, because M1 and M2 transistors

are working at IO current, M3 transistor – at ID3 current, while M4 – at ID3 þ IIN , it
can be obtained:
pffiffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 IO ¼ ID3 þ ID3 þ IIN (3.215)

Squaring the previous relation, it results:

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
4IO ¼ 2ID3 þ IIN þ 2 ID3 ðID3 þ IIN Þ (3.216)

So:

IIN I2
ID3 ¼ IO
þ IN (3.217)
2 16IO

The principle of operation of the circuit from Fig. 3.40 can be easily extended for
realizing the squaring function (Fig. 3.41) [31].
For this circuit, the expression of ID5 current can be obtained replacing IIN with

IIN in the expression (3.217) of ID3 current:

IIN I2
ID5 ¼ IO þ þ IN (3.218)
2 16IO
232 3 Squaring Circuits

VDD

M7 M8
IO

ID3 ID5
M1 M3 M5

IIN -IIN IOUT

2IO
M2 M4 M6

IO

-VDD

Fig. 3.41 Squaring circuit (8) based on PR 3.5

The output current of the squaring circuit is linearly dependent on the currents
from the circuit:

2
IIN
IOUT ¼ ID3 þ ID5
2IO ¼ (3.219)
8IO

The squaring circuit presented in Fig. 3.42 [32] uses a translinear loop
implemented with M1–M4 transistors.
The characteristic equation of the translinear loop is:

VSG3 þ VSG4 ¼ VSG1 þ VSG2 (3.220)

Considering a biasing in saturation of all identical MOS transistors from

Fig. 3.42, it results:
pffiffiffiffiffi pffiffiffiffi pffiffiffiffi pffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 IO ¼ IA þ IB ¼ IA þ IIN þ IA (3.221)

Squaring the previous relation, the expression of IA current will be:

IIN I2
IA ¼ I O
þ IN (3.222)
2 16IO
3.2 Analysis and Design of Squaring Circuits 233

VDD

IIN
M5 M6 M13 M14

VBIAS

M3 M1 M4 M2
IO IA IOUT
IB

M7 M8

M9 M10 M11 M12

1:4

Fig. 3.42 Squaring circuit (9) based on PR 3.5

The output current of the circuit presented in Fig. 3.42 can be expressed as follows:

IOUT ¼ ID13 þ ID14
ID12 ¼ ðIA þ IO Þ þ ðIA þ IO þ IIN Þ
4IO (3.223)

resulting:

2
IIN
IOUT ¼ (3.224)
8IO

The squaring circuit presented in Fig. 3.43 [33] uses a translinear loop
implemented with M1–M4 transistors.
The characteristic equation of the translinear loop is:

VGS3 þ VSG4 ¼ VGS1 þ VSG2 (3.225)

For a biasing in saturation of all identical MOS transistors from Fig. 3.43, it
results:
pffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 IO ¼ IOUT þ IIN þ IOUT
IIN (3.226)

The output current of the circuit presented in Fig. 3.43 can be expressed as follows:

2
IIN
IOUT ¼ IO þ (3.227)
4IO
234 3 Squaring Circuits

Fig. 3.43 Squaring circuit VDD

(10) based on PR 3.5
IO
IOUT IIN

M1 M3

2IIN

M2 M4

- VDD

VDD
1:8
M1 M3 M4

IOUT
I
M2 M5

IO IIN

1:1

1:2

Fig. 3.44 Squaring circuit (11) based on PR 3.5

The squaring circuit presented in Fig. 3.44 [34] contains a translinear loop realized
using M1, M2, M3 and M5 transistors, having the following characteristic equation:

VSG1 þ VSG2 ¼ VSG3 þ VSG5 (3.228)

Considering a biasing in saturation of all MOS transistors from Fig. 3.44, it can be
obtained:
pffiffiffiffiffi pffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffi
2 IO ¼ I þ I
IIN (3.229)
3.2 Analysis and Design of Squaring Circuits 235

VDD

M1 M3
IOUT
IIN

M2 M4 2:1

IO

Fig. 3.45 Squaring circuit (12) based on PR 3.5

resulting:

IIN I2
I ¼ IO þ þ IN (3.230)
2 16IO

The output current of the circuit presented in Fig. 3.44 will have the following
expression:
2
IIN
IOUT ¼ ½I þ ðI
IIN Þ
2IO  ¼ (3.231)
8IO

Another squaring circuit based on the same mathematical principle is presented

in Fig. 3.45 [35].
The characteristic equation of the translinear loop including M1–M4 transistors is:

VSG1 þ VSG2 ¼ VSG3 þ VSG4 (3.232)

resulting:
pffiffiffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffi
2 ID1 ¼ ID3 þ ID4 (3.233)

equivalent with:
pffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 IO ¼ IOUT þ IIN þ IOUT
IIN (3.234)

The expression of the output current will be:

2
IIN
IOUT ¼ IO þ (3.235)
4IO
236 3 Squaring Circuits

VDD

K 2K
2IO
ID1
M3 M1 IOUT

IIN
M4 M2

IO ID2

Fig. 3.46 Squaring circuit (13) based on PR 3.5

A current squaring circuit based on the fifth mathematical principle is presented

in Fig. 3.46 [36].
The circuit implements the following relation between the gate-source voltages
of MOS transistors:

VGS1 þ VSG2 ¼ VGS3 þ VSG4 (3.236)

Because all MOS transistors are biased in the saturation region, it is possible to
write that:
pffiffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 IO ¼ ID1 þ ID1 þ IIN (3.237)

Thus:

IIN I2
ID1 ¼ IO
þ IN (3.238)
2 16IO

The expression of the output current can be written as:

IOUT ¼ 2ID1 þ IIN
2IO (3.239)

resulting:

2
IIN
IOUT ¼ (3.240)
8IO

So, the output current is proportional with the square of the input current.
3.2 Analysis and Design of Squaring Circuits 237

Fig. 3.47 Squaring circuit

(1) based on PR 3.6 IIN IO

IOUT - IO

IIN IOUT

3.2.2.2 Squaring Circuits Based on the Sixth Mathematical

Principle (PR 3.6)

A realization of a current squaring circuit based on a translinear loop with MOS

transistors biased in weak inversion is presented in Fig. 3.47 [37].
For this circuit, it can write that:

2VGS ðIIN Þ ¼ VGS ðIOUT Þ þ VGS ðIO Þ (3.241)

where:
!
IIN
VGS ðIIN Þ ¼ VT þ nVth ln W (3.242)
L IDO

!
IOUT
VGS ðIOUT Þ ¼ VT þ nVth ln W (3.243)
L IDO

and:
!
IO
VGS ðIO Þ ¼ VT þ nVth ln W (3.244)
L IDO

resulting:

2 lnðIIN Þ ¼ lnðIOUT Þ þ lnðIO Þ (3.245)

238 3 Squaring Circuits

Fig. 3.48 Squaring circuit

(2) based on PR 3.6 IIN IOUT

M1 M3

IO

M2 M4

IOUT

So, the output current is proportional with the squaring of the input current, IIN :
2
IIN
IOUT ¼ (3.246)
IO

A possible realization of a current squaring circuit (Fig. 3.48) [38, 39, 40, 43]
uses also MOS transistors biased in weak inversion region. M1 and M2 transistors
are working at the IIN input current, M3 – at the IOUT output current, while M4
transistor is biased at a reference current, IO .
Because VGS1 þ VGS2 ¼ VGS3 þ VGS4 and using logarithmical dependencies of
gate-source voltages on drain currents (similar with relations (3.216) – (3.218)), it
results:

2
IIN
IOUT ¼ (3.247)
IO

3.2.2.3 Squaring Circuits Based on the Seventh Mathematical

Principle (PR 3.7)

A circuit that computes the squaring function starting from the arithmetical mean of
input potentials, being based on the seventh mathematical principle is presented in
Fig. 3.49 [21].
Transistors M5–M8 represent the arithmetical mean circuit, resulting:

V1 þ V2
V3 ¼ (3.248)
2
where V1 and V2 potentials are equal with the gate-source voltages of M1 and M4
transistors, respectively:
rffiffiffiffiffiffiffi
2IO
V1 ¼ VGS1 ¼ VT þ (3.249)
K
3.2 Analysis and Design of Squaring Circuits 239

VDD

K 2K K K K
2IO I2 I2
IO
IOUT
IO /4+IIN /2
IIN
IO
I3 I2
M1 M2 M3 M4
K K 4K K

IO IO

V1 V3 V2
M5 M6 M7 M8

IO

Fig. 3.49 Squaring circuit (1) based on PR 3.7

and:
rffiffiffiffiffiffi
2I2
V2 ¼ VGS4 ¼ VT þ (3.250)
K

resulting:
rffiffiffiffiffiffiffi rffiffiffiffiffiffi!
1 2IO 2I2
V3 ¼ VT þ þ (3.251)
2 K K

Choosing the values of K parameters shown in Fig. 3.49, I3 current will have the
following expression:

4K pffiffiffiffiffiffiffiffi
I3 ¼ ðV3
VT Þ2 ¼ IO þ I2 þ 2 IO I2 (3.252)
2
240 3 Squaring Circuits

VDD

K 4K K

I2

V
VO V1

IO I I I I1

Fig. 3.50 Squaring circuit (2) based on PR 3.7

But I3 ¼ 2IO þ I2 þ IIN . So:

ðIO þ IIN Þ2 IO IIN IIN

2
I2 ¼ ¼ þ þ (3.253)
4IO 4 2 4IO

The output current of the circuit is linearly dependent on currents I2 , IO and IIN ,
as follows:

IO IIN I2
IOUT ¼ I2

¼ IN (3.254)
4 2 4IO

so it will be proportional with the squaring of the input current.

The circuit presented in Fig. 3.50 [41, 42] implements the squaring function,
being based on the computation of the arithmetical mean of input potentials.
Because V potential represents the arithmetic mean of VO and V1 potentials
(fixed by IO and I1 currents, respectively), the expression of I2 current can be written
as follows:

4K
I2 ¼ ðVDD
V
VT Þ2 (3.255)
2

resulting:
 2
VO þ V1
I2 ¼ 2K VDD

VT (3.256)
2

So:
pffiffiffiffiffiffiffiffi
I2 ¼ IO þ I1 þ 2 IO I1 (3.257)
3.2 Analysis and Design of Squaring Circuits 241

VDD

I1
IOUT
I
IO /4+ IIN /2
4K
VO V1 I2
IO IO V I1 I1 2IO
I I
IIN

Fig. 3.51 Squaring circuit (3) based on PR 3.7

Using this square-root function, the desired squaring function can be easily
obtained by subtracting IIN and 2IO currents from I2 current expression. The full
implementation in CMOS technology of the squaring function is presented in
Fig. 3.51 [41, 42].
Using NMOS current mirrors, I2 current is forced to be equal with:

I2 ¼ I1 þ IIN þ 2IO (3.258)

From the two previous relations it results:

ðIO þ IIN Þ2 IO IIN IIN

2
I1 ¼ ¼ þ þ (3.259)
4IO 4 2 4IO

Because the output current has the following linear dependence on the circuit
currents (implemented using simple current mirrors):

IO IIN
IOUT ¼ I1

(3.260)
4 2
it results an output current proportional with the square of the input current:
2
IIN
IOUT ¼ (3.261)
4IOUT

The utilization of a FGMOS transistor usually simplifies the schematic of a

current squaring circuit using MOS transistors biased in saturation region
(Fig. 3.52) [43].
The expression of the drain current of the FGMOS transistor can be written as:
 2
4K 1 1
ID ¼ VGS1 þ VGS2
VT (3.262)
2 2 2
242 3 Squaring Circuits

VDD

K K 2K K K

IO IIN

IOUT
IO IO1 ID
4K IIN

K/2 K/4 M1 M2 K
K K

Fig. 3.52 Squaring circuit (4) based on PR 3.7

where VGS1 and VGS2 represent the gate-source voltages of M1 and M2 transistors,
having the following expressions:
rffiffiffiffiffiffiffi
2IO
VGS1 ¼ VT þ (3.263)
K
rffiffiffiffiffiffiffiffiffi
2IO1
VGS2 ¼ VT þ (3.264)
K

From the previous three relations, it results the dependence of the FGMOS
transistor drain current on IO and IO1 currents:
pffiffiffiffiffiffiffiffiffiffiffi
ID ¼ IO þ IO1 þ 2 IO IO1 (3.265)

Because of the PMOS multiple current mirrors, it can write that:

ID ¼ 2IO þ IO1 þ IIN (3.266)

So:

ðIO þ IIN Þ2 IO IIN IIN

2
IO1 ¼ ¼ þ þ (3.267)
4IO 4 2 4IO

Thus, the output current expression will have the following expression:

IO IIN I2
IOUT ¼ IO1

¼ IN (3.268)
4 2 4IO
3.2 Analysis and Design of Squaring Circuits 243

Fig. 3.53 Squaring circuit VDD

based on PR 3.8

M5 M6

V IOUT
IIN

M1 M2 M3 M4

3.2.2.4 Squaring Circuits Based on the Eighth Mathematical

Principle (PR 3.8)

A realization of a current squarer using the eight mathematical principle, whose

performances are dependent on technological parameters is presented in Fig. 3.53 [44].
The input current can be expressed as a function of the drain currents of M1 and
M5 transistors:

K
IIN ¼ ID5
ID1 ¼ ðVDD
V
VT Þ2
2
K K

ðV
VT Þ2 ¼ ðVDD
2VT ÞðVDD
2V Þ (3.269)
2 2

From the previous relation, V potential can be expressed as follows:

1 2IIN
V¼ VDD
(3.270)
2 K ðVDD
2VT Þ

resulting:

2
K K VDD
2VT IIN
ID1 ¼ ðV
VT Þ2 ¼
(3.271)
2 2 2 K ðVDD
2VT Þ

and:

2
K K VDD
2VT IIN
ID5 ¼ ðVDD
V
VT Þ2 ¼ þ (3.272)
2 2 2 K ðVDD
2VT Þ

The output current of the squarer is equal with:

2
K IIN
IOUT ¼ ID2 þ ID3 ¼ ID1 þ ID5 ¼ ðVDD
2VT Þ2 þ (3.273)
4 K ðVDD
2VT Þ2
244 3 Squaring Circuits

VDD

M3 IO
M1
4K

M2 M4
4K
IOUT

IIN

Fig. 3.54 Squaring circuit based on PR 3.9

Using the notation A ¼ VDD
2VT , it results the following expression of the
output current:

KA2 I2
IOUT ¼ þ IN2 (3.274)
4 KA

The operation of the circuit is affected by the technological errors introduced by

the variations of VT .

3.2.2.5 Squaring Circuits Based on the Ninth Mathematical

Principle (PR 3.9)

Another current squaring circuit based on a square-rooting circuit is presented in

Fig. 3.54 [45].
The characteristic equation of the translinear loop including M1–M4 transistors is:

VSG1 þ VSG2 ¼ VSG3 þ VSG4 (3.275)

resulting:

pffiffiffiffiffiffi pffiffiffiffiffiffi 1 pffiffiffiffiffiffi pffiffiffiffiffiffi

ID1 þ ID2 ¼ ID3 þ ID4 (3.276)
2
3.2 Analysis and Design of Squaring Circuits 245

VDD

2K

IO IIN IOUT IO
I2 I1 I1’ I2’

V1
V2

Fig. 3.55 Squaring circuit based on PR 3.Db

equivalent with:
pffiffiffiffiffiffiffiffiffi pffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
IOUT þ IO ¼ IOUT þ IO þ IIN (3.277)
pffiffiffiffiffiffiffiffiffiffiffiffiffi
IIN ¼ 2 IO IOUT (3.278)

The expression of the output current will be:

2
IIN
IOUT ¼ (3.279)
4IO

3.2.2.6 Squaring Circuits Based on Different Mathematical

Principles (PR 3. Db)

The current squaring circuit presented in Fig. 3.55 [46] contains similar blocks, the
left part of the circuit being characterized by the following relation:
pffiffiffiffiffiffiffiffiffiffi
IIN ¼ I1
I2 ¼ 8KIO ðV1
V2 Þ (3.280)

while the right part of the structure having a squaring dependence of the output
current on the differential input voltage:

IOUT ¼ I1 0 þ I2 0
2IO ¼ K ðV1
V2 Þ2 (3.281)

So:

2
IIN
IOUT ¼ (3.282)
8IO
246 3 Squaring Circuits

3.3 Conclusions

Chapter is dedicated to the analysis of CMOS squaring circuits, a very important

class of analog signal processing structures with many applications in VLSI
designs. Both current-input and voltage-input variable computational structures
were described starting from the mathematical principles they are based on and
continuing with their complete implementation in CMOS technology. The biasing
in saturation region of most MOS active devices represents the functional basis for
improving the frequency response of the presented squaring circuits.

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rant multiplier based on CMOS invertes and using low voltage high speed control circuits. In:
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333–336, Poland
52. Raikos G, Vlassis S (2009) Low-voltage CMOS voltage squarer. In: IEEE international on
electronics, circuits, and systems, pp 159–162, Medina, Tunisia
53. Muralidharan R, Chip-Hong C (2009) Fixed and variable multi-modulus squarer architectures
for triple moduli base of RNS. In: IEEE international conference on circuits and systems,
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Chapter 4
Square-Root Circuits

4.1 Mathematical Analysis for Synthesis of Square-Root

Circuits

An important class of VLSI computational structures is represented by the square-

root circuits. Usually implemented using a translinear loop, they exploit the squar-
ing characteristic of MOS transistors biased in saturation region. The square-root
circuits find a lot of applications in analog signal processing, such as square-root
domain filters, Euclidean distance circuits, vector summation structures or real time
image processing circuits. The presented design techniques are based on five
different elementary mathematical principles, each of them being illustrated by
concrete implementations in CMOS technology of their functional relations.

4.1.1 First Mathematical Principle (PR 4.1)

The first mathematical principle used for implementing square-rooting circuits

[1–17] is based on the following relation:

pffiffiffiffi pffiffiffiffi2 pffiffiffiffiffiffiffiffi

IOUT ¼ I1 þ I2  I1  I2 ¼ 2 I1 I2 (4.1)

4.1.2 Second Mathematical Principle (PR 4.2)

The mathematical relation that models this principle is

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffi pffiffiffiffi 2 pffiffiffiffiffiffiffiffi

I1 þ I2 þ aIOUT ¼ I1 þ I2 ) IOUT ¼ I1 I2 (4.2)
a

C.R. Popa, Synthesis of Computational Structures for Analog Signal Processing, 249
DOI 10.1007/978-1-4614-0403-3_4, # Springer Science+Business Media, LLC 2011
250 4 Square-Root Circuits

4.1.3 Third Mathematical Principle (PR 4.3)

The third mathematical principle is used for obtaining a differential output current
proportional with the difference between the square-root of the input currents:
pffiffiffiffi pffiffiffiffi
IOUT1  IOUT2 ¼ a I1  I 2 (4.3)

4.1.4 Fourth Mathematical Principle (PR 4.4)

The fourth mathematical principle used for implementing square-rooting circuits is

based on the following relation:
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
pffiffiffiffi IOUT IOUT pffiffiffiffiffiffiffiffiffiffi
2 I1 ¼ I1 þ aI2  þ I1 þ aI2 þ ) IOUT ¼ 4 aI1 I2 (4.4)
2 2

4.1.5 Different Mathematical Principle (PR 4.D)

A class of square-rooting circuits is based on different mathematical principles.

4.2 Analysis and Design of Square-Root Circuits

4.2.1 Square-Root Circuits Based on the First Mathematical

Principle (PR 4.1)

The circuit presented in Fig. 4.1 [1] implements the square-rooting function using
the arithmetical mean of input potentials.
The I current can be expressed as follows:

4K
I¼ ðV  VT Þ2 (4.5)
2

As M1–M4 transistors compute the arithmetical mean of V1 and V2 potentials, it

results:
 2
V1 þ V2
I ¼ 2K  VT (4.6)
2

These potentials are imposed by the input currents I1 and I2 :

rffiffiffiffiffiffi
2I1
V1 ¼ VGS5 ¼ VT þ (4.7)
K
4.2 Analysis and Design of Square-Root Circuits 251

VDD

I1 I I2
I1 IOUT
M7 I2
M5 M6 V 4K M8 M9

IO IO

V1 V2
M1 M2 M3 M4

IO

- VDD

Fig. 4.1 Square-root circuit (1) based on PR 4.1

and
rffiffiffiffiffiffi
2I2
V2 ¼ VGS8 ¼ VT þ (4.8)
K
Replacing (4.7) and (4.8) in (4.6), the expression of I current will be
pffiffiffiffiffiffiffiffi
I ¼ I1 þ I2 þ 2 I1 I2 (4.9)
The output current of the circuit will be proportional with the square-root of the
product between their input currents:
pffiffiffiffiffiffiffiffi
IOUT ¼ I  I1  I2 ¼ 2 I1 I2 (4.10)
Another possible implementation of the square-root circuit is based on a similar
structure. The square-root circuit using MOS transistors working in saturation and a
FGMOS transistor for reducing the circuit complexity is presented in Fig. 4.2 [2, 3].
The expression of FGMOST drain current from Fig. 4.2 is
 2
4K VGS ðI1 Þ þ VGS ðI2 Þ
ID ¼  VT (4.11)
2 2
252 4 Square-Root Circuits

VDD

IOUT
I2 ID
4K
I1

Fig. 4.2 Square-root circuit (2) based on PR 4.1

resulting:
pffiffiffiffiffiffiffiffi
ID ¼ I1 þ I2 þ 2 I1 I2 (4.12)

So, the expression of the output current will be

pffiffiffiffiffiffiffiffi
IOUT ¼ ID  I1  I2 ¼ 2 I1 I2 (4.13)

4.2.2 Square-Root Circuits Based on the Second Mathematical

Principle (PR 4.2)

The square-root circuit presented in Fig. 4.3 [4] implements the required function
using a translinear loop realized using M1–M4 transistors.
The characteristic equation of the translinear loop is

VSG3 þ VSG4 ¼ VSG1 þ VSG2 (4.14)

Considering a biasing in saturation of all identical MOS transistors from Fig. 4.3,
it results:
pffiffiffiffi pffiffiffiffi pffiffiffiffi pffiffiffiffi
I3 þ I4 ¼ I1 þ I2 (4.15)
4.2 Analysis and Design of Square-Root Circuits 253

Fig. 4.3 Square-root circuit VDD

(1) based on PR 4.2

I 1 – I2

M3 M1 M4 M2

I3 I1 I4 I2

Imposing by external current mirrors the following relation between the currents
from the circuit:

I1 þ I2 þ 2IOUT
I3 ¼ I4 ¼ (4.16)
4

relation (4.15) becomes:

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffi pffiffiffiffi
I1 þ I2 þ 2IOUT ¼ I1 þ I2 (4.17)

So
pffiffiffiffiffiffiffiffi
IOUT ¼ I1 I2 (4.18)

The circuit presented in Fig. 4.4 [5] implements the square-rooting function
using a translinear loop containing M1–M4 transistors.
The characteristic equation of the translinear loop is

VGS1 þ VGS2 ¼ VGS3 þ VGS4 (4.19)

So
pffiffiffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
4I1 þ 4I2 ¼ 2 I1 þ I2 þ IOUT (4.20)

The output current will be proportional with the square-root of the product
between the input currents:
pffiffiffiffiffiffiffiffi
IOUT ¼ 2 I1 I2 (4.21)
254 4 Square-Root Circuits

Fig. 4.4 Square-root circuit VDD

(2) based on PR 4.2

4I1 I1 + I2 + IOUT

M2 M3

M1

4I2
M4

Fig. 4.5 The IOUT ðI1 Þ characteristic for the square-root circuit from Fig. 4.4 for I2 ¼ 1 mA

The operation of the circuit presented in Fig. 4.4 is simulated for I2 ¼ 1 mA and a
variation range of I1 current between 0 and 1 mA. The IOUT ðI1 Þ characteristic is
presented in Fig. 4.5.
A comparison between the simulated and the theoretical estimated results is
shown in Table 4.1.
For extremely low values of input currents, some of the circuit transistors could
operate in weak inversion region. In this case, the circuit doesn’t implement the
required square-root dependence (4.21). However, the circuit has a relatively
extended range of the input currents, between hundreds nanoamperes and few
miliamperes, the error of achieving the square-root function being relatively
small. The frequency of operation of the square-root circuit presented in Fig. 4.4
4.2 Analysis and Design of Square-Root Circuits 255

Table 4.1 Comparison between the simulated

and the theoretical estimated results for the
square-root circuit presented in Fig. 4.4
I1 (mA) IOUT sim (mA) IOUT theor (mA)
0 0 0
0.1 0.629 0.632
0.2 0.886 0.894
0.3 1.082 1.095
0.4 1.246 1.265
0.5 1.390 1.414
0.6 1.519 1.549
0.7 1.637 1.673
0.8 1.746 1.788
0.9 1.848 1.897
1 1.944 2

strongly depends on its biasing currents. For a proper operation of the structure
(all MOS active devices biased in saturation region), it is expected to obtain an
excellent frequency response.
The square-root circuit presented in Fig. 4.6 [6] contains a translinear loop using
M4, M7, M10 and M11 transistors, having the following characteristic equation:

VGS4 þ VGS7 ¼ VGS10 þ VGS11 (4.22)

It results
pffiffi pffiffiffiffi pffiffiffiffi
I ¼ I1 þ I2 (4.23)

So
pffiffiffiffiffiffiffiffi
I ¼ I1 þ I2 þ 2 I1 I2 (4.24)

The output current will have the following expression:

pffiffiffiffiffiffiffiffi
IOUT ¼ I  I1  I2 ¼ 2 I1 I2 (4.25)

Another current square-rooting circuit is presented in Fig. 4.7 [7].

The characteristic equation of the translinear loop including M1–M4 transistors is

VSG1 þ VSG2 ¼ VSG3 þ VSG4 (4.26)

It can be obtained:

pffiffiffiffiffiffi pffiffiffiffiffiffi 1 pffiffiffiffiffiffi pffiffiffiffiffiffi

ID1 þ ID2 ¼ ID3 þ ID4 (4.27)
2
256 4 Square-Root Circuits

VDD

I2
I2 IOUT
M9
M3 M6
I1
I2 M7
K
I1 M10
4K
M4
K I
I1 I2

M1 M2 M5 M8 M11
4K

Fig. 4.6 Square-root circuit (3) based on PR 4.2

VDD

M1 M3 I2
K 4K

M2 M4
K 4K
IOUT

I1

Fig. 4.7 Square-root circuit (4) based on PR 4.2

4.2 Analysis and Design of Square-Root Circuits 257

I1 I1 I2 I2
IOUT1 IOUT2

M1 M2
VC

M3 M4

Fig. 4.8 Square-root circuit (1) based on PR 4.3

equivalent with:
pffiffiffiffi pffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
I1 þ I2 ¼ I1 þ I2 þ IOUT (4.28)

The expression of the output current will be

pffiffiffiffiffiffiffiffi
IOUT ¼ 2 I1 I2 (4.29)

4.2.3 Square-Root Circuits Based on the Third Mathematical

Principle (PR 4.3)

A circuit that implements the current squaring function is presented in Fig. 4.8 [8].
The differential output current of the circuit can be expressed as follows:

IOUT1  IOUT2 ¼ ðI1  ID1 Þ  ðI2  ID2 Þ (4.30)

The VC constant potential is equal with the difference between two gate-source
voltages. Supposing a biasing in saturation of all identical MOS transistors, it
results:
rffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffi
2ID1 2I1
VC ¼ VGS1  VSG3 ¼  (4.31)
K K

So
rffiffiffiffi
pffiffiffiffiffiffi pffiffiffiffi K
ID1 ¼ I1 þ VC (4.32)
2
258 4 Square-Root Circuits

VDD

M1 I1 I2 M2
4K 4K

M3 M4
K K

M5 M6 M7 M8
4K K K 4K

IO I5 I8 IO

IOUT1 IOUT2

Fig. 4.9 Square-root circuit (2) based on PR 4.3

It can be obtained:

K 2 pffiffiffiffiffiffiffiffiffiffi
ID1 ¼ I1 þ V þ 2KI1 VC (4.33)
2 C
and, similarly:

K 2 pffiffiffiffiffiffiffiffiffiffi
ID2 ¼ I2 þ V þ 2KI2 VC (4.34)
2 C
From (4.30), (4.33) and (4.34), it results a square-root dependence of the
differential output current on input currents:
pffiffiffiffiffiffi pffiffiffiffi pffiffiffiffi
IOUT1  IOUT2 ¼ 2K VC I2  I1 (4.35)

Another implementation of a differential squaring circuit is presented in Fig. 4.9 [8].

The M1, M3, M5 and M6 transistors form a translinear loop, the characteristic
equation being:

VSG3 þ VSG6 ¼ VSG1 þ VSG5 (4.36)

equivalent with:
rffiffiffiffiffiffi rffiffiffiffiffiffiffi rffiffiffiffiffiffi
2I5 2IO 2I1
2 ¼ þ (4.37)
4K K K
4.2 Analysis and Design of Square-Root Circuits 259

VDD

I1 I2

M1 M2 M3 M4
VB2
VB1 VB1
M5 M6 M7 M8

I5 I8

IOUT1 IOUT2

Fig. 4.10 Square-root circuit (3) based on PR 4.3

resulting:
pffiffiffiffiffiffiffiffi
I5 ¼ IO þ I1 þ 2 IO I1 (4.38)

and, similarly:
pffiffiffiffiffiffiffiffi
I8 ¼ IO þ I2 þ 2 IO I2 (4.39)

The differential output current of the circuit can be expressed as follows:

pffiffiffiffiffipffiffiffiffi pffiffiffiffi
IOUT1  IOUT2 ¼ ðI5 þ I2 Þ  ðI8 þ I1 Þ ¼ 2 IO I1  I2 (4.40)

An alternate realization of a differential squaring circuit is shown in Fig. 4.10 [8].

The VB2  VB1 differential voltage can be expressed as function on the gate-
source voltages, as follows:

VB2  VB1 ¼ 2VGS ðI5 Þ  2VGS ðI1 Þ (4.41)

resulting:
rffiffiffiffi
2 pffiffiffiffi pffiffiffiffi
VB2  VB1 ¼2 I5  I1 (4.42)
K

So
rffiffiffiffi
pffiffiffiffi pffiffiffiffi K
I5 ¼ I1 þ ðVB2  VB1 Þ (4.43)
8
260 4 Square-Root Circuits

equivalent with:
rffiffiffiffiffiffiffi
KI1 K
I5 ¼ I 1 þ ðVB2  VB1 Þ þ ðVB2  VB1 Þ2 (4.44)
2 8

and, similarly:
rffiffiffiffiffiffiffi
KI2 K
I8 ¼ I2 þ ðVB2  VB1 Þ þ ðVB2  VB1 Þ2 (4.45)
2 8

The differential output current of the circuit will have the following expression:
rffiffiffiffi
K pffiffiffiffi pffiffiffiffi
IOUT1  IOUT2 ¼ ðI5 þ I2 Þ  ðI8 þ I1 Þ ¼ ðVB2  VB1 Þ I1  I2 (4.46)
2

4.2.4 Square-Root Circuits Based on the Fourth Mathematical

Principle (PR 4.4)

A square-root circuit using a translinear loop containing four MOS transistors

biased in saturation region is presented in Fig. 4.11 [9, 10]. The circuit operation
is derived from the fourth mathematical principle with a ¼ 1. The characteristic
equation of the loop is

2VGS ðI1 Þ ¼ VGS ðID Þ þ VGS ðID þ IOUT Þ (4.47)

resulting:
pffiffiffiffi pffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 I1 ¼ ID þ ID þ IOUT (4.48)

After some computations, it results:

2
IOUT IOUT
ID ¼ I1  þ (4.49)
2 16I1

Because

IOUT
ID þ ¼ I1 þ I2 (4.50)
2
4.2 Analysis and Design of Square-Root Circuits 261

VDD

K K/2
ID ID

IOUT IOUT /2

I1
I2

I1

Fig. 4.11 Square-root circuit (1) based on PR 4.4

it can be obtained:
pffiffiffiffiffiffiffiffi
IOUT ¼ 4 I1 I2 (4.51)

Another application of the fourth mathematical principle (a ¼ 1=2) is presented

in Fig. 4.12 [11].
The characteristic equation of the translinear loop from Fig. 4.12 is

2VGS ðI1 Þ ¼ VGS ðID Þ þ VGS ðID þ IOUT Þ (4.52)

resulting:
pffiffiffiffi pffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 I1 ¼ ID þ ID þ IOUT (4.53)

So

2
IOUT IOUT
ID ¼ I1  þ (4.54)
2 16I1

Because

ID þ ðID þ IOUT Þ ¼ 2I1 þ I2 (4.55)

262 4 Square-Root Circuits

Fig. 4.12 Square-root circuit VDD

(2) based on PR 4.4

I1
I2
ID

IOUT

2K

It results, after some computations, that the output current of the circuit from
Fig. 4.12 can be expressed as follows:
pffiffiffiffiffiffiffiffiffiffi
IOUT ¼ 2 2I1 I2 (4.56)

4.2.5 Square-Root Circuits Based on Different Mathematical

Principles (PR 4.D)

A method for obtaining the square-rooting function using the squaring circuit
shown in Fig. 3.3 from Chap. 3 is presented in Fig. 4.13 [12]. The V1 and V2
potentials are obtained using four gate-drain connected MOS transistors, biased at
I1 and I2 input currents.
The sum of the output currents of the squaring circuit is

IOUT1 þ IOUT2 ¼ 2IO þ K ðV1  V2 Þ2 (4.57)

The V1  V2 differential input voltage can be expressed as a function of the gate-

source voltages, as follows:

V1  V2 ¼ 2VGS ðI1 Þ  2VGS ðI2 Þ (4.58)

4.2 Analysis and Design of Square-Root Circuits 263

CM IOUT
CM

I1 I1 IO 8I1 8I2 IO I2 I2
I OUT1 I OUT2

V1 V2
SQ

IO

Fig. 4.13 Square-root circuit based on PR 4.D – principle circuit

Replacing (4.58) in (4.57) and using the square-root dependence of the drain
current on the gate-source voltage for a MOS transistor biased in saturation, it
results:

rffiffiffiffiffiffi rffiffiffiffiffiffi!2
2I1 2I2
IOUT1 þ IOUT2 ¼ 2IO þ K 2 2 (4.59)
K K

equivalent with:
pffiffiffiffiffiffiffiffi
IOUT1 þ IOUT2 ¼ 2IO þ 8I1 þ 8I2  16 I1 I2 (4.60)

The output current can be expressed using a linear relation between the currents
from the circuit:

IOUT ¼ 8I1 þ 8I2 þ 2IO  ðIOUT1 þ IOUT2 Þ (4.61)

resulting a square-root dependence of the IOUT output current on I1 and I2 input

currents:
pffiffiffiffiffiffiffiffi
IOUT ¼ 16 I1 I2 (4.62)
264 4 Square-Root Circuits

VDD

IO 2IO IO IO
8I1 8I2 IOUT
I1 I1 I2 I2
IOUT1 IOUT2

V1 V2

-VDD

Fig. 4.14 Square-root circuit based on PR 4.D – complete implementation

A possible implementation of the previous presented principle is shown in

Fig. 4.14 [12].

4.3 Conclusions

Chapter presents a large number of square-root circuits designed for analog signal
processing. In order to improve the circuits’ frequency operation, usually MOS
transistors biased in saturation have been used, the current-mode operation of most
presented computational structures being responsible for an additional improve-
ment of the frequency behavior.

References

1. Psychalinos C, Vlassis S (2002) A systematic design procedure for square-root-domain circuits

based on the signal flow graph approach. IEEE Transactions on Circuits and Systems I.
Fundam Theory Appl 49:1702–1712
2. Manolescu AM, Popa C (2009) Low-voltage low-power improved linearity CMOS active
resistor circuits. Springer J Analog Integr Circuits Signal Process 62:373–387
3. Popa C (2008) Optimal superior-order curvature-corrected voltage reference based on the
weight difference of gate-source voltages. Springer J Analog Integr Circuits Signal Process
1:1–6
4. De La Blas CA, Lopez A (2008) A novel two quadrant MOS translinear squarer-divider cell.
In: IEEE International conference on electronics, circuits and systems, St. Julien’s, pp 5–8,
Malta
5. De La Cruz-Blas CA, Lopez-Martin A, Carlosena A (2003) 1.5-V MOS translinear loops with
improved dynamic range and their applications to current-mode signal processing. actions on
and. IEEE Trans Circuits Syst II: Analog Digit Signal Process 50:918–927
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6. Jong-Kug S, Charlot JJ (1999) Design and applications of precise analog computational

circuits. In: Midwest symposium on circuits and systems 275–278, Michigan, USA
7. Kircay A, Keserlioglu MS, Cam U (2009) A new current-mode square-root-domain notch
filter. In: European conference on circuit theory and design, Antalya, pp 229–232, Turkey
8. Ngamkham W, Kiatwarin N et al (2008) A linearized source-couple pair transconductor using
a low-voltage square root circuit. In: International conference on electrical engineering/
electronics, computer, telecommunications and information technology, Krabi, pp 701–704
9. Popa C (2005) A new current-mode CMOS Euclidean distance circuit with improved accuracy
and frequency response. In: IEEE conference on microelectronics, electronics and electronic
technologies, pp 99–102, Opatija, Croatia
10. Popa C (2010) Superior-order curvature-corrected voltage reference using a current generator.
In: Lecture notes in computer science, Springer, pp 12–21
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Chapter 5
Exponential Circuits

5.1 Mathematical Analysis for Synthesis of Exponential

Circuits

Exponential circuits represent important building blocks for VLSI signal processing
structures, telecommunication applications, medical equipments, hearing aid or
disk drives. The exponential function can be obtained in bipolar technology from
the exponential characteristic of the bipolar transistor. The nonzero value of the
base current and the temperature dependence of the bipolar transistor parameters
introduce relatively large errors in the computation of the exponential function.
In CMOS technology, the exponential law is available only for the weak inversion
operation of the MOS transistor. The great disadvantage of the circuits using
MOS transistors in weak inversion is represented by their poor circuit frequency
response, caused by the much smaller drain currents available for charging and
discharging the parasite capacitances of the MOS transistors. Thus, circuits realized
in CMOS technology that require a good frequency response can be designed using
exclusively MOS transistors biased in saturation region. Because it exists a relative
limited number of mathematical principles that are used for implementing the
exponential circuits, the first part of the chapter is dedicated to the analysis of
the mathematical relations representing the functional core of the designed circuits.
In the second part of the chapter, starting from these elementary principles, there
are analyzed and designed concrete exponential circuits, grouped following the
mathematical principles they are based on.
The mathematical analysis that represents the basis for designing exponential
circuits [1–14] is structured in nine mathematical principles.

5.1.1 First Mathematical Principle (PR 5.1)

The classical approximation of the exponential function f ðxÞ ¼ expðxÞ is given by

their limited Taylor series expansion:

C.R. Popa, Synthesis of Computational Structures for Analog Signal Processing, 267
DOI 10.1007/978-1-4614-0403-3_5, # Springer Science+Business Media, LLC 2011
268 5 Exponential Circuits

x2 x3 x4
gðxÞ ¼ 1 þ x þ þ þ þ  (5.1)
2! 3! 4!

For a nth order approximation, all the first n + 1 polynomial terms from the
Taylor series expansions of f ðxÞ and gðxÞ must be equal, the approximation error
being mainly caused by the difference between the (n + 1)th order terms from these
expansions.

5.1.2 Second Mathematical Principle (PR 5.2)

An approximation of the f ðxÞ ¼ expð2axÞ function, a and k being constants, is

given by the following function:
2
1 þ ax þ k ðax2Þ
gðxÞ ¼ 2 (5.2)
1  ax þ k ðax2Þ

The third-order limited Taylor series expansion of f ðxÞ function has the following
expression:

4a3 3
f ðxÞ ffi 1 þ 2ax þ 2a2 x2 þ x þ  (5.3)
3
In order to evaluate the third-order limited Taylor series expansion of gðxÞ
function, its superior-order derivates must be determined. The first-order derivate
of gðxÞ function is

2a  3a3 Kx2
g0 ðxÞ ¼ h 2
i2 (5.4)
1  ax þ k ðax2Þ

while the second-order derivate can be expressed as follows:

10Ka3 x þ 3K 2 a5 x3 þ 4a2
g00 ðxÞ ¼ h i
2 3
(5.5)
1  ax þ k ðax2Þ

The third-order derivate of gðxÞ function is

10Ka3  32Ka4 x þ 34K 2 a5 x2  92 K 3 a7 x4 þ 12a3

g000 ðxÞ ¼ h i
2 4
(5.6)
1  ax þ k ðax2Þ

Using the general Taylor series expansion, the function gðxÞ can be third-order
approximated by the following polynomial function:

gðxÞ ffi 1 þ 2ax þ 2a2 x2 þ 2a3 x3 þ    (5.7)

5.1 Mathematical Analysis for Synthesis of Exponential Circuits 269

Comparing the limited Taylor series expansions of f ðxÞ and gðxÞ functions
expressed by (5.3) and (5.7), the errors of the f ðxÞ ffi gðxÞ approximation are mainly
given by the third-order term from these expansions:
3
gðxÞ 2a3  4a3 3 2a3 x3
ef ðxÞ ðxÞ ffi x ¼ (5.8)
expð2axÞ 3 expð2axÞ

5.1.3 Third Mathematical Principle (PR 5.3)

In order to obtain a second-order approximation of the following exponential

function:
f ðxÞ ¼ expð2mxÞ (5.9)

m being a constant, the gðxÞ function can be used, having the important advantage
of allowing a simple implementation in CMOS technology, using multipliers and
squaring circuits:
 
1þx m
gðxÞ ¼ (5.10)
1x

The third-order limited Taylor series expansion of f ðxÞ function has the follow-
ing expression:

4m3 3
f ðxÞ ffi 1 þ 2mx þ 2m2 x2 þ x þ  (5.11)
3
In order to evaluate the third-order limited Taylor series expansion of gðxÞ
function, its superior-order derivates must be determined. The first-order derivate
of gðxÞ function is

2mð1 þ xÞm1
g0 ðxÞ ¼ (5.12)
ð1  xÞmþ1

while the second-order derivate can be expressed as follows:

4mðm þ xÞ ð1 þ xÞm2
g00 ðxÞ ¼ (5.13)
ð1  xÞmþ2

The third-order derivate of gðxÞ function is

4mð2m2 þ 6mx þ 3x2 þ 1Þ ð1 þ xÞm3

g000 ðxÞ ¼ (5.14)
ð1  xÞmþ3
270 5 Exponential Circuits

Using the general Taylor series expansion, the gðxÞ function can be third-order
approximated by the following polynomial function:
2m  2 
gðxÞ ffi 1 þ 2mx þ 2m2 x2 þ 2m þ 1 x3 þ    (5.15)
3
Comparing the limited Taylor series expansions of f ðxÞ and gðxÞ functions
expressed by (5.11) and (5.15), the errors of the f ðxÞ ffi gðxÞ approximation are
mainly given by the third-order term from these expansions:
3
3 ð2m þ 1Þ  4m3 3
2m 2
gðxÞ 2mx3
ef ðxÞ ðxÞ ffi x ¼ (5.16)
expð2mxÞ 3 expð2mxÞ

5.1.4 Fourth Mathematical Principle (PR 5.4)

The f ðxÞ ¼ expðxÞ exponential function can be second-order approximated using

the following general function:

1 þ ax
gðxÞ ¼ (5.17)
1 þ bx

a and b being constants having values that can be determined from the condition
that gðxÞ function must represent the second-order approximation of f ðxÞ function.
The superior-order derivates of gðxÞ function can be expressed as follows:

ab
g0 ðxÞ ¼ (5.18)
ð1 þ bxÞ2
2bðb  aÞ
g00 ðxÞ ¼ (5.19)
ð1 þ bxÞ3
and

6b2 ða  bÞ
g000 ðxÞ ¼ (5.20)
ð1 þ bxÞ4

The conditions that must be fulfilled for obtaining a second-order approximation

of f ðxÞ using gðxÞ are

gð0Þ ¼ 1 (5.21)

g0 ðxÞjx¼0 ¼ 1 (5.22)

g00 ðxÞjx¼0 ¼ 1 (5.23)

5.1 Mathematical Analysis for Synthesis of Exponential Circuits 271

resulting:
ab¼1 (5.24)

and
2bðb  aÞ ¼ 1 (5.25)

equivalent with:
1
a¼ (5.26)
2
and
1
b¼ (5.27)
2
The value of the third-order derivate of gðxÞ for x ¼ 0 will be
3
g000 ðxÞjx¼0 ¼ (5.28)
2
So, the expressions of gðxÞ function and of their Taylor series expansion will be
1 þ 2x
gðxÞ ¼ (5.29)
1  2x

and

x2 x3
gðxÞ ffi 1 þ x þ þ þ  (5.30)
2 4
Comparing the limited Taylor series expansions of f ðxÞ and gðxÞ functions, the
errors of the f ðxÞ ffi gðxÞ approximation are mainly given by the third-order term
from these expansions:
x3 3
gðxÞ  x6 x3
ef ðxÞ ðxÞ ffi 4
¼ (5.31)
expðxÞ 12 expðxÞ

5.1.5 Fifth Mathematical Principle (PR 5.5)

A third-order approximation of the f ðxÞ ¼ expðxÞ exponential function can be

achieved using the following general function:

1 þ ax
gðxÞ ¼ þ cx (5.32)
1 þ bx
272 5 Exponential Circuits

a, b and c being constants having values that can be determined from the
condition that gðxÞ function must represent the third-order approximation of f ðxÞ
function.
The superior-order derivates of gðxÞ function can be expressed as follows:
ab
g0 ðxÞ ¼ þc (5.33)
ð1 þ bxÞ2
2bðb  aÞ
g00 ðxÞ ¼ (5.34)
ð1 þ bxÞ3
6b2 ða  bÞ
g000 ðxÞ ¼ (5.35)
ð1 þ bxÞ4
and

24b3 ðb  aÞ
g0000 ðxÞ ¼ (5.36)
ð1 þ bxÞ5

The conditions that must be fulfilled for obtaining a third-order approximation of

f ðxÞ using gðxÞ are

gð0Þ ¼ 1 (5.37)

g0 ðxÞjx¼0 ¼ 1 (5.38)

g00 ðxÞjx¼0 ¼ 1 (5.39)

g000 ðxÞjx¼0 ¼ 1 (5.40)

resulting:

abþc¼1 (5.41)

2bðb  aÞ ¼ 1 (5.42)

and

6b2 ða  bÞ ¼ 1 (5.43)
It results:

7
a¼ (5.44)
6

1
b¼ (5.45)
3
5.1 Mathematical Analysis for Synthesis of Exponential Circuits 273

and
1
c¼ (5.46)
2
The value of the fourth-order derivate of gðxÞ for x ¼ 0 will be
4
g0000 ðxÞjx¼0 ¼ (5.47)
3
So, the expressions of gðxÞ function and of their Taylor series expansion will be

1 þ 7x x
gðxÞ ¼ x 
6
(5.48)
13 2

and

x2 x3 x4
gðxÞ ffi 1 þ x þ þ þ þ  (5.49)
2 6 18
Comparing the limited Taylor series expansions of f ðxÞ and gðxÞ functions, the
errors of the f ðxÞ ffi gðxÞ approximation are mainly given by the fourth-order term
from these expansions:
x4 4
gðxÞ  24
x
x4
ef ðxÞ ðxÞ ffi 18
¼ (5.50)
expðxÞ 72 expðxÞ

5.1.6 Sixth Mathematical Principle (PR 5.6)

A third-order approximation of the f ðxÞ ¼ expðxÞ exponential function can be

obtained using the following general function:
9 x x
gðxÞ ¼  þ1 (5.51)
2 3x 2
The superior-order derivates of gðxÞ function can be expressed as follows:

27 1 1
g0 ðxÞ ¼  (5.52)
2 ð3  xÞ2 2

27
g00 ðxÞ ¼ (5.53)
ð3  xÞ3

81
g000 ðxÞ ¼ (5.54)
ð3  xÞ4
274 5 Exponential Circuits

324
g0000 ðxÞ ¼ (5.55)
ð3  xÞ5

So, the expression of the Taylor series expansion of f ðxÞ function will be

x2 x3 x4
gðxÞ ¼ 1 þ x þ þ þ þ  (5.56)
2 6 18
Comparing the limited Taylor series expansions of f ðxÞ and gðxÞ functions, the
errors of the f ðxÞ ffi gðxÞ approximation are mainly given by the fourth-order term
from these expansions:

x4 4
gðxÞ  24
x
x4
ef ðxÞ ðxÞ ffi 18
¼ (5.57)
expðxÞ 72 expðxÞ

5.1.7 Seventh Mathematical Principle (PR 5.7)

A fourth-order approximation of the f ðxÞ ¼ expðxÞ exponential function can be

achieved using the following function:

1 þ ax þ bx2
gðxÞ ¼ (5.58)
1 þ cx þ dx2

the values of a , b, c and d constants being determined from the condition that gðxÞ
function must represent the fourth-order approximation of the f ðxÞ ¼ expðxÞ expo-
nential function. The conditions that must be fulfilled for obtaining a fourth-order
approximation of f ðxÞ using gðxÞ are

gð0Þ ¼ 1 (5.59)

g0 ðxÞjx¼0 ¼ 1 (5.60)

g00 ðxÞjx¼0 ¼ 1 (5.61)

g000 ðxÞjx¼0 ¼ 1 (5.62)

g0000 ðxÞjx¼0 ¼ 1 (5.63)

In order to obtain the explicit Taylor series expansion for gðxÞ, its superior-order
derivates must be computed. The first-order derivate is

a  c þ 2xðb  dÞ þ x2 ðbc  ad Þ
g0 ðxÞ ¼ (5.64)
ð1 þ cx þ dx2 Þ2
5.1 Mathematical Analysis for Synthesis of Exponential Circuits 275

The (5.60) condition imposes the following relation between a and c constants:

ac¼1 (5.65)

Replacing (5.65) in (5.64), it results an equivalent expression for g0 ðxÞ:

1 þ 2xðb  dÞ þ x2 ðbc  cd  d Þ
g0 ðxÞ ¼ (5.66)
ð1 þ cx þ dx2 Þ2

The second-order derivate will have the following expression:

2ðb  d Þ  2c  6dx þ x2 ð6d2  6bd Þ þ x3 ð2d 2  2bcd þ 2cd2 Þ

g00 ðxÞ ¼ (5.67)
ð1 þ cx þ dx2 Þ3

The (5.61) condition imposes the following relation between b, c and d

constants:

2ðb  d Þ  2c ¼ 1 (5.68)

Replacing (5.68) in (5.67), it results an equivalent expression for g00 ðxÞ:

1  6dx  3dx2 ð2c þ 1Þ þ x3 ð2d2  2c2 d  cd Þ

g00 ðxÞ ¼ (5.69)
ð1 þ cx þ dx2 Þ3

The third-order derivate of gðxÞ can be expressed as follows:

6d  3c  12xd þ 36d2 x2 þ x3 ð24cd 2 þ 12d 2 Þ þ x4 ð6d 3 þ 6c2 d 2 þ 3cd 2 Þ

g000 ðxÞ ¼
ð1 þ cx þ dx2 Þ4
(5.70)

The (5.62) condition imposes the following relation between c and d constants:

 6d  3c ¼ 1 (5.71)

resulting:

1  12xd þ ax2 þ bx3 þ gx4

g000 ðxÞ ¼ (5.72)
ð1 þ cx þ dx2 Þ4

The following notations have been used:

a ¼ 36d2 (5.73)

b ¼ 24cd 2 þ 12d2 (5.74)

276 5 Exponential Circuits

and

g ¼ 6d3 þ 6c2 d 2 þ 3cd2 (5.75)

The fourth-order derivate of gðxÞ will have the following expression:

12d þ 2ax þ 3bx2 þ 4gx3

g0000 ðxÞ ¼
ð1 þ cx þ dx2 Þ4
4ðc þ 2dxÞð1  12xd þ ax2 þ bx3 þ gx4 Þ
 (5.76)
ð1 þ cx þ dx2 Þ5

From (5.63) and (5.76) it results:

 12d  4c ¼ 1 (5.77)

Using (5.71) and (5.77), the values for c and d constants will be

1
c¼ (5.78)
2

and

1
d¼ (5.79)
12

From (5.65) it results:

1
a¼ (5.80)
2

and, using (5.68), the value of b is

1
b¼ (5.81)
12

The particular expression of gðxÞ that is able to fourth-order approximate the f ðxÞ
exponential function will be
2
1 þ 2x þ 12
x
gðxÞ ¼ (5.82)
1  2x þ 12
x2
5.1 Mathematical Analysis for Synthesis of Exponential Circuits 277

5.1.8 Eighth Mathematical Principle (PR 5.8)

Another fourth-order approximation of the f ðxÞ ¼ expð2xÞ exponential function is

represented by the following function:
2
1 þ x þ x3
gðxÞ ¼ (5.83)
1  x þ x3
2

The superior-order derivates of gðxÞ function can be expressed as follows:

2
2  2x3
g0 ðxÞ ¼  2 2
(5.84)
1  x þ x3
3
4  4x þ 4x9
g00 ðxÞ ¼  
2 3
(5.85)
1  x þ x3
4
8  16x þ 8x2  4x9
g000 ðxÞ ¼  2 4
(5.86)
1  x þ x3
2 3 5
0000 16  160x
3 þ 3  3 þ 27
160x 64x 16x
g ðxÞ ¼  5
(5.87)
1  x þ x3
2

The value of the fifth-order derivate of gðxÞ for x ¼ 0 is

80
g00000 ðxÞjx¼0 ¼ (5.88)
3
resulting the following fourth-order Taylor series expansion for gðxÞ:

ð2xÞ2 ð2xÞ3 ð2xÞ4 2x5

gðxÞ ¼ 1 þ 2x þ þ þ þ þ  (5.89)
2! 3! 4! 9
while the fourth-order Taylor series expansion of f ðxÞ is

ð2xÞ2 ð2xÞ3 ð2xÞ4 ð2xÞ5

f ðxÞ ¼ 1 þ 2x þ þ þ þ þ  (5.90)
2! 3! 4! 5!
Comparing the limited Taylor series expansions of f ðxÞ and gðxÞ functions, the
errors of the f ðxÞ ffi gðxÞ approximation are mainly given by the fifth-order term
from these expansions:

4x5 5
gðxÞ  2x9 2x5
ef ðxÞ ðxÞ ffi 15
¼ (5.91)
expð2xÞ 45 expð2xÞ
278 5 Exponential Circuits

5.1.9 Ninth Mathematical Principle (PR 5.9)

A fourth-order approximation of the f ðxÞ ¼ expðxÞ exponential function can be

obtained using the following general function:

1 þ ax
gðxÞ ¼ þ cx þ dx2 (5.92)
1 þ bx

a, b, c and d being constants with values that can be determined from the condition
that gðxÞ function must represent the fourth-order approximation of f ðxÞ function.
The superior-order derivates of gðxÞ function can be expressed as follows:

ab
g0 ðxÞ ¼ þ c þ 2dx (5.93)
ð1 þ bxÞ2

2bðb  aÞ
g00 ðxÞ ¼ þ 2d (5.94)
ð1 þ bxÞ3

6b2 ða  bÞ
g000 ðxÞ ¼ (5.95)
ð1 þ bxÞ4

24b3 ðb  aÞ
g0000 ðxÞ ¼ (5.96)
ð1 þ bxÞ5

and

120b4 ða  bÞ
g00000 ðxÞ ¼ (5.97)
ð1 þ bxÞ6

The conditions that must be fulfilled for obtaining a fourth-order approximation

of f ðxÞ using gðxÞ are

gð0Þ ¼ 1 (5.98)

g0 ðxÞjx¼0 ¼ 1 (5.99)

g00 ðxÞjx¼0 ¼ 1 (5.100)

g000 ðxÞjx¼0 ¼ 1 (5.101)

5.1 Mathematical Analysis for Synthesis of Exponential Circuits 279

and

g0000 ðxÞjx¼0 ¼ 1 (5.102)

resulting:

abþc¼1 (5.103)

2bðb  aÞ þ 2d ¼ 1 (5.104)

6b2 ða  bÞ ¼ 1 (5.105)

and

24b3 ðb  aÞ ¼ 1 (5.106)

From (5.105) and (5.106), it results:

29
a¼ (5.107)
12

1
b¼ (5.108)
4

So, using (5.107) and (5.108), the values of c and d must be:

5
c¼ (5.109)
3

and

1
d¼ (5.110)
6

The value of the fifth-order derivate of gðxÞ for x ¼ 0 is

5
g00000 ðxÞjx¼0 ¼ (5.111)
4

Thus, the expressions of gðxÞ function and of their Taylor series expansion will be

1 þ 29x 5x x2
gðxÞ ¼ x 
12
 (5.112)
14 3 6
280 5 Exponential Circuits

and

x2 x3 x4 x5
gðxÞ ffi 1 þ x þ þ þ þ þ  (5.113)
2 6 24 96

Comparing the limited Taylor series expansions of f ðxÞ and gðxÞ functions, the
errors of the f ðxÞ ffi gðxÞ approximation are mainly given by the fifth-order term
from these expansions:

x5 x5
 x5
ef ðxÞ ðxÞ ffi 96 120 ¼
gðxÞ
(5.114)
expðxÞ 480 expðxÞ

5.2 Analysis and Design of Exponential Circuits

5.2.1 Exponential Circuits Based on the First Mathematical

Principle (PR 5.1)

Using the second-order Taylor series expansion for approximating the exponential
function having as variable x ¼ IIN =IOUT , where IIN is the input current and IO is the
reference current, it results:
  "   #
IIN IIN 1 IIN 2
IO exp ffi IO 1þ þ þ  (5.115)
IO IO 2 IO

A possible realization of an exponential circuit, based on this mathematical

principle, is presented in Fig. 5.1 [1].
Considering a biasing in saturation for all MOS transistors from the circuit, the
drain current of the FGMOS transistor will have the following expression:
" rffiffiffiffiffiffi rffiffiffiffiffiffiffi! #2
4K 1 2I1 2IO
I2 ¼ 2VT þ þ  VT (5.116)
2 2 K K

equivalent with:
pffiffiffiffiffiffiffiffi
I2 ¼ I1 þ IO þ 2 I1 IO (5.117)
5.2 Analysis and Design of Exponential Circuits 281

VDD

K 2K K/2

IO K K 2K

IO I1 I2
4K IIN
IOUT

K K

Fig. 5.1 Exponential circuit (1) based on PR 5.1

Because I2 ¼ I1 þ 2IO þ IIN it results that:

ðIO þ IIN Þ2 IO IIN IIN

2
I1 ¼ ¼ þ þ (5.118)
4IO 4 2 4IO

The output current of the circuit presented in Fig. 5.1 is

IO I2
IOUT ¼ 2I1 þ ¼ IO þ IIN þ IN (5.119)
2 2IO

Comparing (5.115) with (5.119), the approximate value of IOUT current will be
 
IIN
IOUT ffi IO exp (5.120)
IO

An exponential circuit based on the approximation of the exponential function

using the second-order limited Taylor series is presented in Fig. 5.2 [2].
Because M1–M4 transistors implement an arithmetical mean circuit, V3 poten-
tial will be equal with the arithmetical mean of V1 and V2 potentials:
rffiffiffiffiffiffiffi rffiffiffiffiffiffi!
V1 þ V2 1 2IO 2I2
V3 ¼ ¼ VT þ þ (5.121)
2 2 K K
282 5 Exponential Circuits

VDD

K 2K K K K K/4
2IO I2 I2 IO / 4
IO
IIN IOUT
IO
I3 I2
K K 4K K

IO IO

V1 V3 V2
M1 M2 M3 M4
K K K K

IO

Fig. 5.2 Exponential circuit (2) based on PR 5.1

The expression of I3 current is

pffiffiffiffiffiffiffiffi
I3 ¼ 2K ðV3  VT Þ2 ¼ IO þ I2 þ 2 IO I2 (5.122)

But I3 ¼ 2IO þ I2 þ IIN . It results:

ðIO þ IIN Þ2
I2 ¼ (5.123)
4IO

and
2
IO IO IIN IIN
IOUT ¼ I2 þ ¼ þ þ
4 2 2 4IO
"  2 #   (5.124)
IO   1 IIN IO IIN
¼ 1 þ IO þ
IIN
ffi exp
2 2 IO 2 IO

The circuit presented in Fig. 5.3 [3] implements the exponential function using
the first mathematical principle (PR 5.1).
5.2 Analysis and Design of Exponential Circuits 283

VDD

IO
M2 M3
M1 M4
IIN
I4 IOUT
I1 I2 M5 I3

IO

Fig. 5.3 Exponential circuit (3) based on PR 5.1

The M1–M5 transistors from Fig. 5.3 represent a multiplier circuit. All transistors
are biased in weak inversion region, the dependence of their drain currents on gate-
source voltages being expressed by the following relation:

VSG þ ðn  1ÞVSB
ID ¼ IDO exp (5.125)
nVth

IDO and n being model parameters, while Vth represents the thermal voltage. For
M1–M4 transistors, this relation can be particularized as follows:
 
VSG1
I1 ¼ IDO exp (5.126)
nVth

VSG2 þ ðn  1ÞVSB2
I2 ¼ IDO exp (5.127)
nVth

VSG3 þ ðn  1ÞVSB3
I3 ¼ IDO exp (5.128)
nVth

and
 
VSG4
I4 ¼ IDO exp (5.129)
nVth

Because VSG1 ¼ VSG2 , from (5.126) and (5.127), it can be written that:

I2 ðn  1ÞVSB2
¼ exp (5.130)
I1 nVth
284 5 Exponential Circuits

Similarly, because VSG3 ¼ VSG4 , from (5.128) and (5.129), it results:

I3 ðn  1ÞVSB3
¼ exp (5.131)
I4 nVth

The circuit connections impose VSB3 ¼ VSB2 so, using (5.130) and (5.131), the
relation between I1 -I4 currents will be

I1 I3 ¼ I2 I4 (5.132)

So, I3 current can be expressed as follows:

I2 I4
I3 ¼ (5.133)
I1

Because I1 ¼ IO and I2 ¼ I4 ¼ IIN þ IO , it results:

ðIO þ IIN Þ2 I2
I3 ¼ ¼ IO þ 2IIN þ IN (5.134)
IO IO

The output current of the circuit presented in Fig. 5.3 will have the following
expression:
"    #
IIN 1 IIN 2
IOUT ¼ IO þ I3 ¼ 2IO 1þ þ (5.135)
IO 2 IO

Using the notation x ¼ IIN =IO and (5.1) relation that models the first mathemati-
cal principle, it results that IOUT current represents the second-order approximation
of the exponential function:
 
IIN
IOUT ffi IO exp (5.136)
IO

For applications requiring a better accuracy that can be obtained using the
second-order approximation of the exponential function, a method is to use the
third-order approximation of the exponential function, expressed as

x2 x3
expðxÞ ffi 1 þ x þ þ (5.137)
2 6

for x ¼ IIN =IO . It results:

  "     #
IIN IIN 1 IIN 2 1 IIN 3
IO exp ffi IO 1 þ þ þ þ  (5.138)
IO IO 2 IO 6 IO
5.2 Analysis and Design of Exponential Circuits 285

VDD

K 4K K

I2

M1 M2 V M3 M4
VO V1

IO I I I I1

Fig. 5.4 Exponential circuit (4) based on PR 5.1 – circuit core

The core of the exponential circuit with third-order approximation is represented

by a current squaring circuit (having a possible implementation presented in Fig. 5.4).
Because M1–M4 transistors implement an arithmetical mean circuit, the V poten-
tial will represent the algebraic mean of VO and V potentials (fixed by IO and I1
currents, respectively). So, I2 current expression can be written as

4K
I2 ¼ ðVDD  V  VT Þ2 (5.139)
2

or
 2
VO þ V1
I2 ¼ 2K VDD   VT (5.140)
2

resulting:
pffiffiffiffiffiffiffiffi
I2 ¼ IO þ I1 þ 2 IO I1 (5.141)

Using this square-root function, the required squaring function can be obtained
subtracting IIN and 2IO currents from I2 current expression. The full implementation
in CMOS technology of the squaring circuit is presented in Fig. 5.5 [4].
Using NMOS current mirrors, I2 current is forced to be equal with:

I2 ¼ I1 þ IIN þ 2IO (5.142)

From the two previous relations it results:

ðIO þ IIN Þ2 IO IIN IIN

2
I1 ¼ ¼ þ þ (5.143)
4IO 4 2 4IO
286 5 Exponential Circuits

VDD

I1
I
4K 3
VO V1 I2 IIN
IO V 2
IO I1 I1 2IO
I I
1

Fig. 5.5 Exponential circuit (4) based on PR 5.1 – complete implementation

In order to obtain the third-order approximation (5.138) of the exponential

function, equivalent with the computation of the IIN 3
=IO2 term, two identical circuits
from Fig. 5.5 must be used. For the second circuit, IO current has to be replaced by
IIN current and IIN current – by IIN2
=IO , respectively. Because IIN current is smaller
than IO current, it is important to use a reasonable value of the IIN =IO ratio, in such a
2
way that IIN =IO current to determine a biasing in saturation of all MOS transistors
from Fig. 5.5. For extremely low values of IIN current, some transistors could
operate in weak inversion region, this fact fundamentally changing the function
implemented by the circuit. In conclusion, the minimal value of IIN current is
imposed by the condition of operating at the limit of saturation region of all MOS
2
transistors from Fig. 5.5. The IIN =IO term can be easily obtained by subtracting IO =4
and IIN =2 from I1 current expression:

2
IIN
¼ 4I1  IO  2IIN (5.144)
IO

The block diagram of the exponential circuit with third-order approximation is

presented in Fig. 5.6 [4].
The I1 0 current can be expressed as follows:

2
IIN IIN I3
I1 0 ¼ þ þ IN2 (5.145)
4 2IO 4IO

The output current of the circuit presented in Fig. 5.6 will be

2 2 5 IIN
IOUT ¼ I1 þ I1 0 þ IO þ (5.146)
3 3 6 2
5.2 Analysis and Design of Exponential Circuits 287

1 2 3 1 2 3 IOUT

IO IIN I1 IIN (IIN)2/IO I1’ IIN/2

5IO /6
K 2K/3

Fig. 5.6 Exponential circuit (5) based on PR 5.1 – block diagram

VDD

I1
I
2IIN
4K
VO V1 I2 IIN
IO V I1 I1 2IO 4I1
IO I I IO
K 4K

VDD

1 1

I1’ IOUT
I’
IIN/2
42
VO’ V1 ’ I2’ IIN/IO
IO IIN V’ I1 ’ I1 ’ 2IO
I’ I’ 5IO/6
K 2K/3 2K/3

Fig. 5.7 Exponential circuit (5) based on PR 5.1 – complete implementation

The full implementation of the exponential circuit with third-order approximation

is presented in Fig. 5.7 [4], resulting:

2
IIN I3
IOUT ¼ IIN þ IO þ þ IN2 (5.147)
2IO 6IO
288 5 Exponential Circuits

a b
VDD VDD

IO IIN

IIN (IIN)2/IO

IOUT1 IOUT2

Fig. 5.8 Squaring circuits (1) (a) circuit for computing the second-order term (b) circuit for
computing the third-order term

So, IOUT current represents the third-order approximation of the exponential

function:
 
IIN
IOUT ffi IO exp (5.148)
IO

In order to obtain a proper operation of the previous circuit, all its MOS
transistors must be biased in saturation region. The maximal range of the IIN current
(mainly related to the value of the IO reference current) will be imposed by the
essential condition that MOS transistors to be biased in the saturation region. The
advantage of a very good circuit accuracy, that can be obtained as a result of its
third-order approximation of the exponential function is counterbalanced by a
relatively restricted range of the IIN input current.
A possible realization of a circuit that implements the third-order approximation
of the exponential function uses two squaring circuits presented in Fig. 5.8 [4] for
computing the second-order and the third-order terms from the Taylor series
expansion of the exponential function.
For the first squaring circuit presented in Fig. 5.8a [4], the translinear loop has
the following characteristic equation:

2VGS ðIO Þ ¼ VGS ðIOUT1 Þ þ VGS ðIOUT1  IIN Þ (5.149)

Considering a biasing in saturation of all MOS transistors from Fig. 5.8a, it

results:
pffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 IO ¼ IOUT1 þ IOUT1  IIN (5.150)
5.2 Analysis and Design of Exponential Circuits 289

After computations, IOUT1 current will have the following expression:

IIN I2
IOUT1 ¼ IO þ þ IN (5.151)
2 16IO

Similarly, the output current of the current squaring circuit presented in Fig. 5.8b
can be expressed as follows:

2
IIN I3
IOUT2 ¼ IIN þ þ IN2 (5.152)
2IO 16IO

As the ratio of IIN and IOUT currents could have relatively small values, the
designer must pay attention to check if all MOS transistors from Fig. 5.8b are biased
2
in saturation region (the IIN =IO current can decrease under the limit that generates
the transition in weak inversion of some MOS transistors). This small limiting of
the inferior limit of IIN current is compensated by the extremely small approxima-
tion error of the circuit (fourth-order one).
Using the third-order limited Taylor expansion, the approximate expression of
the exponential function will be
  "  2  3 #
IIN IIN 1 IIN 1 IIN
IO exp ffi IO 1þ þ þ (5.153)
IO IO 2 IO 6 IO

Expressing the second-order and the third-order terms from (5.153) and (5.154)
and replacing in (5.155), it results a linear dependence of the exponential function
approximation as a function of the circuit currents:
 
IIN 40 8
IO exp ffi IOUT ¼ IO þ ðIO  IOUT1 Þ þ 5IIN þ IOUT2 (5.154)
IO 3 3

The complete implementation of the exponential circuit with third-order approx-

imation, based on (5.154) relation, is presented in Fig. 5.9 [4].
Another possible implementation [5] of an exponential circuit with third-order
approximation uses the following squaring structure as circuit core:
Because VGS1 þ VSG2 ¼ VGS3 þ VSG5 , it results:
pffiffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffi
2 IO ¼ ID3 þ ID5 (5.155)

where ID5 ¼ ID3 þ IIN . So

IIN I2
ID3 ¼ IO  þ IN (5.156)
2 16IO
290 5 Exponential Circuits

VDD
K K K 43K/3

5K
K K K/2 K

IO IIN
K 16K 8K/3

IO IIN IOUT2

IOUT
IIN IOUT1
2
(IIN) /IO
40K/3

Fig. 5.9 Exponential circuit (6) based on PR 5.1

and

IIN I2
ID5 ¼ IO þ þ IN (5.157)
2 16IO

The quadratic term required for implementing the limited Taylor series expansion
of the exponential function will have the following linear expression:
2
IIN
¼ 8ðID3 þ ID5 Þ  16IO (5.158)
IO

In order to obtain the third-order term from the limited Taylor series expansion
of the exponential function, the same squaring circuit presented in Fig. 5.10 can be
used, having different biasing currents (Fig. 5.11) [5].
In this case, the ID3 0 and ID5 0 currents will have the following expressions:
2
IIN I3
ID3 0 ¼ IIN  þ IN2 (5.159)
2IO 16IO

and
2
IIN I3
ID5 0 ¼ IIN þ þ IN2 (5.160)
2IO 16IO

resulting the following expression of the third-order term:

3
IIN
¼ 8ðID3 0 þ ID5 0 Þ  16IIN (5.161)
IO2
5.2 Analysis and Design of Exponential Circuits 291

Fig. 5.10 Exponential circuit

(7) based on PR 5.1 – circuit IO ID3
core (1)

M1 M3

IIN

M2 M5

IO ID5

Fig. 5.11 Exponential circuit

(7) based on PR 5.1 – circuit IIN ID3’
core (2)

M1

IIN2/IO

M2 T5

IIN ID5’

Considering (5.160) and (5.163), the third-order approximation of the exponen-

tial function will be
 
IIN 4 5
IO exp ffi IOUT ¼ 4ðID3 þ ID5 Þ þ ðID3 0 þ ID5 0 Þ  IIN  7IO (5.162)
IO 3 3

so a linear expression of the circuit currents, which can be implemented using

multiple PMOS and NMOS current mirrors. It results the following implementation
of the third-order approximated exponential circuit (Fig. 5.12) [5].
For applications that require a better accuracy that can be obtained using the
second or third-order approximation of the exponential function presented above,
it is possible to use the n-th order approximation of the exponential function using
the Taylor series, where n is given by the maximal value of the accepted approxi-
mation error. The result will be a tradeoff between the approximation error and
the circuit complexity.
292 5 Exponential Circuits

VDD

8K 4K
K K 4K/3
K 4K/3
IO ID3

ID3’ 4K
K 8K
IIN
8(ID3 + ID5) (4/3) 4(ID3 + ID5)
IIN (ID3’ + ID5’) IOUT
2
IIN /IO

ID5 16IO (5/3)IIN

K 7IO 5K/3
16K ID5’ 7K
1

Fig. 5.12 Exponential circuit (7) based on PR 5.1 – complete implementation

VDD

1 2

IO 1 1 1

IO IOUT I2 IOUT
4K IIN

K K

Fig. 5.13 Squaring circuit (2)

In order to implement the exponential function with nth order approximation,

n identical squaring circuits must be used, having as possible implementation the
structure presented in Fig. 5.13 [1].
The input and output currents for these n circuits and their connection are
presented in Fig. 5.14 [6].
The “S” block implements a linear function for IOUT , using bO , bIN , b1 , b2 , . . .,
bn1 constants:

X
n1
ðkÞ
IOUT ¼ bO IO þ bIN IIN þ bk IOUT (5.163)
k¼1
5.2 Analysis and Design of Exponential Circuits 293

IO IIN IIN IIN2/IO IINn-2/IOn-3 IINn-1/IOn-2

IO IIN IO IIN IO IIN

IOUT IOUT IOUT

(1) (2) (n-1)

IOUT IOUT IOUT

IIN
bIN b1 b2 bn-1

IO Σ
bO IOUT

IOUT

Fig. 5.14 Exponential circuit (8) based on PR 5.1 – block diagram

where bk are constants coefficients which must be determined. Using the notation
x ¼ IIN =IO , the n output currents of these circuits can be expressed as follows:

ð1Þ IO   IO
IOUT ¼ 1 þ 2x þ x2 ¼ a1 ðxÞ (5.164)
4 4
ð2Þ IO   IO
IOUT ¼ x þ 2x2 þ x3 ¼ a2 ðxÞ (5.165)
4 4
ð3Þ IO  2  IO
IOUT ¼ x þ 2x3 þ x4 ¼ a3 ðxÞ (5.166)
4 4

ðn1Þ IO  n2  IO
IOUT ¼ x þ 2xn1 þ xn ¼ an1 ðxÞ (5.167)
4 4

In order to obtain the nth order approximation of the exponential function using
the previous expressions of the output currents, it is necessary to obtain the
expression of x2 , x3 , . . ., xn as linear functions of a1 ðxÞ, a2 ðxÞ, . . ., an1 ðxÞ,
equivalent with the necessity of obtaining a linear dependence of IOUT current as
ð1Þ ð2Þ ðn1Þ
a function of IOUT , IOUT ,. . ., IOUT currents:
After some algebraic computations, it results the following expressions of x2 ,
x3 , . . ., xn :
x2 ¼ a1 ðxÞ  ð2x þ 1Þ (5.168)

x3 ¼ a2 ðxÞ  2a1 ðxÞ þ ð3x þ 2Þ (5.169)

x4 ¼ a3 ðxÞ  2a2 ðxÞ þ 3a1 ðxÞ  ð4x þ 3Þ (5.170)

294 5 Exponential Circuits

x5 ¼ a4 ðxÞ  2a3 ðxÞ þ 3a2 ðxÞ  4a1 ðxÞ þ ð5x þ 4Þ (5.171)

xk ¼ ak1 ðxÞ  2ak2 ðxÞ þ 3ak3 ðxÞ þ 4ak4 ðxÞ

þ    þ ð1Þk1 ½ðx þ 1Þðk  3Þ þ ð3x þ 2Þ (5.172)

X
n1
xn ¼ ð1Þk1 kank ðxÞ þ ð1Þn1 ½ðx þ 1Þðn  3Þ þ ð3x þ 2Þ ðn > 2Þ (5.173)
k¼1

In conclusion, the expression of the nth order approximation of the exponential

ðkÞ
function can be written as a linear function of IO , 1  k  n. Because

ðkÞ IO
IO ¼ ak ðxÞ (5.174)
4

it results:
h i
4 ð1Þ ð2Þ ð1Þ
 ð2x þ 1Þ
4
IOUT  2IOUT þ ð3x þ 2Þ
IO IOUT IO
expðxÞ ¼ 1 þ x þ þ
h 2! i 3!
ð3Þ ð2Þ ð1Þ
4
IO IOUT  2IOUT þ 3IOUT  ð4x þ 3Þ
þ þ  (5.175)
4!
  ð1Þ  
2 3 4 5 4I 1 2 3 4
expðxÞ ¼ 1 þ x 1  þ  þ   þ OUT  þ  þ 
2! 3! 4! 5! IO 2! 3! 4! 5!
ð2Þ   ð3Þ  
4IOUT 1 2 3 4IOUT 1 2
þ  þ   þ  þ  þ  (5.176)
IO 3! 4! 5! IO 4! 5!

Replacing x ¼ IIN =IO and identifying the constants bk as follows:

bO ¼ 0 (5.177)

2 3 8 13
bIN ¼ 1  þ  þ   (5.178)
2! 3! 4! 5!
 
1 2 3 4
b1 ¼ 4  þ  þ  (5.179)
2! 3! 4! 5!
 
1 2 3
b2 ¼ 4  þ   (5.180)
3! 4! 5!
 
1 2
b3 ¼ 4  þ  (5.181)
4! 5!
5.2 Analysis and Design of Exponential Circuits 295

IBIAS 2IO IIN

IIN IC1
ISQ ISQ IO IOUT
IO SQ CM ISQ MULT / DIV
IC2
IBIAS 2IO IIN

Fig. 5.15 Exponential circuit based on PR 5.2 – block diagram

it results:
 
IIN ð1Þ ð2Þ ð3Þ
IO exp ffi IO þ bIN IIN þ b1 IOUT þ b2 IOUT þ b3 IOUT þ    (5.182)
IO

Thus, the nth order approximation of the exponential function using a limited
Taylor series expansion can be obtained if in Fig. 5.14 the bO , bIN , b1  bn1 constant
coefficients are set to have values corresponding to (5.177)–(5.181) relations.

5.2.2 Exponential Circuits Based on the Second Mathematical

Principle (PR 5.2)

The block diagram of the exponential circuit based on the second mathematical
principle is presented in Fig. 5.15.
The composing blocks are: SQ – a current squaring circuit, having the imple-
mentation presented in Fig. 5.16 [5, 10], CM – a current mirror with two outputs and
a transfer factor equal with 1 and MULT/DIV – a multiplier/divider circuit
presented in Fig. 5.17 [9]. The operation of this circuit is detailed analyzed in
Chap. 2 (Fig. 2.71).
The characteristic equation of the translinear loop for the squaring circuit
presented in Fig. 5.16 is

2VGS ðIO Þ ¼ VGS ðIÞ þ VGS ðI þ IIN Þ (5.183)

Considering that all MOS transistors from Fig. 5.16 are biased in saturation, it
results:
pffiffiffiffiffi pffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffi
2 IO ¼ I þ I þ IIN (5.184)

So

IIN I2
I ¼ IO  þ IN (5.185)
2 16IO
296 5 Exponential Circuits

Fig. 5.16 Squaring circuit

(3) IO ISQ

IIN

VDD

IC2 IOUT IC1 IO

IO1 IO2

IREF IREF

Fig. 5.17 MULT/DIV circuit implementation

The output current of the squaring circuit will contain a constant term and a term
proportional with the squaring of the input current:

2
IIN
ISQ ¼ 2I þ IIN ¼ 2IO þ (5.186)
8IO

The output current of the current multiplier circuit presented in Fig. 5.17 is

IC1
IOUT ¼ IO (5.187)
IC2

The connections from Fig. 5.15 impose that:

IC1 ¼ ISQ þ IBIAS  2IO þ IIN (5.188)

and

IC2 ¼ ISQ þ IBIAS  2IO  IIN (5.189)

5.2 Analysis and Design of Exponential Circuits 297

VDD

M6 M7

M2 M3
M1 M4
IIN I1 I2 I3 I4
IOUT1
M5
IIN
IO M13 M12

M8 M9 M10 M11 M14

Fig. 5.18 Exponential circuit based on PR 5.3

Considering (5.186)–(5.189), it results:

2
IIN
IIN
1þ þ
IBIAS 8IO IBIAS
IOUT ¼ IO 2
(5.190)
IIN IIN
1 þ
IBIAS 8IO IBIAS

With the notations a ¼ 1=IBIAS , k ¼ IBIAS =4IO and x ¼ IIN , the output current
expression will be
2
1 þ ax þ k ðax2Þ
IOUT ¼ IO 2 (5.191)
1  ax þ k ðax2Þ

So, using the second mathematical principle expressed by relation (5.2), it

results that IOUT current represents the second-order approximation of the exponen-
tial function:

IOUT ffi IO expð2axÞ (5.192)

5.2.3 Exponential Circuits Based on the Third Mathematical

Principle (PR 5.3)

The circuit presented in Fig. 5.18 [10] implements the exponential function using
the third mathematical principle (PR 5.3).
298 5 Exponential Circuits

VDD

M2 M3 M2a M3a
M1 M4 M1a M4a
IC
IC IOUT2 IIN
IOUT1
IC M5 M5a IO2
IO1

exponential converter

Fig. 5.19 VGA circuit based on PR 5.3

The M1–M5 transistors from Fig. 5.18 represent a multiplier circuit. All
transistors are biased in weak inversion region, the dependence of their drain
currents on gate-source voltages being expressed by the following relation:

VSG þ ðn  1ÞVSB
ID ¼ IDO exp (5.193)
nVth

IDO and n being model parameters, while Vth represents the thermal voltage. The
relation between I1 –I4 currents is

I1 I3 ¼ I2 I4 (5.194)

or, equivalent:

ðIO  IIN ÞIOUT1 ¼ IO ðIO þ IIN Þ (5.195)

resulting:

IIN
1þ
IO
IOUT1 ¼ IO (5.196)
IIN
1
IO

Using as variable x ¼ IIN =IO and the approximation of the exponential function
given by the fourth mathematical principle for m ¼ 1, it results:
 
2IIN
IOUT1 ffi IO exp (5.197)
IO

Based on the same principle, it is possible to design a VGA circuit (Fig. 5.19) [10].
5.2 Analysis and Design of Exponential Circuits 299

The M1a–M5a transistors biased in weak inversion implement another multiplier

circuit, having a similar operation with the circuit realized using M1–M5 transistors,
so

I1a I3a ¼ I2a I4a (5.198)

resulting:

IOUT1 ðIO2  IIN Þ ¼ ðIOUT1  IOUT2 ÞIO2 (5.199)

Thus

IOUT1 IIN
IOUT2 ¼ (5.200)
IO2

The M1–M5 multiplier implements the following approximate relation:

 
2IC
IOUT1 ffi IO1 exp (5.201)
IO1

From (5.200) and (5.201), it results:

 
IO1 2IC
IOUT2 ðIIN Þ ¼ IIN exp ¼ GI IIN (5.202)
IO2 IO1

The value of the current gain can be exponentially controlled using the control
current, IC :
 
IO1 2IC
GI ¼ exp (5.203)
IO2 IO1

5.2.4 Exponential Circuits Based on the Fourth Mathematical

Principle (PR 5.4)

The block diagram of the exponential circuit based on the fourth mathematical
principle is presented in Fig. 5.20. The MULT/DIV circuit has the implementation
presented in Fig. 5.17.
The expression of IOUT current is

IC1
IOUT ¼ IO (5.204)
IC2
300 5 Exponential Circuits

Fig. 5.20 Exponential circuit

based on PR 5.4 – block IIN
diagram 2IO IC1

IO IOUT
MULT / DIV
2IO IC2

IIN

resulting:
 
2IO þ IIN 1 þ 12
IO
IIN

IOUT ¼ IO ¼ IO   (5.205)
2IO  IIN 1 1 IIN
2 IO

Using the notation x ¼ IIN =IO and (5.29) relation that models the fourth mathe-
matical principle, it results that IOUT current represents the second-order approxi-
mation of the exponential function:
 
IIN
IOUT ffi IO exp (5.206)
IO

5.2.5 Exponential Circuits Based on the Fifth Mathematical

Principle (PR 5.5)

The block diagram of the exponential circuit based on the fifth mathematical
principle is presented in Fig. 5.21. The MULT/DIV circuit has the implementation
presented in Fig. 5.17.
The expression of IOUT 0 current is

IC1
IOUT 0 ¼ IO (5.207)
IC2

resulting:
 
6IO þ 7IIN 1 þ 76 IIINO
IOUT 0 ¼ IO ¼ 2IO   (5.208)
3IO  IIN 1  1 IIN 3 IO
5.2 Analysis and Design of Exponential Circuits 301

7IIN
6IO IC1

IO IOUT’ IOUT
MULT / DIV
3IO IC2
IIN

IIN

Fig. 5.21 Exponential circuit based on PR 5.5 – block diagram

The output current of the circuit having the block diagram presented in Fig. 5.21
will have the following expression:
2   3
1 þ 76 IIINO  
1 IIN 5
IOUT ¼ IOUT 0  IIN ¼ 2IO 4   (5.209)
1 1 IIN 2 IO
3 IO

Using the notation x ¼ IIN =IO and (5.48) relation that models the fifth mathe-
matical principle, it results that IOUT current represents the third-order approxima-
tion of the exponential function:
 
IIN
IOUT ffi IO exp (5.210)
IO

5.2.6 Exponential Circuits Based on the Sixth Mathematical

Principle (PR 5.6)

The block diagram of the exponential circuit based on the sixth mathematical
principle is presented in Fig. 5.22. The MULT/DIV circuit has the implementation
presented in Fig. 5.17.
The expression of IOUT 0 current is

IC1
IOUT 0 ¼ IO (5.211)
IC2

So
 
9 IIN
9IIN =2 2 IO
IOUT 0 ¼ IO ¼ IO   (5.212)
3IO  IIN 3  IIN IO
302 5 Exponential Circuits

IC1 = 9IIN/2 IO
IO IOUT’ IOUT
MULT / DIV
3IO IC2
IIN/2

IIN

Fig. 5.22 Exponential circuit based on PR 5.6 – block diagram

The output current of the circuit having the block diagram presented in Fig. 5.22
will have the following expression:
2   3
IIN
9  
I 1 I
¼ IO 4 þ 15
I 2
¼ IOUT 0 þ IO   
IN O IN
IOUT (5.213)
2 3  IIN 2 IO
IO

Using the notation x ¼ IIN =IO and (5.51) relation that models the sixth mathe-
matical principle, it results that IOUT current represents the third-order approxima-
tion of the exponential function:
 
IIN
IOUT ffi IO exp (5.214)
IO

5.2.7 Exponential Circuits Based on the Seventh Mathematical

Principle (PR 5.7)

The block diagram of the exponential circuit based on the seventh mathematical
principle is presented in Fig. 5.23. The SQ and MULT/DIV circuits have the
implementations presented in Figs. 5.16 and 5.17.
The output current of the circuit presented in Fig. 5.23 has the following relation:

IC1
IOUT ¼ IO (5.215)
IC2

Because

4 2
IC1 ¼ ISQ þ IIN  IO (5.216)
3 3
5.2 Analysis and Design of Exponential Circuits 303

IIN (2/3)IO
IIN IC1
ISQ (4/3)ISQ IO IOUT
IO
SQ CM (4/3)ISQ
MULT / DIV
IC2
IIN (2/3)IO

Fig. 5.23 Exponential circuit based on PR 5.7 – block diagram

and

4 2
IC2 ¼ ISQ  IIN  IO (5.217)
3 3

It results, using the (5.186) expression of ISQ :

I2
2IO þ IIN þ 6IINO
IOUT ¼ IO I2
(5.218)
2IO  IIN þ 6IINO

or, equivalent:
   2
1 þ 12 IIN
IO þ 12
1 IIN
IO
IOUT ¼ IO    2 (5.219)
1  12 IIN
IO þ 12
1 IIN
IO

resulting, using (5.82) relation, that IOUT current represents the fourth-order approx-
imation of the exponential function:
 
IIN
IOUT ffi IO exp (5.220)
IO

5.2.8 Exponential Circuits Based on the Eighth Mathematical

Principle (PR 5.8)

The block diagram of the exponential circuit based on the eighth mathematical
principle is presented in Fig. 5.24. The SQ and MULT/DIV circuits have the
implementations presented in Figs. 5.16 and 5.17.
The output current expression is

IC1
IOUT ¼ IO (5.221)
IC2
304 5 Exponential Circuits

IIN (13/3)IO
IIN IC1
ISQ (8/3)ISQ IO IOUT
SQ CM MULT / DIV
IO (8/3)ISQ
IC2
IIN (13/3)IO

Fig. 5.24 Exponential circuit based on PR 5.8 – block diagram

Because

8 13
IC1 ¼ ISQ þ IIN  IO (5.222)
3 3
and

8 13
IC2 ¼ ISQ  IIN  IO (5.223)
3 3
it results:

I2
IO þ IIN þ 3IINO
IOUT ¼ IO I2
(5.224)
IO  IIN þ 3IINO

or, equivalent
   2
1þ IIN
IO þ 13 IIN
IO
IOUT ¼ IO    2 (5.225)
1 IIN
IO þ 13 IIN
IO

resulting, using (5.83) relation, that IOUT current represents the fourth-order approx-
imation of the exponential function:
 
IIN
IOUT ffi IO exp (5.226)
IO

5.2.9 Exponential Circuits Based on the Ninth Mathematical

Principle (PR 5.9)

The block diagram of the exponential circuit based on the ninth mathematical
principle is presented in Fig. 5.25. The MULT/DIV circuit has the implementations
presented in Fig. 5.17.
5.2 Analysis and Design of Exponential Circuits 305

(29/12)IIN
IO IC1
(8/3)IO
IO IOUT’ IOUT
MULT / DIV
IO IC2
(5/3)IIN
(4/3)ISQ
IIN/4

IIN

ISQ
SQ CM
IO

Fig. 5.25 Exponential circuit based on PR 5.9 – block diagram

The expression of IOUT 0 current is

 
IC1 IO þ 29I IN 1 þ 29
12
IIN
IO
IOUT 0 ¼ IO ¼ IO 12
¼ IO   (5.227)
IC2 IO  4
I IN
1  1 INI
4 IO

The output current of the current squaring circuit can be expressed as follows:

2
IIN
ISQ ¼ 2IO þ (5.228)
8IO

So, the expression of the output current of the exponential circuit presented in
Fig. 5.25 will be

4 8 5
IOUT ¼ IOUT 0  ISQ þ IO  IIN (5.229)
3 3 3

equivalent with:
 
1 þ 29 IIN
12 IO 5 I2
IOUT ¼ IO    IIN  IN
1  14 IIINO 3 6IO
2   3
1 þ 29 IIN    2
5 I 1 I
¼ IO 4 5
12 IO
   IN

IN
(5.230)
1  1 IIN 3 IO 6 IO
4 IO
306 5 Exponential Circuits

resulting, using (5.112) relation, that IOUT current represents the fourth-order
approximation of the exponential function:
 
IIN
IOUT ffi IO exp (5.231)
IO

5.3 Conclusions

Chapter presents a multitude of CMOS implementations of exponential circuits for

VLSI designs. Even in CMOS technology is available the exponential characteristic
of MOS transistors biased in weak inversion, the requirements for a good frequency
response impose the almost exclusively utilization of MOS transistors working in
saturation region for designing performance exponential circuits. Superior-order
approximation functions based on limited Taylor series expansions have been used
in order to accurately approximate the exponential function.

References

1. Popa C (2004) FGMOST-based temperature-independent Euclidean distance circuit. In: Inter-

national conference on optimization of electric and electronic equipment, pp 29–32, Brasov,
Romania
2. Manolescu AM, Popa C (2009) Low-voltage low-power improved linearity CMOS active
resistor circuits. Springer J Analog Integr Circuits Signal Process 62:373–387
3. Kao CH, Lin WP, Hsieh CS (2005) Low-voltage low-power current mode exponential circuit.
In: IEE proceedings on circuits, devices and systems pp 633–635
4. Popa C (2003) CMOS current-mode pseudo-exponential circuits with superior-order approxi-
mation. In: IEEE-EURASIP workshop on nonlinear signal and image processing, Trieste, Italy
(only CD)
5. Popa C (2004) CMOS current-mode high-precision exponential circuit with improved fre-
quency response. In: International conference on automation, quality & testing, robotics
pp 279–284, Cluj, Romania
6. Popa C (2005) A new current-mode pseudo-exponential circuit with an n-th order approxima-
tion. In: The international symposium on system theory, automation, robotics, computers,
informatics, electronics and instrumentation pp 404–407, Craiova, Romania
7. Popa C (2010) Improved linearity CMOS active resistor based on complementary computa-
tional circuits. In: IEEE international conference on electronics, circuits, and systems, Athens,
pp 455–458, Greece
8. Landolt O, Vittoz E, Heim P (1992) CMOS selfbiased Euclidean distance computing circuit
with high dynamic range. Electron Lett 28:352–354
9. Lopez-Martin AJ, Carlosena A (1999) Geometric-mean based current-mode CMOS multi-
plier/divider. In: International symposium on circuits and systems, Orlando, pp 342–345
10. Kao CH, Tseng CC, Hsieh CS (2005) Low-voltage exponential function converter. In: IEE
proceedings on circuits, devices and systems pp 485–487
References 307

11. Jia L, Fengyi H, Xinrong H, Xusheng T (2010) A 1GHz, 68dB CMOS variable gain amplifier
with an exponential-function circuit. In: International symposium on signals systems and
eElectronics, Nanjing, pp 1–4
12. Ethier S, Sawan M (2010) Exponential current pulse generation for efficient very high-
impedance multisite stimulation. In: IEEE transactions on biomedical circuits and systems
pp 1–9
13. Hedayati H, Bakkaloglu B (2009) A 3GHz wideband ∑D fractional-N synthesizer with
voltage-mode exponential CP-PFD. In: Radio frequency integrated circuits symposium, Bos-
ton, pp 325–328, USA
14. Moro-Frias D, Sanz-Pascual MT, De La Cruz-Bias CA (2010) Linear-in-dB variable gain
amplifier with PWL exponential gain control. In: IEEE international symposium on circuits
and systems, Paris, pp 2824–2827, France
Chapter 6
Euclidean Distance Circuits

6.1 Mathematical Analysis for Synthesis of Euclidean

Distance Circuits

The Euclidean distance function is very important in instrumentation circuits,

communication, neural networks, display systems or classification algorithms,
useful for vector quantization or nearest neighbor classification. In order to obtain
a good frequency response, the Euclidean distance circuits are implemented using
exclusively MOS transistors working in saturation. Depending on their input
variable, the Euclidean distance circuits can be classified in computational
structures having current-input or voltage-input vectors.

6.1.1 Euclidean Distance of Voltage Input Vectors

The Euclidean distance between two n-dimensional vectors:

Va ¼ ðVa1; Va2 ; :::; Van Þ (6.1)

and

Vb ¼ ðVb1; Vb2 ; :::; Vbn Þ (6.2)

is defined [1–10] as:

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
X n
VOUT ¼ k Va  V b k ¼ ðVak  Vbk Þ2 ; (6.3)
k¼1

being a direct measure of similarity between the Va and Vb vectors.

The structure of an Euclidian distance circuit with n inputs, designed for voltage
input vectors is represented in Fig. 6.1 [1, 2], consisting in n current squarer circuits
and a square-rooting circuit.

C.R. Popa, Synthesis of Computational Structures for Analog Signal Processing, 309
DOI 10.1007/978-1-4614-0403-3_6, # Springer Science+Business Media, LLC 2011
310 6 Euclidean Distance Circuits

Va1 – Vb1 Va2 – Vb2 Van – Vbn

…
SQ 1 SQ 2 SQ n

IOUT 1 IOUT 2 IOUT n

IOUT Σ

SQR

VOUT

Fig. 6.1 Euclidian distance circuit with n inputs for voltage vectors

6.1.2 Euclidean Distance of Current Input Vectors

An equivalent function based on current-mode operation can be written as:

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
X n
IOUT ¼ kIa  Ib k ¼ ðIak  Ibk Þ2 ; (6.4)
k¼1

where:

Ia ¼ ðIa1; Ia2 ; :::; Ian Þ (6.5)

and:

Vb ¼ ðVb1; Vb2 ; :::; Vbn Þ (6.6)

represent the input current-mode n-dimensional vectors.

The structure of an Euclidian distance circuit with n inputs designed for current
vectors is represented in Fig. 6.2 [1, 2], consisting in n current squarer circuits and a
square-root circuit.
6.2 Analysis and Design of Euclidean Distance Circuits 311

Ia1 – Ib1 Ia2 – Ib2 Ian – Ibn

…
SQ 1 SQ 2 SQ n

IOUT 1 IOUT 2 IOUT n

IOUT Σ

SQR

IOUT

Fig. 6.2 Euclidian distance circuit with n inputs for current vectors

6.2 Analysis and Design of Euclidean Distance Circuits

6.2.1 Euclidean Distance Circuits for Voltage Input Vectors

A possible realization of an Euclidean distance circuit is presented in Fig. 6.3.

The expression of IOUT current is:
X
n X
n X
n
IOUT ¼ IOUT1  IOUT2 ¼ IkX  IkY ¼ ðIkX  IkY Þ (6.7)
k¼1 k¼1 k¼1

Considering that the differential output current of each voltage squaring circuit
is equal with KDV 2 =4, DV being its differential input voltage, the expression of
IOUT current for the entire structure presented in Fig. 6.3 will be:

KX n
IOUT ¼ ðVkX  VkY Þ2 ; (6.8)
4 k¼1

IOUT being also the drain current of the FGMOS transistor, it results:
 2
2K VB þ VOUT
IOUT ¼  VT : (6.9)
2 2

So:
rffiffiffiffiffiffiffiffiffiffiffiffi
2IOUT
VOUT ¼ 2VT  VB þ 2 : (6.10)
2K
312 6 Euclidean Distance Circuits

VDD

I1X I1Y InX InY IOUT IOUT1

VOUT
VB
2K
Va1 Vb1 Van
SQ 1 SQ n Vbn
IOUT2
...

- VDD

Fig. 6.3 Euclidean distance circuit – first implementation

Imposing that VB ¼ 2VT [6, 7], the output voltage will be expressed as follows:
rffiffiffiffiffiffiffiffiffi
IOUT
VOUT ¼2 (6.11)
K

Replacing (6.8) in (6.11), it can be obtained:

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
X n
VOUT ¼ ðVkX  VkY Þ2 : (6.12)
k¼1

6.2.2 Euclidean Distance Circuits for Current Input Vectors

A possible realization of an Euclidean distance circuit is presented in Fig. 6.4 [8]

and it contains n current squaring circuits and a current square-rooting circuit in
order to implement the required function.
The first squaring circuit is realized using the translinear loop implemented with
M1–M4 transistors, having the following characteristic equation:

VGS1 þ VSG2 ¼ VGS3 þ VSG4 : (6.13)

The relation between the currents from the circuit are:

IIN1 þ IIN1 0 ¼ IOUT1  IIN1 0 : (6.14)

So:

IOUT1  IIN1
IIN1 0 ¼ : (6.15)
2
6.2 Analysis and Design of Euclidean Distance Circuits 313

VDD
n:1
IO IX
IY
IOUT1 IOUTn

M1 M3 M6 M7

IIN1 IINn IOUT

IIN1’ IINn’

M2 M4 M5 M8

...
IO

Fig. 6.4 Euclidean distance circuit – second implementation

Considering a biasing in saturation of all MOS transistors from Fig. 6.4, it

results:
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
pffiffiffiffiffi IOUT1 þ IIN1 IOUT1  IIN1
2 IO ¼ þ : (6.16)
2 2

The IOUT1 current will be expressed as follows:

2
IIN1
IOUT1 ¼ 2IO þ : (6.17)
8IO

Similarly, analyzing the translinear loop implemented using M1, M2, M5 and
M6 transistors, it results:
2
IINn
IOUTn ¼ 2IO þ : (6.18)
8IO

The expression of IX current is:

X
n
1 X n
IX ¼ IOUT k ¼ 2nIO þ I2 ; (6.19)
k¼1
8IO k¼1 IN k

while IY current has the following expression:

IX 1 X n
IY ¼ ¼ 2IO þ I2 : (6.20)
n 8nIO k¼1 IN k
314 6 Euclidean Distance Circuits

Fig. 6.5 Current squaring

circuit (1)
IO IOUT

IIN

IOUT + IIN

Fig. 6.6 Symbolic

representation of the current
squaring circuit (1) IO IIN

IO IIN

IOUT IOUT’

IOUT IOUT + IIN

In order to implement the square-rooting function, the translinear loop

containing M1, M2, M7 and M8 transistors is used, resulting:
2
IOUT
IY ¼ 2IO þ : (6.21)
8IO
From (6.20) and (6.21), the output current can be expressed as follows:
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
1X n
IOUT ¼ I2 : (6.22)
n k¼1 IN k

Another possible implementation of a current squaring circuit for an Euclidean

distance circuit is based on the utilization of two groups of cascaded MOS transistors,
the devices from the first group being biased at the same drain current, while each
MOS transistor from the second group works at different drain currents (Fig. 6.5) [4].
The symbolic representation of the current squarer is presented in Fig. 6.6 [4].
6.2 Analysis and Design of Euclidean Distance Circuits 315

IO IIN1 IO IIN2 IO IINn

IO IIN IO IIN IO IIN

IOUT IOUT’ IOUT IOUT’ IOUT IOUT’

IOUT 1 IOUT 1’ IOUT 2 IOUT 2’ IOUT n IOUT n’

IOUT a IOUT b

Fig. 6.7 Euclidean distance circuit – third implementation (block diagram)

Considering a biasing in saturation of all MOS transistors from Fig. 6.5, it can be
written that:
pffiffiffiffiffi pffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 IO ¼ IOUT þ IOUT þ IIN : (6.23)

After some algebraic computations, it results the expression of the output

current, IOUT :

IIN I2
IOUT ¼ IO  þ IN (6.24)
2 16IO
and

0 IIN I2
IOUT ¼ IOUT þ IIN ¼ IO þ þ IN : (6.25)
2 16IO
Because the Euclidean distance circuit must have n inputs, it is obviously the
necessity of using n identical circuits from Fig. 6.5, having the same IO reference
current, but different input currents, IIN1 , IIN2 , . . ., IINn . The output currents of
these squaring circuits will be noted with IOUT 1 , IOUT 2 , . . ., IOUT n and IOUT1 0 , . . .,
IOUT n 0 , respectively and they will be summed in order to obtain the output currents,
IOUT a and IOUT b (Fig. 6.7 [4]).
The expression of IOUT a current can be written as:
X
n
IOUT a ¼ IOUT k ; (6.26)
k¼1

equivalent with:

1X n
1 X n
IOUT a ¼ nIO  IIN k þ I2 ; (6.27)
2 k¼1 16IO k¼1 IN k
316 6 Euclidean Distance Circuits

Fig. 6.8 Current square-root VDD

circuit (1)

IO
IIN
ID
K
IOUT

2K K

while IOUT b current expression is:

1X n
1 X n
IOUT b ¼ nIO þ IIN k þ I2 : (6.28)
2 k¼1 16IO k¼1 IN k

The total output current of the squarer circuit is the sum of IOUT a and IOUT b
currents:

1 X n
IOUT S ¼ IOUTa þ IOUTb ¼ 2nIO þ I2 : (6.29)
8IO k¼1 IN k

The implementation of the square-rooting circuit is presented in Fig. 6.8 [4].

Similarly with the current squarer, it can be written that:
pffiffiffiffiffi pffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 IO ¼ ID þ ID þ IOUT : (6.30)

It results:
2
IOUT IOUT
ID ¼ IO  þ (6.31)
2 16IO

and

2ID þ IOUT  2IO ¼ IIN (6.32)

So, the IOUT output current will be proportional with the square-root of the input
current, IIN :
pffiffiffiffiffiffiffiffiffiffiffiffi
IOUT ¼ 8IO IIN : (6.33)
6.2 Analysis and Design of Euclidean Distance Circuits 317

VDD

IOUT b
IOUT IO IOUT a
ID
IOUT Σ
IIN IOUT IOUT 1 IOUT 2 IOUT n IIN
IIN1 IIN2 IINn
2 2n

Fig. 6.9 Euclidean distance circuit – third implementation (complete circuit)

VDD

2K

IO IIN1

IOUT 1
IO IO1 ID
4K
IIN1
K/4
K/2 M1 M2
K K

Fig. 6.10 Current squaring circuit (2)

In order to obtain the Euclidean distance of the input currents, n current squarers
and a square-root circuit are used in Fig. 6.9 [4].
The IIN input current, is imposed to be equal with:

1 X n
IIN ¼ IOUT S  2nIO ¼ I2 : (6.34)
8IO k¼1 IN k

From (6.33) and (6.34), the output current of the entire circuit could be expressed as:
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
X n
IOUT ¼ 2
IIN k: (6.35)
k¼1

The third implementation of the Euclidean distance circuit uses the current
squarer presented in Fig. 6.10 [3].
318 6 Euclidean Distance Circuits

Considering that all MOS transistors from Fig. 6.10 are working in saturation,
the expression of the drain current of the FGMOS transistor can be written as:
 2
4K 1 1
ID ¼ VGS1 þ VGS2  VT ; (6.36)
2 2 2

where VGS1 and VGS2 represent the gate-source voltages of M1 and M2 transistors,
respectively, having the following expressions:
rffiffiffiffiffiffiffi
2IO
VGS1 ¼ VT þ ; (6.37)
K
rffiffiffiffiffiffiffiffiffi
2IO1
VGS2 ¼ VT þ : (6.38)
K

From the previous three relations it results the dependence of the FGMOS
transistor drain current on IO and IO1 currents:
pffiffiffiffiffiffiffiffiffiffiffi
ID ¼ IO þ IO1 þ 2 IO IO1 : (6.39)

Because of the PMOS multiple current mirrors, it can be written that:

ID ¼ 2IO þ IO1 þ IIN1 ; (6.40)

resulting:

ðIO þ IIN1 Þ2 IO IIN1 IIN1

2
IO1 ¼ ¼ þ þ : (6.41)
4IO 4 2 4IO

Thus, the output current expression is:

2
IO IIN1 IIN1
IOUT1 ¼ IO1   ¼ : (6.42)
4 2 4IO

A possible implementation of the square-rooting circuit is based on a structure

that is similar with the circuit used for obtaining the squaring function. The square-
rooting circuit using MOS transistors working in saturation and a FGMOS transis-
tor for reducing the circuit complexity is presented in Fig. 6.11 [9].
The expression of the drain current for the FGMOS transistor from Fig. 6.11 is:
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
ID ¼ IO þ IOUTS þ 4IO IOUTS (6.43)
6.2 Analysis and Design of Euclidean Distance Circuits 319

VDD

IOUT
IO ID

IOUT Σ

Fig. 6.11 Current square-root circuit (2)

where IOUTS represents the sum of output currents obtained from the n squaring
circuits:

X
n
1 X n
IOUTS ¼ IOUTk ¼ I2 : (6.44)
k¼1
4IO k¼1 IN k

Because of the PMOS current mirrors from Fig. 6.11, it exists the following
linear relation between the currents from the circuit:

ID ¼ IO þ IOUTS þ IOUT : (6.45)

So, the expression of the output current for the entire Euclidean distance circuit
will be:
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi X n
IOUT ¼ 4IO IOUTS ¼ 2
IIN k: (6.46)
k¼1

The complete implementation of the Euclidean distance circuit is presented in

Fig. 6.12 [3].
A CMOS implementation of a current squaring circuit using MOS transistors
biased in weak inversion region is presented in Fig. 6.13.
The translinear loop from Fig. 6.13 has the following characteristic equation:

2VGS ðIIN Þ ¼ VGS ðIOUT Þ þ VGS ðIO Þ; (6.47)

320 6 Euclidean Distance Circuits

VDD

IIN1 IINn

IOUT

Fig. 6.12 Euclidean distance circuit – fourth implementation

Fig. 6.13 Current squaring

circuit (3) IIN IOUT

IO

where:
!
IIN
VGS ðIIN Þ ¼ VT þ nVth ln W ; (6.48)
L IDO

!
IOUT
VGS ðIOUT Þ ¼ VT þ nVth ln W (6.49)
L IDO

and:
!
IO
VGS ðIO Þ ¼ VT þ nVth ln W : (6.50)
L IDO
6.2 Analysis and Design of Euclidean Distance Circuits 321

Fig. 6.14 Current square-

root circuit (3) IOUT IIN

IO

VDD

IINn IOUTn IOUT Σ

IIN1 IOUT1 IOUT

IO IO IO
IOUT1 IOUTn

Fig. 6.15 Euclidean distance circuit – fifth implementation

Considering that all MOS active devices are identical, the output current expres-
sion of the CMOS current squarer will have the following expression:

2
IIN
IOUT ¼ (6.51)
IO

A simple realization of the square-rooting circuit (Fig. 6.14) is derived from the
current squarer presented in Fig. 6.7.
Similarly with the current squarer, it results:
pffiffiffiffiffiffiffiffiffiffi
IOUT ¼ IO IIN : (6.52)

In order to obtain the Euclidean distance of the input currents, n current squarers
and a square-rooting circuit must be used, the complete implementation of the
Euclidean distance circuit being presented in Fig. 6.15.
The total output current, IOUT S , will be:

X
n
1 Xn
IOUT S ¼ IOUT k ¼ I2 : (6.53)
k¼1
IO k¼1 IN k
322 6 Euclidean Distance Circuits

From (6.52) and (6.53), because the input current of the square rooting circuit is
equal with the total output current of the current squaring circuits (IIN ¼ IOUT S ), the
output current of the entire circuit can be expressed as:
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
X n
IOUT ¼ 2
IIN k: (6.54)
k¼1

6.3 Conclusions

Chapter analyzes the possibilities of implementing in CMOS technology of the

Euclidean distance, covering a large area of applications in VLSI designs. Circuits
having both current-input and voltage-input vectors have been presented, their
practical device-level designs being closely related to the squaring and square-
rooting circuits presented in the previous chapters.

References

1. Popa C (2009) A new FGMOST Euclidean distance computational circuits based on algebraic
mean of the input potentials. In: Lecture notes in computer science, Springer, pp 459–466
2. Vlassis S, Fikos G, Siskos S (2001) A floating gate CMOS Euclidean distance calculator and
its application to hand-written digit recognition. In: International conference on image
processing, pp 350–353
3. Popa C (2004) FGMOST-based temperature-independent Euclidean distance circuit. In: Inter-
national conference on optimization of electric and electronic equipment, pp 29–32
4. Popa C (2005) Current-mode Euclidean distance circuit independent on technological
parameters. In: International semiconductor conference, pp 459–462
5. Vlassis S, Yiamalis T, Siskos S (1999) Analogue computational circuits based on floating-gate
transistors. In: International conference on electronics, circuits and systems, 5–8 Sept 1999, pp
129–132
6. Popa C (2003) Low-voltage accurate CMOS threshold voltage extractors. In: IEEE-EURASIP
workshop on nonlinear signal and image processing, Trieste, Italy (only CD)
7. Popa C (2004) CMOS current-mode Euclidean distance circuit using floating-gate MOS
transistors. In: International conference on microelectronics, 16–19 May 2004, pp 585–588
8. Netbut C, Kumngern M, Prommee P, Dejhan K (2006) A versatile vector summation circuit.
In: International symposium on communications and information technologies, Bangkok, pp
1093–1096
9. Manolescu AM, Popa C (2009) Low-voltage low-power improved linearity CMOS active
resistor circuits. Springer J Analog Integr Circuits Signal Process 62:373–387
10. Hyo-Jin A, Chang-Seok C, Hanho L (2009) High-speed low-complexity folded degree-
computationless modified Euclidean algorithm architecture for RS decoders. In: International
symposium on integrated circuits, Singapore, 14–16 Dec 2009, pp 582–585
Chapter 7
Active Resistor Circuits

7.1 Mathematical Analysis for Synthesis of Active Resistor

Circuits

The diversity of mathematical principles that represent the basis of designing active
resistor circuits [1–25] is relatively restricted, existing about six fundamental
theoretical methods for implementing this class of circuits. In the process of
designing this circuits, V1 and V2 represent the input potentials, VO and IO are a
constant voltage and a constant current, respectively, while RECH notation is used
for the equivalent resistance between the input terminals.

7.1.1 First Mathematical Principle (PR 7.1)

The active resistor circuits designed based on the first mathematical principle uses a
linear differential amplifier as constitutive core and two input–output connections, in
order to implement a linear current–voltage characteristic between two input pins.

7.1.2 Second Mathematical Principle (PR 7.2)

The linearization techniques based on the second mathematical principle uses a

proper voltage biasing of a classical differential amplifier, that modifies the transfer
characteristic of this circuit, in order to have a linear behavior for the resulting
active resistor structure.

C.R. Popa, Synthesis of Computational Structures for Analog Signal Processing, 323
DOI 10.1007/978-1-4614-0403-3_7, # Springer Science+Business Media, LLC 2011
324 7 Active Resistor Circuits

7.1.3 Third Mathematical Principle (PR 7.3)

The method for designing a linear active resistor, based on the third mathematical
principle, consists in the passing between two pins of a current obtained at the
output of a differential amplifier, considering these pins as differential circuit
inputs.

7.1.4 Fourth Mathematical Principle (PR 7.4)

The linearization technique of the active resistors designed using the fourth mathe-
matical principle is based on the utilization of two blocks implementing comple-
mentary functions (usually, squaring and square-rooting functions).

7.1.5 Fifth Mathematical Principle (PR 7.5)

The active resistors designed using the fifth mathematical principle are based on the
“mirroring” of the Ohm law from two control terminals to the external pins of
active resistor circuit, the equivalent resistance being equal with the ratio of a
reference voltage, VO and a reference current, IO .

7.1.6 Different Mathematical Principles (PR 7.D)

Active resistors using this mathematical principle present different possible

implementations, their common point being the exclusively utilization of MOS
transistors biased in saturation.

7.2 Analysis and Design of Active Resistor Circuits

7.2.1 Active Resistor Circuits Based on the First Mathematical

Principle (PR 7.1)

Active resistor circuits designed based on the first mathematical principle use a
linear differential amplifier as constitutive core in order to implement a linear
current–voltage characteristic between two input pins. Two input–output
connections allow to compute the differential output current, I1
I2 , and to pass
7.2 Analysis and Design of Active Resistor Circuits 325

Fig. 7.1 Active resistor with CM

positive equivalent resistance
based on PR 7.1 – block
diagram CM

I2 I1

I1 I1 I2 I2

V1 Linear V2
I1-I2 DA I1-I2

IO

Fig. 7.2 Active resistor with CM

negative equivalent resistance
based on PR 7.1 – block
diagram CM

I2 I1

I1 I1 I2 I2

V1 Linear V2
I2-I1 DA I2-I1

IO

it through the input pins of the entire structure (Fig. 7.1) [1] using two additional
current mirrors.
The equivalent resistance of the entire structure can be defined as the ratio
between the V1
V2 differential input voltage and the I1
I2 differential current:

V1
V 2 1
RECH ¼ ¼ ; (7.1)
I 1
I2 Gm

Gm being the equivalent transconductance of the linear differential amplifier.

The possibility of controlling the value of the equivalent resistance is given by the
dependence of the Gm equivalent transconductance on the IO biasing current.
The replacing of the input–output connections from Fig. 7.1 by two input–output
cross-connections will change the sign of the equivalent resistance for the structure
presented in Fig. 7.2 [1]. The area of applications of controllable negative resistance
326 7 Active Resistor Circuits

I1 I2

M1 M2
V1 IO IO V2

I1 VO VO I2
- + + -
IO IO
IO IO

Fig. 7.3 Linear DA block – principle circuit

active resistors covers many domains, including the cancellation of amplifiers’ gain
load or the design of improved performances integrators.

V1
V2 1
RECH ¼ ¼
: (7.2)
I2
I1 Gm

The linearity of both positive and negative resistance active resistor circuits is,
mainly, determined by the linearity of the constitutive differential amplifier. A
possible method for linearizing the transfer characteristic of classical differential
amplifier uses the principle based on the constant sum of gate-source voltages
(Fig. 7.3) [2].
For a biasing in saturation of MOS transistors from Fig. 7.3, the V1
V2
differential input voltage can be expressed as follows:

V1
V2 ¼ VGS1
VO (7.3)

and:

V1
V2 ¼ VO
VGS2 ; (7.4)

resulting the expressions of the sum and difference between gate-source voltages:

VGS1 þ VGS2 ¼ 2VO (7.5)

and:

VGS1
VGS2 ¼ 2ðV1
V2 Þ: (7.6)

The I1
I2 differential output current is:

K K
I1
I2 ¼ ðVGS1
VT Þ2
ðVGS2
VT Þ2 ; (7.7)
2 2
7.2 Analysis and Design of Active Resistor Circuits 327

equivalent with:

K
I1
I ¼ ðVGS1
VGS2 ÞðVGS1 þ VGS2
2VT Þ: (7.8)
2

Replacing (7.5) and (7.6) in (7.8), it results a linear transfer characteristic of the
differential amplifier presented in Fig. 7.3:

I1
I2 ¼ 2K ðVO
VT ÞðV1
V2 Þ: (7.9)

Usually, the VO voltage sources are implemented as current-controlled voltage

sources. The simplest way to realize these sources, having the advantages of
simplicity and of minimization the errors introduced by the bulk effect is to use
the gate-source voltage of a MOS transistor in saturation, biased at a constant
current, IO :
rffiffiffiffiffiffiffi
2IO
VO ¼ VGSO ¼ VT þ : (7.10)
K

Replacing these particular expressions of VO voltage sources in the general

expression (7.9) of the output current of the differential amplifier, it results:
pffiffiffiffiffiffiffiffiffiffi
I1
I2 ¼ 8KIO ðV1
V2 Þ; (7.11)

so, an equivalent transconductance of the differential amplifier:

pffiffiffiffiffiffiffiffiffiffi
Gm ¼ 8KIO ; (7.12)

that can be controlled by the biasing current, IO .

An active resistor circuit based on the first mathematical principle (PR 7.1), that
uses the linearization technique of the composing differential amplifier, based on
the constant sum of the gate-source voltages is presented in Fig. 7.4. The VO voltage
sources from Fig. 7.3 are practically implemented in Fig. 7.4, using the gate-source
voltages of M3 and M4 transistors, biased at a constant current, IO . In order to
obtain a differential amplifier with two I1 output currents and two I2 output currents
(as it is shown in Fig. 7.1), a parallel connection of two identical differential
amplifiers is used in Fig. 7.4 (M1–M2 and M5–M6, respectively).
The expression of the VO current-controlled voltage sources will be:
rffiffiffiffiffiffiffi
2IO
VO ¼ VGS3 ¼ VGS4 ¼ VT þ : (7.13)
K
328 7 Active Resistor Circuits

VDD

IO IO

I1 I2 I1
I2
M5 I1 I2 M6
M1 M2
I1 - I2 I1 - I2
V1 M3
M4 V2
I1 - I2
I1 - I2

Fig. 7.4 Active resistor with positive equivalent resistance based on PR 7.1 – first implementation

VDD

IO IO

I1 I2 I1
I2

I1 I2
M1 M2
I2 -I1 I2 -I1
V1 M3
M4 V2
I2 -I1
I2 -I1

Fig. 7.5 Active resistor with negative equivalent resistance based on PR 7.1 – first
implementation

The equivalent resistance of the entire structure can be set by choosing the value
of the biasing current, IO :

V1
V2 1 1
RECH ¼ ¼ ¼ pffiffiffiffiffiffiffiffiffiffi : (7.14)
I1
I2 Gm 8KIO

In order to obtain an active resistor circuit with negative equivalent resistance

based on the previous active resistor structure, two input–output cross-connections
can be used. The resulting active resistor circuit, using the block diagram presented
in Fig. 7.2, is shown in Fig. 7.5.
7.2 Analysis and Design of Active Resistor Circuits 329

VDD

IO
IO IO

I1 I2 I2
I1
I1-I2 I1-I2
V1 M1 M3 M5 M6 M4 M2 V2

VO VO

Fig. 7.6 Active resistor with positive equivalent resistance based on PR 7.1 – second
implementation

The equivalent resistance of the active resistor structure is:

V1
V2 1 1
RECH ¼ ¼
¼
pffiffiffiffiffiffiffiffiffiffi : (7.15)
I2
I1 Gm 8KIO

An alternative implementation of the active resistor circuit with positive equiv-

alent resistance using the same principle is presented in Fig. 7.6. The VO voltage
sources from Fig. 7.3 are practically implemented in Fig. 7.6 using the gate-source
voltages of M5 and M6 transistors, biased at a constant current, IO . Similar with the
active resistor presented in Fig. 7.4, two parallel-connected differential amplifiers
(M1–M2 and M3–M4) have been used in order to generate two output currents I1
and two output currents I2 . The expression of the equivalent resistance of the
structure presented in Fig. 7.6 is also given by (7.14).
Similar input–output cross-connections allow to obtain a negative resistance
active resistor circuit (Fig. 7.7).
The active resistor circuit presented in Fig. 7.8 [3, 4] is based on the same
operation principle. The M3–M4 and M5–M6 pairs implement two current mirrors,
necessary to extract I1 and I2 currents from the circuit, in order to compute I12 ¼
I1
I2 current. The VC is a DC potential which fixes the value of the equivalent
resistance between the input pins and sets ID7 and ID8 current to be equal with IO
current. The VO generators are voltage sources, controlled by IO current.
Because M1 and M3 transistors are identical and biased at the same drain
current, it results VGS1 ¼ VGS3 , so:

V1
VX
VGS1 ¼ : (7.16)
2
330 7 Active Resistor Circuits

VDD

IO IO IO

I1 I1 I2 I2
I2-I1 I2-I1
V1 M1 M3 M5 M6M4 M2 V2

VO
VO

Fig. 7.7 Active resistor with negative equivalent resistance based on PR 7.1 – second
implementation

I2 VDD I1

I1 I2
I12 I12
V1 M1 M2 V2
I1 I2
IO IO
M3 M4 M5 M6

I I’

- + IO1 IO2 + -
VX VY
IO A VC B IO 2I2
2I1 VO VO
M7 M8

Fig. 7.8 Active resistor with positive equivalent resistance based on PR 7.1 – third principle
implementation
7.2 Analysis and Design of Active Resistor Circuits 331

VDD

M3 M4 M5
2K

M6 M7 M8
2K

I2 I1

I1 I2
I12 M1a M2a I12
V1 M1 9K M2 V2
9K
I1 I2
M1b M2b
M9 9K 9K
M1’ M12 M2’
M1c M2c
9K 9K
VX IO IO VY 2I2 2I2
2I1 2I1
IO IO
M10 VC M11

Fig. 7.9 Active resistor with positive equivalent resistance based on PR 7.1 – third complete
implementation

where VX ¼ V2
VO . It results:

V1
V2 þ VO
VGS1 ¼ (7.17)
2

and, similarly:

V2
V1 þ VO
VGS2 ¼ : (7.18)
2
So, the differential current, I12 ¼ I1
I2 , can be expressed as follows:

K K K
I12 ¼ ðVGS1
VT Þ2
ðVGS2
VT Þ2 ¼ ðV1
V2 ÞðVO
2VT Þ: (7.19)
2 2 2
Thus, the active resistor presented in Fig. 7.8 has an equivalent resistance,
expressed by:

V1
V2 2
RECH ¼ ¼ : (7.20)
I12 KðVO
2VT Þ

The complete circuit implementation is presented in Fig. 7.9 [3, 4]. The VC is an
externally applied potential, used to control the value of equivalent resistance (VO
depends on IO current, which is fixed by VC potential).
332 7 Active Resistor Circuits

Fig. 7.10 The ðI1
I2 Þ ðV1
V2 Þ simulation for the active resistor presented in Fig. 7.9

The current-controlled voltage generators, VO from Fig. 7.8 have been replaced
in Fig. 7.9 by two series connections of three MOS transistors (M1a, M1b, M1c and
M2a, M2b, M2c, respectively). The VO voltage can be expressed as follows:

rffiffiffiffiffiffiffi! rffiffiffiffirffiffiffiffi
2IO 2 K
VO ¼ 3VGS ðIO Þ ¼ 3 VT þ ¼ 3VT þ ðVC
VT Þ ¼ VC þ 2VT :
9K K 2
(7.21)

From (7.20) and (7.21), it results an expression of the equivalent resistance of the
circuit presented in Fig. 7.9, that does not depend on the threshold voltage:

1
RECH ¼ : (7.22)
2KVC

The ðI1
I2 Þ ðV1
V2 Þ simulation for the active resistor presented in Fig. 7.9 is
shown in Fig. 7.10.
In order to estimate the linearity of the circuit, the active resistor is compared
with an ideal resistor, resulting the simulated linearity error presented in Fig. 7.11.
The maximum linearity error of the active resistor presented in Fig. 7.9 for a
limited input voltage range (jV1
V2 j  500 mV) is smaller that 0:35%.
The circuit presented in Fig. 7.8 can be changed, in order to obtain an active
resistor with negative equivalent resistance, resulting the circuit presented in
Fig. 7.12 [3, 4].
It exists the possibility of implementing an active resistor circuit based on the
same linearization principle, using FGMOS transistors (Fig. 7.13) [3–5]. The V1
and V2 are the output pins of the active resistor, I12 is the current passing between
these terminals, VC is a DC potential which controls the value of the equivalent
7.2 Analysis and Design of Active Resistor Circuits 333

Fig. 7.11 The simulated linearity error for the active resistor circuit presented in Fig. 7.9

I2 I1

VDD

I12 M2 I12
V1 M1 V2
I1 I2
IO IO
M3 M4 M5 M6

I I’

- + IO1 IO2 + -
VX VY
IO A VC B IO 2I2
2I1 VO VO
T7 T8

Fig. 7.12 Active resistor with negative equivalent resistance based on PR 7.1 – third principle
implementation
334 7 Active Resistor Circuits

I1 I2 V1 I1 I2

I1 I2
I12

M3 M1 M2 M4

I12
VO VO
- + + -
V2

2I1 IO IO VC IO IO 2I2

M5 M6

Fig. 7.13 Active resistor with positive equivalent resistance based on PR 7.1 – fourth principle
implementation

resistance between the input pins and sets ID5 and ID6 currents to be equal to IO
current. The VO generators are voltage sources, controlled by the IO current, while
I1 and I2 are intern currents of the active resistor.
Considering a biasing in saturation of all MOS transistors, I1 and I2 currents can
be expressed as follows:
 2  2
K V1 þ V2 K V1
V2
I1 ¼
ðV2
VO Þ
VT ¼ þ ðVO
VT Þ (7.23)
2 2 2 2

and:
 2  2
K V 1 þ V2 K V2
V1
I2 ¼
ðV1
VO Þ
VT ¼ þ ðVO
VT Þ : (7.24)
2 2 2 2

The expression of the I12 differential current becomes:

I12 ¼ I1
I2 ¼ K ðV1
V2 ÞðVO
VT Þ; (7.25)

resulting an equivalent resistance of the entire structure, expressed by the following

relation:

V1
V2 1
RECH ¼ ¼ : (7.26)
I12 KðVO
VT Þ
7.2 Analysis and Design of Active Resistor Circuits 335

VDD

I2 I1
V1
I1 I1 I2 I2
I12

M1a I12 M2a

V2
M1b M2b
2I1 IO IO 2I2
IO VC IO

Fig. 7.14 Active resistor with positive equivalent resistance based on PR 7.1 – fourth complete
implementation

In order to avoid the degradation of circuit linearity caused by the bulk effect, a
proper implementation of the current-controlled voltage sources VO from Fig. 7.13
has been realized in Fig. 7.14. For this particular choice, the VO voltage can be
expressed as follows:

rffiffiffiffiffiffiffi!
2IO
VO ¼ VGS1a þ VGS1b ¼ VGS2a þ VGS2b ¼ 2 VT þ ; (7.27)
4K

because M1a, M1b, M2a and M2b transistors (having the aspect ratio fourth time
greater than the other transistors from the circuit) are biased at the same constant
current, IO . The precision of the entire structure presented in Fig. 7.14 [3–5] will be
not affected by the bulk effect:

1 1
RECH ¼  qffiffiffiffiffi ¼ : (7.28)
K VT þ 2 4K
2IO KV C

Another active resistor circuit having the possibility of applying between the
input pins both positive and negative voltages, is presented in Fig. 7.15, this
additional feature being possible using a double supply voltage.
336 7 Active Resistor Circuits

VDD

M12 M13 M14

I1 2I1 I1
M9 M10 M11

I2 2I2 I2

M1 M7 M5 M6 M8 M2
V1 V2
I12 I2 IO IO I1 I12
V V’

I
I’
2I2
2I1
M15 M16 M3 VC M4 M17 M18

Fig. 7.15 Active resistor with positive equivalent resistance based on PR 7.1 – fifth
implementation

Because of the multiple current mirrors, I and I0 currents are zero and
I12 ¼ I2
I1 . The equivalent resistance of the circuit is:

V1
V2
RECH ¼ : (7.29)
I12

The expression of I1 current is:

K
ðV2
V 0
VT Þ ;
2
I1 ¼ (7.30)
2

where V 0 ¼ V1
VGS5 . As M3 and M5 transistors are identical and biased at the

same drain current, their gate-source voltages will be also equal, so
VGS5 ¼ VGS3 ¼ VC . It results:

V 0 ¼ V1
VC : (7.31)

The expression of I1 current becomes:

K
I1 ¼ ½ðV2
V1 Þ þ ðVC
VT Þ2 (7.32)
2
7.2 Analysis and Design of Active Resistor Circuits 337

VDD

M12 M13 M14

I1 2I1 I1
M9 M10 M11

I2 2I2 I2

M1 M7 M5’ M8 M2
V1 M6’ V2
I12 I2 IO IO I1 I12
V M5’’ V’
M6’’
I
I’
2I2
2I1
M15 M16 M3 VC M4 M17 M18

Fig. 7.16 Active resistor with positive equivalent resistance based on PR 7.1 – fifth improved
implementation

and, similarly:

K
I2 ¼ ½ðV1
V2 Þ þ ðVC
VT Þ2 : (7.33)
2
The I12 differential current can be expressed as follows:

I12 ¼ I2
I1 ¼ 2K ðV1
V2 ÞðVC
VT Þ: (7.34)

The equivalent resistance of the entire structure presented in Fig. 7.15 will have
the following expression:

V1
V2 1
RECH ¼ ¼ : (7.35)
I12 2K ðVC
VT Þ

In order to remove the dependence of the equivalent resistance on the threshold

voltage, it can be used an improved circuit, presented in Fig. 7.16.
The M5 and M6 transistors from Fig. 7.15 have been replaced by two series
connections, M5’–M5” and M6’–M6”, respectively, all these four transistors having
aspect ratios fourth time greater than the other transistors from the circuit. Now,
V 0 ¼ V1
2VGS50 , where:
rffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffi
2ID50 2ID3
VGS50 ¼ VT þ ¼ VT þ
4K 4K
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi (7.36)
1 K VC þ VT
¼ VT þ ðVC
VT Þ2 ¼ ;
2K 2 2
338 7 Active Resistor Circuits

Fig. 7.17 Linear differential

amplifier with proper current I1 I2
biasing

V1 V2

I O’
i1

I
IO

SQ

resulting:

V 0 ¼ V1
VT
VC : (7.37)

The expression of I1 current becomes:

K
I1 ¼ ½ðV2
V1 Þ þ VC 2 (7.38)
2
and, similarly:

K
I2 ¼ ½ðV1
V2 Þ þ VC 2 : (7.39)
2
The I12 differential current can be expressed as follows:

I12 ¼ I2
I1 ¼ 2KVC ðV1
V2 Þ: (7.40)

The equivalent resistance of the entire structure presented in Fig. 7.16 will be
independent on the threshold voltage:

V1
V2 1
RECH ¼ ¼ : (7.41)
I12 2KVC

Another possible implementation of a linear differential amplifier is based on a

proper current biasing of a classical differential amplifier. The method (Fig. 7.17)
[6] for obtaining a linear transfer characteristic of the differential amplifier is to
obtain the IO 0 biasing current of the entire differential structure as a sum of a main
constant term, IO and an additional term, proportional with the squaring of the
differential input voltage, I ¼ KðV1
V2 Þ2 =4:

K
IO 0 ¼ IO þ I ¼ IO þ ðV1
V2 Þ2 ; (7.42)
4
7.2 Analysis and Design of Active Resistor Circuits 339

VDD

I2 I1

I1 I1 I2 I2
I12
V1 I12 V2

IO’
i1

I
IO
SQ

Fig. 7.18 Active resistor with positive equivalent resistance based on PR 7.1 – sixth
implementation

resulting, in this case, a perfect linear behavior of the optimized differential

amplifier:
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
V 1
V2
I1
I2 ¼ 4KIO 0
K 2 ðV1
V2 Þ2
pffiffiffiffiffiffiffiffi 2 (7.43)
¼ KIO ðV1
V2 Þ ¼ Gm ðV1
V2 Þ;

Gm being the equivalent transconductance of the proposed structure, that can be

controlled by the biasing current, IO .
Based on the block diagram presented in Fig. 7.1, the improved linearity
differential cell presented in Fig. 7.17 can be re-used in order to obtain an original
active resistor with excellent linearity, having the circuit presented in Fig. 7.18 [6].
For this circuit, the current passing through the input pins, I12 , can be expressed
as follows:
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
V1
V2
I12 ¼ I1
I2 ¼ 4KIO 0
K 2 ðV1
V2 Þ2 : (7.44)
2
Because the biasing current of the circuit core, IO 0 , was designed to be the sum of
a main constant term IO , and an additional term proportional with the squaring of
the differential input voltage:

K
IO 0 ¼ IO þ ðV1
V2 Þ2 ; (7.45)
4
340 7 Active Resistor Circuits

VDD

I2 I1

I1 I1 I2 I2
I12 I12
V1 V2

IO ’
i1

I
IO
SQ

Fig. 7.19 Active resistor with negative equivalent resistance based on PR 7.1 – sixth
implementation

the I12 current will have the following expression:

pffiffiffiffiffiffiffiffi
I12 ¼ KIO ðV1
V2 Þ: (7.46)

Defining the equivalent resistance of the circuit from Fig. 7.18 as the ratio
between the V1
V2 differential input voltage and the current passing through
the input pins, I12 , it results:

V1
V2 1
RECH ¼ ¼ pffiffiffiffiffiffiffiffi : (7.47)
I12 KIO

The circuit presents the advantage of controllability (the active resistance RECH
can be changed by modifying the IO biasing current).
Using the active resistor with positive equivalent resistance presented in
Fig. 7.18, in order to obtain a circuit with controllable negative resistance circuit,
it is necessary to use two input–output cross-connections, resulting the circuit
presented in Fig. 7.19 [6]. Because now I12 ¼ I2
I1 , the equivalent resistance of
the circuit from Fig. 7.19 will be:

1
RECH 0 ¼
RECH ¼
pffiffiffiffiffiffiffiffi : (7.48)
KIO
7.2 Analysis and Design of Active Resistor Circuits 341

V1 M V2

IO IO
T T
V
V1T V2T
DA

IOUT IOUT

Fig. 7.20 Active resistor with positive equivalent resistance based on PR 7.2 – block diagram

7.2.2 Active Resistor Circuits Based on the Second

Mathematical Principle (PR 7.2)

The linearization techniques based on the second mathematical principle uses a

proper biasing of a classical differential amplifier, that modifies the transfer char-
acteristic of this circuit, in order to obtain a linear behavior for the resulting active
resistor structure.
The block diagram of active resistor circuit using the second mathematical
principle is presented in Fig. 7.20. The output currents of the “DA” block from
Fig. 7.20 [4, 7] are forces to pass through the input pins, implementing, in this way,
a linear current–voltage characteristic, IOUT ðV1
V2 Þ, for the active resistor struc-
ture, so a constant equivalent resistance of the structure.

7.2.2.1 The “DA” (Differential Amplifier) Block

The “DA” block is implemented as a classical active-load differential amplifier,

having the concrete realization presented in Fig. 7.21. Considering a biasing in
saturation of MOS devices from Fig. 7.21 [4, 7, 8], the output current of the
differential amplifier can be expressed as:

K
IOUT ¼ I2
I1 ¼ ðV1T
V2T Þð2V
V1T
V2T
2VT Þ: (7.49)
2

In order to obtain a linear transfer characteristic, IOUT ðV1T
V2T Þ, it is necessary

that the value from the second parenthesis from (7.49) to be constant with respect to
the differential input voltage V1T
V2T :

2V
V1T
V2T
2VT ¼ A ¼ ct:; (7.50)

342 7 Active Resistor Circuits

Fig. 7.21 Active resistor V

with positive equivalent
resistance based on PR 7.2 –
DA block implementation
V2T V1T
M1a M1a’

I2 I1 IOUT

M2a M2a’

M1b M1b’

IOUT I2 I1

M2b M2b’

resulting the necessity of implementing a V voltage equal with:

V1T þ V2T A
V¼ þ VT þ ; (7.51)
2 2

7.2.2.2 The “T” (Translation) Block

The translation of the V potential by VT þ A=2 can be obtained using “T” block,
having the implementation presented in Fig. 7.22 [4, 7].
Because the same IO current is passing through both transistors from Fig. 7.22, it
can be obtained:
rffiffiffiffiffiffiffi
2IO
V1 ¼ V1T þ VT þ (7.52)
K
7.2 Analysis and Design of Active Resistor Circuits 343

Fig. 7.22 Active resistor

with positive equivalent
resistance based on PR 7.2 – IO IO
T block implementation

V1 M9 M9’ V2

V1T V2T

IO /2 IO /2

M14 M15 M15’ M14’

V1 V2

IO IO
V

Fig. 7.23 Active resistor with positive equivalent resistance based on PR 7.2 – M block
implementation

and:
rffiffiffiffiffiffiffi
2IO
V2 ¼ V2T þ VT þ : (7.53)
K

So, both V1 and V2 input potentials are DC shifted with the same amount,
pffiffiffiffiffiffiffiffiffiffiffiffiffi
VT þ 2IO =K .

7.2.2.3 The “M” (Arithmetic Mean) Block

In order to obtain the arithmetic mean of input potentials expressed by (7.51), an

arithmetical mean circuit must be used (Fig. 7.23) [4, 7], this particular implementation
having the advantage of containing only MOS transistors, biased in saturation region.

V1 þ V2
V¼ : (7.54)
2
It can be obtained:
rffiffiffiffiffiffiffi
V1T þ V2T 2IO
V¼ þ VT þ : (7.55)
2 K
344 7 Active Resistor Circuits

VDD

M11 M12 M12’ M11’

M10 M13 M13’ M10’

IO/2 “M” IO/2
“T” “T”
V1 M9 M14 M15 M15’ M14’ M9’ V2
0
3I1 IO 3I2
IO
V
I1 I2
M1b M1b’
V1T V2T
M1a M1a’
M5 I1 I2 M5’
IO I1 I2 IO
IO
M4 M3 M3’ M4’
M16 M6 M8 M2a M2a’ M8’ M6’

“DA”
IOUT M2b M2b’ IOUT

Fig. 7.24 Active resistor with positive equivalent resistance based on PR 7.2 – complete
implementation
pffiffiffiffiffiffiffiffiffiffiffiffiffi
Comparing (7.51) and (7.55) relations, it results that A ¼ 2 2IO =K , so:
rffiffiffiffiffiffiffi
K 2IO pffiffiffiffiffiffiffiffiffiffi
IOUT ¼ ðV1T
V2T Þ2 ¼ 2KIO ðV1T
V2T Þ: (7.56)
2 K

And, by using (7.52) and (7.53), equivalent with:

pffiffiffiffiffiffiffiffiffiffi
IOUT ¼ 2KIO ðV1
V2 Þ ¼ Gm ðV1
V2 Þ; (7.57)
pffiffiffiffiffiffiffiffiffiffi
Gm ¼ 2KIO being the equivalent transconductance of the differential ampli-
fier. As a result of using translation blocks, the Gm transconductance of the
differential core will be not dependent on the threshold voltage, so the active
resistor linearity will be not affected by the bulk effect.
Because the output currents of the “DA” block are forces to pass through the
input pins (Fig. 7.20), a linear current–voltage characteristic, IOUT ðV1
V2 Þ, of
the active resistor structure will be obtained. So, a constant equivalent resistance of
the entire structure from Fig. 7.20 can be achieved:

V1
V2 1 1
RECH ¼ ¼ ¼ pffiffiffiffiffiffiffiffiffiffi : (7.58)
IOUT Gm 2KIO

The full implementation of the active resistor circuit is presented in Fig. 7.24 [4, 7].
7.2 Analysis and Design of Active Resistor Circuits 345

V1 M V2

IO IO
T T
V
V1T V2T
DA
IOUT IOUT

Fig. 7.25 Active resistor with negative equivalent resistance based on PR 7.2 – block diagram

VDD

M11 M12 M12’ M11’

M10 M13 M13’ M10’

IO/2 “M” IO/2
“T”
“T”
V1 M9 M14 M15 M15’ M14’ M9’ V2
0
3I1 IO 3I2
IO
V
IOUT
I1 I2
M1b M1b’
V1T V2T
M1a M1a’
IO M5 I1 I2 M5’
I1 I2 IO
IO
M4 M3 M3’ M4’
M16 M6 M2a M2a’ M6’
M8 M8’

“DA”
M2b M2b’
IOUT

Fig. 7.26 Active resistor with negative equivalent resistance based on PR 7.2 – complete
implementation

In order to obtain an active resistor circuit with negative equivalent resistance,

the senses of the output currents of “DA” block must be inversed, resulting the
block diagram presented in Fig. 7.25 [4].
The implementation of the active circuit with negative resistance is presented in
Fig. 7.26 [4, 7], the equivalent resistance of this structure being:

1 1
RECH 0 ¼
¼
pffiffiffiffiffiffiffiffiffiffi : (7.59)
Gm 2KIO
346 7 Active Resistor Circuits

Fig. 7.27 Active resistor

with positive equivalent IO
resistance based on PR 7.3 –
block diagram
DA

I12

I12 I12
V1 I V2

7.2.3 Active Resistor Circuits Based on the Third Mathematical

Principle (PR 7.3)

The method for designing a linear active resistor based on the third mathematical
principle consists in passing, between two pins, of a current obtained from the
output of a differential amplifier; these pins represents the inputs of the differential
circuit. This current will be linearly dependent on the differential input voltage, so
the equivalent resistance between these two pins will be equal with 1=Gm (Gm is the
transconductance of the differential amplifier).

V1
V2 1
RECH: ¼ ¼ : (7.60)
I12 Gm

The block diagram of this active resistor is presented in Fig. 7.27 [4, 8–10].
The “DA” block is a linear differential structure and “I” block represents a
“current pass” circuit. Its goal is to “pass” a current received at its input between
two pins (V1 and V2 ). A possible implementation of the current pass block is
presented in Fig. 7.28 [4, 11], consisting in a simple and a multiple current mirror.
As a result of the quadratic characteristic of a MOS transistor operating in
saturation, the transfer characteristic of the classical CMOS differential amplifier
will be strongly nonlinear, its linearity being in reasonable limits only for a very
limited range of the differential input voltage amplitudes.
There are many possibilities of improving the linearity of the classical differen-
tial amplifier. The method used for increasing the linearity of the active resistor
circuit having the block diagram presented in Fig. 7.27 is based on the compensa-
tion of quadratic characteristic of the MOS transistor working in saturation region
by two identical current-mode square-root circuits. The result will be a more linear
transfer characteristic of the circuit, quantitatively evaluated by an important
reduction of the total harmonic distortions of the differential amplifier (Fig. 7.29)
[4, 9, 10, 12].
7.2 Analysis and Design of Active Resistor Circuits 347

Fig. 7.28 Active resistor VDD

with positive equivalent
resistance based on PR 7.3 –
current-pass block
implementation
I12
I12
V2

V1
I12

-VDD

VDD

I1’ IO IO I2’
SQR SQR

I1 I2
M1 M2
V1 V2
I12
I1 + I2

Fig. 7.29 Active resistor with positive equivalent resistance based on PR 7.3 – linear DA block
implementation

A possible implementation of the square-root circuits from Fig. 7.29 is shown in

Fig. 7.30 [4, 10, 12], representing a perfect symmetrical structure using MOS
transistors and a FGMOS device.
The expression of I current is:

   2
4K VGS ðIO Þ þ VGS I1;2
I¼
VT
2 2 (7.61)
pffiffiffiffiffi pffiffiffiffiffiffiffi2 pffiffiffiffiffiffiffiffiffiffiffi
¼ IO þ I1;2 ¼ IO þ I1;2 þ 2 IO I1;2 :
348 7 Active Resistor Circuits

VDD

I1,2’

IO
I1,2 IO I

M
4K

M1,2 MO
K K

Fig. 7.30 Active resistor with positive equivalent resistance based on PR 7.3 – square-root block
implementation

The output current of the square-root circuit from Fig. 7.30 will have the
following square-root dependence on I1;2 and IO currents:
pffiffiffiffiffiffiffiffiffiffiffi
I1;2 0 ¼ I
IO
I1;2 ¼ 2 I1;2 IO : (7.62)

Considering this square-root dependencies of I1 0 and I2 0 currents on I1 and I2

currents, the output current of the differential amplifier from Fig. 7.29, I12 , can be
expressed as:
pffiffiffiffiffipffiffiffiffi pffiffiffiffi
I12 ¼ I1 0
I2 0 ¼ 2 IO I1
I2 ; (7.63)

resulting:
pffiffiffiffiffiffiffiffiffiffi
I12 ¼ 2KIO ðVGS1
VGS2 Þ; (7.64)

VGS1 and VGS2 being the gate-source voltages of M1 and M2 transistors from
Fig. 7.29. It results a linear transfer characteristic of the differential amplifier:

I12 ¼ Gm ðV1
V2 Þ; (7.65)

pffiffiffiffiffiffiffiffiffiffi
where Gm is the circuit transconductance, Gm ¼ 2KIO . So, in a first-order analy-
sis, the dependence of the differential circuit output current on its differential input
voltage will be perfectly linear.
7.2 Analysis and Design of Active Resistor Circuits 349

Fig. 7.31 Active resistor VDD

with negative equivalent
resistance based on PR 7.3 –
current-pass block
implementation
I12
I12
V1

V2
I12

-VDD

The equivalent resistance of the circuit presented in Fig. 7.27 will have the
following expression:

1
RECH: ¼ pffiffiffiffiffiffiffiffiffiffi (7.66)
2KIO

and it can be controlled by the IO biasing current.

An advantage of the active resistor presented in Fig. 7.27 is that a circuit with a
negative equivalent resistance can be obtained by a minor change in the current-
pass circuit presented in Fig. 7.28. The modified implementation of the current-pass
circuit that can be used for obtaining an active resistor with a negative equivalent
resistance is presented in Fig. 7.31 [13].
The resulting expression of the active resistance will be RECH 0 ¼
RECH ¼
pffiffiffiffiffiffiffiffiffiffi

1=2 2KIO .

7.2.4 Active Resistor Circuits Based on the Fourth

Mathematical Principle (PR 7.4)

The structure of the active resistor circuit based on the fourth mathematical
principle contains three important blocks (Fig. 7.32) [4, 14]: a voltage-current
squarer, “SQ”, a current square-root circuit, “SQR”, and a current-pass circuit, “I”.
The I12 current is proportional with the square-root of IOUT and IO currents, while
IOUT current is proportional with the square of the differential input voltage,
V1
V2 . So, the result will be a linear relation between the differential voltage
across the input pins of the active resistor and the current passing between them.
350 7 Active Resistor Circuits

SQ

IOUT

IO
SQR

I12

I12 I12
V1 I V2

Fig. 7.32 Active resistor with positive equivalent resistance based on PR 7.4 – block diagram

VDD

IOUT

I3
I1 I3 I2

M1 M3 M2
V1 K 2K K V2

-VDD

Fig. 7.33 Active resistor with positive equivalent resistance based on PR 7.4 – squaring circuit
implementation

The current squaring circuit is based on the perfect symmetrical structure,

presented in Fig. 7.33 [15]. The utilization of a FGMOS device decreases the
silicon occupied area of this circuit.
The output current expression has a linear dependence on the drain currents of
M1, M2 and M3 transistors:

IOUT ¼ I1 þ I2
I3 : (7.67)

Considering a biasing in saturation of all MOS devices from Fig. 7.33, the
previous currents will have the following expressions:

K
I1 ¼ ðV1
VS
VT Þ2 ; (7.68)
2
7.2 Analysis and Design of Active Resistor Circuits 351

Fig. 7.34 Active resistor VDD

with positive equivalent
resistance based on PR 7.4 –
square-root circuit
implementation

IOUT IO I12

K 4K

K 4K
IO
I

K
I2 ¼ ðV2
VS
VT Þ2 ; (7.69)
2
2
V1 þ V2
I3 ¼ K
VS
VT : (7.70)
2

From the previous relations, it results a quadratic dependence of the output

current, IOUT , on the V1
V2 differential input voltage:

K
IOUT ¼ ðV1
V2 Þ2 : (7.71)
4
The square-root circuit is presented in Fig. 7.34, designed using exclusively
MOS active devices biased in the saturation region.
The relation between the currents from the circuit is:
rffiffiffiffiffiffiffiffiffiffiffiffi! rffiffiffiffiffiffiffi! rffiffiffiffiffiffi!
2IOUT 2IO 2I
VT þ þ VT þ ¼ 2 VT þ ; (7.72)
K K 4K

equivalent with:
pffiffiffiffiffiffiffiffiffiffiffiffiffi
I ¼ IOUT þ IO þ 2 IOUT IO : (7.73)

Implementing the proper linear relation between the previous currents of the
square-root circuit:

I12 ¼ I
IOUT
IO ; (7.74)

the output current of the circuit from Fig. 7.34 will be proportional with the square-
root of the input current:
pffiffiffiffiffiffiffiffiffiffiffiffiffi
I12 ¼ 2 IOUT IO : (7.75)
352 7 Active Resistor Circuits

The current-pass circuit, I, has the implementation presented in Fig. 7.28.

Because of the complementary characteristics (7.71) and (7.75) of the squaring
and square-root circuits, the I12 ðV1
V2 Þ current–voltage characteristic of the
active resistor will be linear.
pffiffiffiffiffiffiffiffi
I12 ¼ KIO ðV1
V2 Þ: (7.76)

It is possible to define an equivalent resistance of the circuit presented in

Fig. 7.32 as:

V1
V2
RECH: ¼ ; (7.77)
I12
resulting:
1
RECH: ¼ pffiffiffiffiffiffiffiffi : (7.78)
KIO

The advantage of the active resistor circuit is that the value of the equivalent
active resistance can be controlled by modifying the reference current IO .

7.2.5 Active Resistor Circuits Based on the Fifth

Mathematical Principle (PR 7.5)

The active resistor based on the fifth mathematical principle has the block diagram
presented in Fig. 7.35, [4, 12] and it uses three important types of blocks:
• Two linearized differential amplifiers for converting the V1
V2 input voltage
and the VO reference voltage in two currents that will be inserted into the
multiplier circuit. The most important requirements for these differential
amplifiers are referring to the linearity of the transfer characteristics, associated
with the maximization of their input voltage ranges that allows a good linearity,
to the common mode input range and to the independence of the circuit
performances on the second-order effects. The currents generated by the differ-
ential amplifiers will be proportional with their input voltages, I1 ¼ Gm VO and
I2 ¼ Gm ðV1
V2 Þ;
• A current-mode multiplier circuit, “MULT”, for “mirroring” the Ohm law,
whose operation is described by the relation I12 ¼ IO I2 =I1 ;
• A current-pass circuit, which imposes the condition that the same current to pass
between the V1 and V2 input pins
Consider that DA1 and DA2 differential amplifiers from Fig. 7.35 are
implemented using the linearization technique proposed in Fig. 7.29. So:
pffiffiffiffiffiffiffiffi
I2 ¼ 2KI ðV1
V2 Þ; (7.79)
pffiffiffiffiffiffiffiffi
I1 ¼ 2KI VO ; (7.80)
7.2 Analysis and Design of Active Resistor Circuits 353

Fig. 7.35 Active resistor (1) VO

with positive equivalent
resistance based on PR 7.5 –
block diagram
DA I
I1
IO I12
MULT
I2

DA II

I12
I12 I12
V1 V2
I

I biasing current replacing the IO current from Fig. 7.29. Defining the equivalent
resistance between V1 and V2 pins as the ratio between the V1
V2 differential
input voltage and the current passing through these pins, I12 , it results:

V1
V2 VO
RECH ¼ ¼ : (7.81)
I12 IO

In conclusion, the active resistor presented in Fig. 7.35 will have an equivalent
resistance that can be controlled by modifying the ratio of the VO reference voltage
and the IO reference current.
A possible method for obtaining the multiplying function using the previous
designed square-root circuit is to use two identical circuits presented in Fig. 7.29,
implementing the following functions:
pffiffiffiffiffiffiffiffi
IOUT1 ¼ 2 IO I2 (7.82)

and:
pffiffiffiffiffiffiffiffiffi
IOUT2 ¼ 2 I12 I1 ; (7.83)

IOUT1 and IOUT2 being the output currents of these square-root circuits. Using a
classical current mirror, it is possible to impose IOUT1 ¼ IOUT2 , resulting the neces-
sary multiplying function:

I2
I12 ¼ IO : (7.84)
I1
354 7 Active Resistor Circuits

In order to obtain an active resistor circuit with negative equivalent resistance,

the block diagram from Fig. 7.35 must be modified by inversing the sense of the I12
current passing through the I block, resulting an equivalent resistance expressed by:
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
0 VO ðW=LÞ1 IO1
RECH ¼
: (7.85)
IO ðW=LÞ2 IO2

An alternative method [15] for obtaining, using the fifth mathematical principle,
a linear current–voltage characteristic of the active resistor, similar with the char-
acteristic of a classical passive resistor, consists in the “mirroring” of the Ohm law
from the input pins of the circuit to another pins, used for applying an external
reference voltage and an external reference current. The equivalent resistance of the
active structure will be controllable by the ratio between the reference voltage and
the reference current. Because of the requirements for a good frequency response,
only MOS transistors working in saturation are used and a current-mode operation
of an important part of the circuit is implemented. A possible choice of the
complementary blocks that minimize the complexity of the entire structure is
referring to the squaring and square-rooting functions. In order to further reduce
the silicon occupied area, classical MOS devices have been replaced by FGMOS
transistors.
The structure of the active resistor is based on four important blocks: two
voltage-current squarers, a current square-root circuit, a current divider circuit
and a current-pass circuit, named SQ, SQR, DIV and I, respectively on the block
diagram from Fig. 7.36 [15].
The I12 current is proportional with the square-root of the product between I and
IO currents, while I is proportional with the ratio of I2 and I1 currents. Each of these
two last currents is proportional with the squaring of V1
V2 and VO voltages,
respectively. The result of this implementation of the circuit will be a linear relation
between the V1
V2 differential voltage across the input pins of the active resistor
and the current passing between these pins, I12 .
The current squaring circuits can be implemented using the circuit presented in
Fig. 7.33, resulting a quadratic dependence of the I2 output current on the V1
V2
differential input voltage:

K
I2 ¼ ðV1
V2 Þ2 : (7.86)
4
In a similar way, the other squarer from the block diagram will compute the
following expression of I1 current:

K 2
I1 ¼ V : (7.87)
4 O
7.2 Analysis and Design of Active Resistor Circuits 355

Fig. 7.36 Active resistor (2) VO

with positive equivalent
resistance based on PR 7.5 –
block diagram
SQ I
I1

I
IO DIV SQR IO

I2

SQ II

I12
I12 I12 V
V1 I 2

The current square-root block from Fig. 7.36 can be realized using the circuit
presented in Fig. 7.34, the output current being proportional with the square-root of
the input current:
pffiffiffiffiffiffiffi
I12 ¼ 2 IO I : (7.88)

The divider circuit can be obtained using two square-root circuits from Fig.
pffiffiffiffiffi7.34,
ffi
connected as it is shown in Fig. 7.37. The computed functions are IO1 ¼ 2 I1 I and
pffiffiffiffiffiffiffiffi
IO2 ¼ 2 I2 IO . Because IO1 ¼ IO2 , the function implemented by the circuit from
Fig. 7.37 [15] will be:

I2
I ¼ IO : (7.89)
I1

The current-pass circuit is similar with the structure presented in Fig. 7.28. Using
previous relations, it results that the equivalent resistance of the active resistor
having the block diagram presented in Fig. 7.36 is:

V1
V2 VO
RECH: ¼ ¼ : (7.90)
I12 2IO

An important advantage of the previous presented circuit is that the value of the
equivalent active resistance can be controlled by modifying the ratio of a reference
voltage, VO and a reference current, IO .
356 7 Active Resistor Circuits

VDD

I1 I IO I2

IO1 IO2

IREF IREF

Fig. 7.37 Active resistor (2) with positive equivalent resistance based on PR 7.5 – DIV block
implementation

7.2.6 Active Resistor Circuits Based on Different Mathematical

Principles (PR 7.D)

Active resistors based on different mathematical principles use MOS transistors

biased both in linear region and in saturation. A possible realization of an active
resistor is presented in Fig. 7.38 [16].
The M1 and M2 transistors are biased in linear region, while all other MOS
transistors are operated in saturation region. The I1 and I2 currents can be expressed
as follows:
 2

K VDS1
I1 ¼ VDS1 ðVGS1
VT Þ
(7.91)
2 2

and:
 
K V2
I2 ¼ VDS2 ðVGS2
VT Þ
DS2 : (7.92)
2 2

The M5–M6 current mirror imposes the identity between I1 and I2 currents, so
VGS3 ¼ VGS4 , resulting VDS1 ¼ VDS2 . Using (7.91) and (7.92), it results:

K
IIN ¼ I2
I1 ¼
VDS2 ðVGS2
VGS1 Þ
2 (7.93)
K K
¼ VDS2 ½ðVG2 þ VDD Þ
ð0 þ VDD Þ ¼ VDS2 VG2 :
2 2

The equivalent input impedance can be defined as follows:

VDS2 2
RECH ¼ ¼ : (7.94)
IIN KVG2
7.2 Analysis and Design of Active Resistor Circuits 357

Fig. 7.38 Active resistor (1) VDD

with positive equivalent
resistance based on PR 7.D
M6 M5

M4 M3
RECH
IIN

I2 I1
VG2 M2 M1

-VDD

The circuit simulates in the input pin an equivalent resistance, RECH , having a
value that can be controlled by a biasing potential VG2 .
Another possible realization of an active resistor circuit is presented in Fig. 7.39 [17].
The expressions of I1
I4 currents are:

K
I1 ¼ ðVC1
V1
VT Þ2 ; (7.95)
2

K
I2 ¼ ðVC1
V2
VT Þ2 ; (7.96)
2

K
I3 ¼ ðVC2
V1
VT Þ2 ; (7.97)
2

K
I4 ¼ ðVC2
V2
VT Þ2 : (7.98)
2

Because of M16–M17 and M20–M21 current mirrors, I7 ¼ 2I1 and I10 ¼ 2I2 .
The I and I 0 currents can be expressed using a linear relation containing the previous
currents:

I ¼ I0 ¼ I1 þ I4
I2
I3 (7.99)

resulting:

K
I ¼ I0 ¼ ðV2
V1 Þð2VC1
V1
V2
2VT Þ
2 (7.100)
K
þ ðV1
V2 Þð2VC2
V1
V2
2VT Þ:
2
358 7 Active Resistor Circuits

VDD

M5 M6 M7 M8 M9 M10 M11 M12 M13 M14

VC1
M1 M2
VC 2
M3 M4
I I3 I1 I2 I1 I2 I4 I’
V1 V2

I7 I4
I3 I10

M15 M16 M17 M18 M19 M20 M21 M22

K 2K 2K K

-VDD

Fig. 7.39 Active resistor (2) with positive equivalent resistance based on PR 7.D

So:

I ¼ I0 ¼ K ðVC2
VC1 ÞðV1
V2 Þ: (7.101)

The equivalent resistance of the active structure presented in Fig. 7.39 can be
expressed as follows:

V1
V2 V1
V2 1
RECH ¼ ¼ ¼ (7.102)
I I0 K ðVC2
VC1 Þ

and it can be controlled using VC2
VC1 differential voltage.

Another implementation of an active resistor circuit using exclusively MOS
transistors biased in saturation is presented in Fig. 7.40 .
The I current can be expressed as a linear function on the currents from the
circuit:

I ¼ I2
I1
I5 þ I6 : (7.103)

Because I6 ¼ 2I1 and I5 ¼ 2I2 , it results:

I ¼ I1
I2 : (7.104)

Similarly, the I0 current will have the following expression:

I 0 ¼ I2
I1 þ I7
I8 : (7.105)

Using I7 ¼ 2I1 and I8 ¼ 2I2 relations (implemented using different aspect ratios
MOS transistors), it can be obtained:

I 0 ¼ I1
I2 : (7.106)
7.2 Analysis and Design of Active Resistor Circuits 359

VDD

M1 M2 M3
K 2K

M4 M5 M6
2K K
M7 M8

I5 I1 IO IO I2 I7 M9
V’
M10 M11 IO
I I’
V1 V V2

I6 I2 M12 M13 I1 I8
M14 M15 M16 M18 M19
M17
2K K K 2K

-VDD

Fig. 7.40 Active resistor (3) with positive equivalent resistance based on PR 7.D

So, the same current I ¼ I0 will pass between the inputs, being expressed by the
following relation:

K K
I ¼ I0 ¼ ðV
V1
VT Þ2
ðV 0
V2
VT Þ :
2
(7.107)
2 2

As the drain current of M12 transistor is imposed to be IO , their gate-source

voltage will be equal with:
rffiffiffiffiffiffiffi
0 2IO
V
V1 ¼ VT þ : (7.108)
K

Thus:
rffiffiffiffiffiffiffi
0 2IO
V ¼ V1 þ VT þ : (7.109)
K

Similarly:
rffiffiffiffiffiffiffi
2IO
V
V2 ¼ VT þ : (7.110)
K

So:
rffiffiffiffiffiffiffi
2IO
V ¼ V2 þ VT þ : (7.111)
K
360 7 Active Resistor Circuits

From (7.107), (7.109) and (7.111), it results:

rffiffiffiffiffiffiffi!2 rffiffiffiffiffiffiffi!2
K
0 2IO K 2IO
I¼I ¼ V2
V1 þ
V1
V2 þ ; (7.112)
2 K 2 K

equivalent with:
pffiffiffiffiffiffiffiffiffiffi
I ¼ I0 ¼ 8KIO ðV2
V1 Þ; (7.113)

The equivalent resistance of the entire active structure can be defined as the ratio
between the V1
V2 differential voltage and the I ¼ I0 current:

V1
V2 V1
V2 1
RECH ¼ ¼ ¼
pffiffiffiffiffiffiffiffiffiffi : (7.114)
I I0 8KIO

The RECH equivalent resistance can be controlled by the IO reference current.

7.3 Conclusions

Chapter presents a multitude of active resistor structures implemented in CMOS

technology. Functionally equivalent with a classical resistor, active resistor circuits
have the most important advantage of reducing the silicon area, especially for large
values of the simulated resistances. Additionally, both positive and negative equiv-
alent resistances are available by small changing of the design. The possibility of
controlling the value of the equivalent resistance using a control current or a control
voltage extends the area of utilization of this class of VLSI circuits.

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Chapter 8
Multifunctional Structures

8.1 Mathematical Analysis for Synthesis of Multifunctional

Structures

An important goal in VLSI designs is represented by the possibility of a multiple

utilization of the same cell, the increased modularity that can be achieved being
reflected in an important reduction of power consumption and of design costs
per circuit function. Many fundamental linear or nonlinear analog blocks can be
realized starting from the same core, the optimization technique implemented
for the nucleus being efficient for all the derived circuits. The presented multi-
functional structures are based on four different elementary mathematical
principles, each of them being illustrated by concrete implementations in CMOS
technology of their functional relations.
The multifunctional structures [2, 3, 5, 9, 35, 46] that can be realized starting
from an improved performances multifunctional core are: differential amplifiers [1,
11, 14, 16–18, 20–31, 34, 59, 64], multiplier circuits [32, 33, 36–45, 47, 48, 50],
active resistors [10, 12, 13, 19, 60–63] (with both positive and negative controllable
equivalent resistance), squaring [4, 38, 49–54], square-rooting [8, 15, 55–58] or
exponential [6, 7] circuits.

8.1.1 First Mathematical Principle (PR 8.1)

The output currents of the multifunctional circuit core (Fig. 8.1) have the following
general expressions:
pffiffiffiffiffiffiffiffi
IOUT1 ¼ IO þ a KIO ðV1  V2 Þ þ bK ðV1  V2 Þ2 (8.1)

and:
pffiffiffiffiffiffiffiffi
IOUT2 ¼ IO  a KIO ðV1  V2 Þ þ bK ðV1  V2 Þ2 ; (8.2)

C.R. Popa, Synthesis of Computational Structures for Analog Signal Processing, 363
DOI 10.1007/978-1-4614-0403-3_8, # Springer Science+Business Media, LLC 2011
364 8 Multifunctional Structures

Fig. 8.1 MFC core based on

PR 8.1 – symbolical
IOUT1 IOUT2
representation

V1 MFC V2

IO

Fig. 8.2 Differential

amplifier based on PR 8.1 –
CM
block diagram IOUT

IOUT1 IOUT2

V1 V2
MFC

IO

a and b being constants, depending on the particular implementation of the

multifunctional circuit core.

8.1.1.1 Principle of Operation of a Linear Differential Amplifier

The block diagram of the differential amplifier using the multifunctional core from
Fig. 8.1 is shown in Fig. 8.2.
The output current of the differential amplifier circuit is obtained as the differ-
ence between the individual output currents, IOUT1 and IOUT2 :
pffiffiffiffiffiffiffiffi
IOUT ¼ IOUT1  IOUT2 ¼ 2a KIO ðV1  V2 Þ: (8.3)

The equivalent transconductance of the structure can be defined as follows:

IOUT pffiffiffiffiffiffiffiffi
Gm ¼ ¼ 2a KIO (8.4)
V 1  V2

and it can be controlled using the IO biasing current.

8.1 Mathematical Analysis for Synthesis of Multifunctional Structures 365

Fig. 8.3 Active resistor with

CM
positive equivalent resistance
based on PR 8.1 – block
diagram
CM

IOUT2 IOUT1 IOUT1

IOUT1 IOUT2 IOUT2

V1 V2
MFC
IOUT1-IOUT2 IOUT1-IOUT2

IO

8.1.1.2 Principle of Operation of an Active Resistor with Positive Equivalent

Resistance

In order to obtain an active resistor with positive equivalent resistance (Fig. 8.3) [1],
the multifunctional core must be modified for generating two IOUT1 output currents
and two IOUT2 output currents.
Additionally, two input–output connections have been added, forcing between
the input pins the same current, IOUT1  IOUT2 . The equivalent resistance of the
entire structure can be defined as the ratio between the differential input voltage,
V1  V2 and the differential current, IOUT1  IOUT2 :

V 1  V2 1 1
RECH ¼ ¼ ¼ pffiffiffiffiffiffiffiffi : (8.5)
IOUT1  IOUT2 Gm 2a KIO

The possibility of controlling the value of the equivalent resistance is fulfilled using
the dependence of the equivalent transconductance, Gm on the biasing current, IO .

8.1.1.3 Principle of Operation of an Active Resistor with Negative Equivalent

Resistance

The replacing of the input–output connections from Fig. 8.3 with two input–output
cross-connections will change the sign of the equivalent resistance for the structure
presented in Fig. 8.4 [1].

V1  V2 1 1
RECH ¼ ¼ ¼  pffiffiffiffiffiffiffiffi : (8.6)
IOUT2  IOUT1 Gm 2a KIO
366 8 Multifunctional Structures

Fig. 8.4 Active resistor with

CM
negative equivalent resistance
based on PR 8.1 – block
diagram
CM

IOUT2 IOUT1 IOUT1

IOUT1 IOUT2 IOUT2

V1 MFC V2
IOUT2-IOUT1 IOUT2-IOUT1

IO

Fig. 8.5 Squaring circuit (1)

based on PR 8.1 – block IOUT
diagram

2IO

IOUT1 IOUT2

V1 V2
MFC

IO

8.1.1.4 Principle of Operation of a Voltage Squaring Circuit

The output current of the squaring circuit presented in Fig. 8.5 [2] can be obtained as a
linear relation, containing the sum of the individual output currents, IOUT1 and IOUT2 :

IOUT ¼ IOUT1 þ IOUT2  2IO ¼ 2bK ðV1  V2 Þ2 : (8.7)

8.1.1.5 Principle of Operation of a Multiplier Circuit (First Method)

For implementing a voltage multiplier circuit, using the multifunctional core

presented in Fig. 8.1, a possible method consists in the replacing of the IO constant
8.1 Mathematical Analysis for Synthesis of Multifunctional Structures 367

Fig. 8.6 Multiplier circuit

(1) based on PR 8.1 – block
CM
diagram IOUT

IOUT1 IOUT2

V1 V2
MFC I

I O’

2IO

I OUT1 ’ IOUT2’

V3 V4
MFC II

IO

biasing current with a current, IO 0 , representing the output current of a squaring

circuit from Fig. 8.5, having as input the differential voltage V3  V4 (Fig. 8.6):

IO 0 ¼ IOUT1 0 þ IOUT2 0  2IO ¼ 2bK ðV3  V4 Þ2 : (8.8)

It results:
pffiffiffiffiffiffiffiffiffi
IOUT ¼ IOUT1  IOUT2 ¼ 2a KIO 0 ðV1  V2 Þ
pffiffiffiffiffi (8.9)
¼ 2aK 2b ðV1  V2 ÞðV3  V4 Þ:

8.1.1.6 Principle of Operation of a Multiplier Circuit (Second Method)

In order to obtain the multiplication function using two squaring circuits from
Fig. 8.5, a possible method is presented in Fig. 8.7 [2] (the consideration of the
difference between the output currents of two squaring circuits, the first circuit
having as input potentials, V1 and  V2 , while the second-one, V1 and V2 ).
368 8 Multifunctional Structures

CM
IOUT

IOUT1 IOUT2 IOUT1’ IOUT2’

V1 MFC I -V2 V1 MFC II V2

IO IO

Fig. 8.7 Multiplier circuit (2) based on PR 8.1 – block diagram

The output current of the multiplier circuit from Fig. 8.7 will have the following
expression:
h i h i
IOUT ¼ 2IO þ 2bK ðV1 þ V2 Þ2  2IO þ 2bK ðV1  V2 Þ2 ¼ 8bKV1 V2 : (8.10)

8.1.1.7 Principle of Operation of a Square-Root Circuit

A possible method for obtaining the square-root function using the squaring circuit
from Fig. 8.5 is presented in Fig. 8.8 [2]. The input potentials, V1 and V2 , are
obtained using four gate-drain connected MOS transistors, biased at I1 and I2 input
currents.
The sum of the output currents of the multifunctional core is:

IOUT1 þ IOUT2 ¼ 2IO þ 2bK ðV1  V2 Þ2 : (8.11)

The V1  V2 differential input voltage can be expressed as a function of the gate-

source voltages as follows:

V1  V2 ¼ 2VGS ðI1 Þ  2VGS ðI2 Þ: (8.12)

Replacing (8.12) in (8.11) and using the square-root dependence of the drain
current on its gate-source voltage for a MOS transistor biased in saturation, it
results:

rffiffiffiffiffiffi rffiffiffiffiffiffi!2
2I1 2I2
IOUT1 þ IOUT2 ¼ 2IO þ 2bK 2 2 ; (8.13)
K K
8.1 Mathematical Analysis for Synthesis of Multifunctional Structures 369

CM IOUT CM

I1 I1 IO 16bI1 16bI2 IO I2 I2
IOUT1 IOUT2

V1 MFC V2

IO

Fig. 8.8 Square-root circuit based on PR 8.1 – block diagram

equivalent with:
pffiffiffiffiffiffiffiffi
IOUT1 þ IOUT2 ¼ 2IO þ 16bI1 þ 16bI2  32b I1 I2 : (8.14)

The output current can be expressed using a linear relation between the currents
from the circuit:

IOUT ¼ 16bI1 þ 16bI2 þ 2IO  ðIOUT1 þ IOUT2 Þ; (8.15)

resulting a square-root dependence of the output current, IOUT , on the input currents,
I1 and I2 :
pffiffiffiffiffiffiffiffi
IOUT ¼ 32b I1 I2 : (8.16)

8.1.1.8 Principle of Operation of a Current Squaring Circuit

The method for obtaining the current squaring function is based on the modifying of
the previous square-root circuit by changing the positions of current mirrors from
Fig. 8.8 (Fig. 8.9) [2].
Similar with the previous circuit, the sum of the output currents, IOUT1 and IOUT2 , is:
pffiffiffiffiffiffiffiffi
IOUT1 þ IOUT2 ¼ 2IO þ 16bI1 þ 16bI2  32b I1 I2 : (8.17)
370 8 Multifunctional Structures

CM CM

I1 I1 16bI1 2IO 8IIN IIN/4b IIN

IOUT
IOUT1 IOUT2
I2

V1 MFC V2

I2/4
IO

Fig. 8.9 Squaring circuit (2) based on PR 8.1 – block diagram

The current mirrors and the connections from Fig. 8.9 implement the following
relation between the currents from the circuit:

IOUT1 þ IOUT2 ¼ 16bI1 þ 2IO þ 8IIN : (8.18)

From the previous relations, it results:

ð2bI2  IIN Þ2 I2 IIN 2

IIN
I1 ¼ ¼  þ : (8.19)
16b2 I2 4 4b 16b2 I2

The expression of the output current of the current squaring circuit will be:

IIN I2 I2
IOUT ¼ I1 þ  ¼ IN2 ; (8.20)
4b 4 16b I2

where IIN is considered to be the input current and I2 represents the reference
current. For simplicity, the I2 current can be considered to be equal with the
reference current, IO , that biases the differential amplifier. Thus:

2
IIN
IOUT ¼ : (8.21)
16b2 IO
8.1 Mathematical Analysis for Synthesis of Multifunctional Structures 371

Fig. 8.10 MFC core based

on PR 8.2 IO IOUT IO

V1 MFC V2

CM

IO
IO IOUT1 IO IO IOUT2 IO

V1 MFC I V2 V2 MFC II V1

Fig. 8.11 Differential amplifier based on PR 8.2 – block diagram

8.1.2 Second Mathematical Principle (PR 8.2)

The output current of the multifunctional circuit core (Fig. 8.10) has the following
expression:

pffiffiffiffiffiffiffiffiffiffi K
IOUT ¼  2KIO ðV1  V2 Þ þ ðV1  V2 Þ2 : (8.22)
2

8.1.2.1 Principle of Operation of a Linear Differential Amplifier

The block diagram of the differential amplifier using the multifunctional core from
Fig. 8.10 is shown in Fig. 8.11 [3].
Using the previous relation for the multifunctional cores from Fig. 8.11, it
results:

pffiffiffiffiffiffiffiffiffiffi K
IOUT1 ¼  2KIO ðV1  V2 Þ þ ðV1  V2 Þ2 ; (8.23)
2
pffiffiffiffiffiffiffiffiffiffi K
IOUT2 ¼ 2KIO ðV1  V2 Þ þ ðV1  V2 Þ2 ; (8.24)
2
372 8 Multifunctional Structures

V3 V4
DA

IO1 IOUT1 IO1 IO2 IOUT2 IO2

V1 MFC I V2 V1 MFC II V2

Fig. 8.12 Multiplier circuit based on PR 8.2 – block diagram

VDD

V3 V4
M5 M5’ M6 M6’
IO1 IO1 IO2 IO2

Fig. 8.13 Implementation of DA block

IO being the reference current. For obtaining the amplifying function with
theoretical null distortions, it is necessary to consider the difference of the previous
output currents:
pffiffiffiffiffiffiffiffiffiffi
IOUT2  IOUT1 ¼ 2 2KIO ðV1  V2 Þ: (8.25)

8.1.2.2 Principle of Operation of a Multiplier Circuit

In order to implement the multiplying function, the first linear dependent on the
differential input voltage term from relation (8.22) is used. The block diagram of
the multiplier circuit, based on the second mathematical principle is presented in
Fig. 8.12 [3].
The method for removing the last quadratic term from (8.22) consists in the
utilization of two identical multifunctional cores from Fig. 8.1, having identical
differential input voltage, but different biasing currents, IO1 and IO2 (MFC 1 and
MFC 2 in Fig. 8.12). As the quadratic term does not depend on IO1 and IO2 currents,
the consideration of the difference between the output currents, IOUT1 and IOUT2 ,
will cancel out this undesired term.
The IO1 and IO2 currents are generated by a classical differential amplifier, DA
(implemented in Fig. 8.13 [3]), having V3  V4 as differential input voltage. In order
8.1 Mathematical Analysis for Synthesis of Multifunctional Structures 373

to obtain a double current of the output of this differential amplifier, its practical
implementation is realized using a parallel connection of two identical classical
differential amplifiers.
The expressions of the output currents are:

pffiffiffiffiffiffiffiffiffiffiffiffi K
IOUT1 ¼  2KIO1 ðV1  V2 Þ þ ðV1  V2 Þ2 ; (8.26)
2
pffiffiffiffiffiffiffiffiffiffiffiffi K
IOUT2 ¼  2KIO2 ðV1  V2 Þ þ ðV1  V2 Þ2 : (8.27)
2

The difference between the output currents, IOUT1 and IOUT2 , will be:
pffiffiffiffiffiffipffiffiffiffiffiffi pffiffiffiffiffiffi
IOUT ¼ IOUT1  IOUT2 ¼ 2K IO2  IO1 ðV1  V2 Þ: (8.28)

For the circuit presented in Fig. 8.13, considering that its composing transistors
are biased in saturation, it can write that:
rffiffiffiffi
pffiffiffiffiffiffi pffiffiffiffiffiffi K
IO2  IO1 ¼ ðV3  V4 Þ: (8.29)
2

Replacing (8.29) in (8.28), it results that the circuit proposed in Fig. 8.12
implements the multiplying function:

IOUT ¼ K ðV1  V2 ÞðV3  V4 Þ: (8.30)

8.1.2.3 Principle of Operation of a Squaring Circuit

The proposed method for implementing the squaring function is derived from the
realization of the differential amplifier circuit with increased linearity, presented in
Fig. 8.11. In order to obtain an output current proportional with the square of the
differential input voltage, the second term from (8.22) must be used. Practically,
the sum of IOUT1 and IOUT2 output currents from Fig. 8.11 will contain only the
quadratic term:

IOUT1 þ IOUT2 ¼ K ðV1  V2 Þ2 : (8.31)

374 8 Multifunctional Structures

8.1.3 Third Mathematical Principle (PR 8.3)

The third mathematical principle can be written as follows:

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
 
V1  V 2 K pffiffiffiffiffiffiffiffi
IOUT ¼ 4K IO þ ðV1  V2 Þ  K 2 ðV1  V2 Þ2 ¼ KIO ðV1  V2 Þ:
2
2 4
(8.32)

8.1.4 Fourth Mathematical Principle (PR 8.4)

8.1.4.1 Superior-Order Approximation of a Continuous Mathematical

Function

A possible method for obtaining any continuous function using current squaring
circuits consists in the consideration of the superior-order approximation of this
function using the limited Taylor series expansion. The input variable is represented
by the ratio between the input current and the reference current, x ¼ IIN =IO .
A f ðxÞ continuous function can be expand in Taylor series as follows:

X
1 
1 
f ðxÞ ¼ f ðxÞjx¼0 þ f ðkÞ ðxÞ  xk ; (8.33)
k¼1
k! 
x¼0

f ðkÞ ðxÞ being the kth order derivate of f ðxÞ function. The previous relation is
equivalent with a polynomial expression of f ðxÞ function with constant coefficients ak :

X
1
f ðxÞ ¼ aO þ ak xk ; (8.34)
k¼1

where:

aO ¼ f ðxÞjx¼0 (8.35)

and:

f ðkÞ ðxÞ
ak ¼ : (8.36)
k! x¼0
8.1 Mathematical Analysis for Synthesis of Multifunctional Structures 375

Any continuous function can be approximated using a nth order limited Taylor
expansion, the approximation error being proportional with the number of the
neglected terms:

X
n
f ðxÞ ffi aO þ ak x k : (8.37)
k¼1

Because x variable is non-dimensional, the current-mode evaluation of f ðxÞ

function can be made by generating a current IOUT ðxÞ ¼ IO f ðxÞ:

X
n  k
IIN
IOUT ðxÞ ffi aO IO þ IO ak : (8.38)
k¼1
IO

The block diagram of a function generator circuit is presented in Fig. 8.14 [4–7],
consisting in n  1 identical current squaring circuits for a n - th order polynomial
series expansion of f ðxÞ function and in a block that computes ak coefficients for
k ¼ 0; 1; :::; n. The advantage of this implementation is that a very good precision
of the circuit can be achieved by increasing the value of n.
The implemented currents using the previous circuits are:

IOUTð0Þ ¼ IIN ; (8.39)

2
IIN
IOUTð1Þ ¼ ; (8.40)
IO

2
IOUTð1Þ 3
IIN
IOUTð2Þ ¼ ¼ ; (8.41)
IIN IO2

2
IOUTðn1Þ nþ1
IIN
IOUTðnÞ ¼ ¼ : (8.42)
IOUTðn2Þ IOn

The “ak ” block is implemented using simple and multiple current mirrors and
must be able to compute the ak coefficients from (8.35) and (8.36). The output
current of this block, IOUT ðxÞ, will be proportional with the superior-order
approximated function, f ðxÞ. In order to increase the circuit accuracy, the number
of squaring blocks from Fig. 8.14 can be increased. So, a compromise between the
circuit complexity and its precision must be made. The circuit accuracy is also
increased because of the independence of the output current on technological
parameters.
376 8 Multifunctional Structures

IO IOUT (0) = IIN

IO
a0
IO IIN IOUT (0)
a1
IOUT IOUT IOUT
IOUT (1)
a2
IOUT (1)
IIN IOUT (1)
IO IIN
IOUT IOUT IOUT
IOUT (2)
a3
IOUT (2) IOUT (2)
ak
IO IIN
block IOUT(x)
IOUT IOUT IOUT
IOUT (3)
a4
IOUT (3)
IOUT (3)
IO IIN
IOUT IOUT IOUT
IOUT (4) IOUT (4)
a5
IOUT (4)

IOUT (n-3) IOUT (n-2) Digital

IO IIN selection
IOUT IOUT IOUT
IOUT (n-1)
an

Fig. 8.14 Function generator circuit based on PR 8.2 – block diagram

8.1.4.2 Second-Order Approximation of a Continuous Mathematical

Function

Another possible implementation of the same mathematical principle is also based

on the approximation of any continuous mathematical function by its superior-order
limited Taylor series expansion:

f ðxÞ ¼ aO þ a1 x þ a2 x2 þ a3 x3 þ    ; (8.43)
8.1 Mathematical Analysis for Synthesis of Multifunctional Structures 377

Table 8.1 Coefficients of Function aO a1 a2

usual functions for second-
order Taylor approximation exp(x) 1 1 1/2
cos (x) 1 0 1/2
cosh (x) 1 0 1/2
(1  x)1 1 1 1
(1 + x)1/2 1 1/2 1/8
(1  x)1/2 1 1/2 1/8
(1 + x)1/3 1 1/3 1/9
(1  x)1/3 1 1/3 1/9
(1 + x)1/4 1 1/4 3/32
(1x)1/4 1 1/4 3/32
(1 + x)2 1 2 3
(1x)2 1 2 3
ln (1  x) 0 1 1/2
ln (1 + x) 0 1 1/2
(1 + x)2 1 2 1
(1  x)2 1 2 1

where x ¼ IIN =IO (the ratio of the input current and the reference current).
For some usual continuous mathematical functions, the values of a0 , a1 and a2
coefficients used for a second-order approximation are centralized in Table 8.1.

8.1.4.3 Third-Order Approximation of a Continuous Mathematical Function

A gðxÞ function that can approximate many f ðxÞ continuous mathematical functions
could have the following expression:

a1 x
gðxÞ ¼ þ a3 x þ a4 ; (8.44)
1 þ a2 x

the ak constants having the following expressions: a1 ¼ p2 =q, a2 ¼ q=p,

a3 ¼ n  p2 =q, a4 ¼ m. In order to evaluate the capability of gðxÞ function to
approximate a f ðxÞ continuous function, the Taylor series expansion for gðxÞ
must be determined:

a1
g0 ðxÞ ¼ þ a3 ; (8.45)
ð1 þ a2 xÞ2

2a1 a2
g00 ðxÞ ¼ ; (8.46)
ð1 þ a2 xÞ3

6a1 a22
g000 ðxÞ ¼ ; (8.47)
ð1 þ a2 xÞ4
378 8 Multifunctional Structures

24a1 a32
g0000 ðxÞ ¼ ; (8.48)
ð1 þ a2 xÞ5

resulting:

q2 4
gðxÞ ¼ m þ nx þ px2 þ qx3 þ x þ   : (8.49)
p

So, the gðxÞ function third-order approximates a continuous f ðxÞ function,

having the Taylor series expansion expressed by:

f ðxÞ ¼ m þ nx þ px2 þ qx3 þ rx4 þ   : (8.50)

The approximation error is mainly caused by the fourth-order terms from the
previous expansions:

gðxÞ r þ a1 a32 x4
ef ðxÞ ðxÞ ffi : (8.51)
f ðxÞ

The expressions of gðxÞ functions and of the approximation errors for 13 usual
mathematical functions are presented in Appendix 2.

8.1.4.4 Third-Order Approximation of a Continuous Mathematical Function

Using Two Primitive Functions

A method for obtaining a multitude of continuous mathematical functions using

their third-order Taylor series expansion is to use two primitive functions and to
express the approximation of each required mathematical function as a linear
combination of these primitives. The continuous function that will be implemented
is noted with f ðxÞ, its third-order approximation – with gðxÞ, while the primitive
functions are noted with f1 ðxÞ and f2 ðxÞ. The approximation function gðxÞ can be
expressed as follows:

gðxÞ ¼ af1 ðxÞ þ bf2 ðxÞ þ cx þ d; (8.52)

a, b, c and d being constant coefficients associated with each implemented

function f ðxÞ. The following analysis will be made for a particular choosing of
these primitive functions that generate relatively simple mathematical relations and
reasonable values of the coefficients:

1
f1 ðxÞ ¼ (8.53)
1x
8.1 Mathematical Analysis for Synthesis of Multifunctional Structures 379

and:

1
f2 ðxÞ ¼ : (8.54)
2x

The Taylor series expansions of f1 ðxÞ and f2 ðxÞ are:

f1 ðxÞ ¼ 1 þ x þ x2 þ x3 þ x4 þ    (8.55)

and:

1 x x2 x3 x4
f2 ðxÞ ¼ þ 2 þ 3 þ 4 þ 5 þ   : (8.56)
2 2 2 2 2

So, the function gðxÞ can be expressed as follows:

  
b b b
gðxÞ ¼ a þ þ d þ a þ þ c x þ a þ x2
2 4 8
 
b 3 b 4
þ aþ x þ aþ x þ   : (8.57)
16 32

Considering that the Taylor expansion of f ðxÞ function is:

f ðxÞ ¼ m þ nx þ px2 þ qx3 þ rx4 þ   ; (8.58)

m, n, p, q and r being constant coefficients of the expansion (known, because

f ðxÞ function is also known), the condition that gðxÞ function must represent the
third-order approximation of f ðxÞ function can be written as follows:

b
m ¼ a þ þ d; (8.59)
2
b
n ¼ a þ þ c; (8.60)
4
b
p¼aþ (8.61)
8

and:

b
q¼aþ ; (8.62)
16

resulting:

a ¼ 2q  p; (8.63)
380 8 Multifunctional Structures

b ¼ 16ðp  qÞ; (8.64)

c ¼ n þ 2q  3p (8.65)

and:

d ¼ m þ 6q  7p: (8.66)

So, gðxÞ function that third-order approximates f ðxÞ will have the following
expression:

1 1
gðxÞ ¼ ð2q  pÞ þ 16ðp  qÞ
1x 2x (8.67)
þ ðn þ 2q  3pÞx þ ðm þ 6q  7pÞ:

The approximation error is mainly caused by the fourth-order terms from the
previous expansions, (8.57) and (8.58):

gðxÞ a þ 32b
 r 4 3q  p  r 4
ef ðxÞ ðxÞ ffi x ¼ x: (8.68)
f ðxÞ 2f ðxÞ

Table 8.2 centralizes the values of constants m, n, p, q and r and also the
expressions of the approximation errors (8.68) and of the approximation function
gðxÞ for the previous 11 usual continuous mathematical functions:

8.1.4.5 Fifth-Order Approximation of a Continuous Mathematical Function

Using Four Primitive Functions

A similar method for obtaining a multitude of continuous mathematical functions

using their fifth-order Taylor series expansion is to use four primitive functions and
to express the approximation of each required mathematical function as a linear
combination of these primitives. The continuous function that will be implemented
is noted with f ðxÞ, its fifth-order approximation – with gðxÞ, while the primitive
functions are noted with f1 ðxÞ, f2 ðxÞ, f3 ðxÞ and f4 ðxÞ. The approximation function
gðxÞ can be expressed as follows:

gðxÞ ¼ a1 f1 ðxÞ þ a2 f2 ðxÞ þ a3 f3 ðxÞ þ a4 f4 ðxÞ þ a5 x þ a6 ; (8.69)

a1 , a2 , a3 , a4 , a5 and a6 being constant coefficients associated with each

implemented function f ðxÞ. The following analysis will be made for a particular
choosing of these primitive functions that generate relatively simple mathematical
relations and reasonable values of the coefficients:

1
f1 ðxÞ ¼ ; (8.70)
1x
Table 8.2 Coefficients, eðxÞ and gðxÞ of eleven usual functions for third-order Taylor approximation using two primitive functions
f(x) m n p q r e g(x)
expðxÞ 1 1 1 1 1 4 1 1 16 1
x
 þ
2 6 24 48 expðxÞ 6 1  x 3 2x
x 3
 
pffiffiffiffiffiffiffiffiffiffiffi 6 2
1 1 1 1 5 4 1 1 3
1þx 45x
  pffiffiffiffiffiffiffiffiffiffiffi 
2 8 16 128 256 1 þ x 41 x 2  x
5
þxþ
pffiffiffiffiffiffiffiffiffiffiffi 2
1x 1 1 1 1 5 3x4 1 x 3
    pffiffiffiffiffiffiffiffiffiffiffi   þ
2 8 16 128 256 1  x 2x 4 2
p3
ffiffiffiffiffiffiffiffiffiffiffi
1þx 1 1 1 5 10 41x4 19 1 224 1
  p ffiffiffiffiffiffiffiffiffiffiffi 
3 9 81 243 3 81 1  x 81 2  x
243 1 þ x
64x 58
þ þ
p ffiffiffiffiffiffiffiffiffiffiffi 81 27
3 1 1 5 10 4 1 1 64 1
1x 1 4x
    pffiffiffiffiffiffiffiffiffiffiffi  
3 9 81 243 243 3 1  x 81 1  x 81 2  x
10x 38
 þ
p ffiffiffiffiffiffiffiffiffiffiffi 81 27
4 1 3 7 77 4 13 1 19 1
1þx 1 605x
  pffiffiffiffiffiffiffiffiffiffiffi 
4 32 128 2048 4096 4 1 þ x 64 1  x 8 2  x
41x 127
þ þ
8.1 Mathematical Analysis for Synthesis of Multifunctional Structures

p ffiffiffiffiffiffiffiffiffiffiffi 64 64
4 1 3 7 77 1 1 5 1
1x 1 67x4
    pffiffiffiffiffiffiffiffiffiffiffi  
4 32 128 2048 4096 4 1  x 64 1  x 8 2  x
5x 85
 þ
64 64
1 1 2 3 4 5 10x4 ð1 þ xÞ2 11 112
 þ
ð1 þ xÞ2 1x 2x
 19x  44
381

(continued)
Table 8.2 (continued)
382

f(x) m n p q r e g(x)
1 1 2 3 4 5 4 2 5 16
2x ð1  xÞ  þxþ4
ð1  xÞ2 1x 2x
lnð1 þ xÞ 0 1 1 1 1 7x4 7 1 40 1
  
2 3 4 8 lnð1 þ xÞ 61 x 3 2 x
19x 11
þ þ
6 2
lnð1  xÞ 0 1 1 1 1 x4 1 1 8 1
    
2 3 4 8 lnð1  xÞ 61  x 32  x
x 3
 þ
6 2
8 Multifunctional Structures
8.1 Mathematical Analysis for Synthesis of Multifunctional Structures 383

1
f2 ðxÞ ¼ ; (8.71)
1þx

1
f3 ðxÞ ¼ ; (8.72)
2x

1
f4 ðxÞ ¼ ; (8.73)
2þx

The Taylor series expansions of f1 ðxÞ, f2 ðxÞ, f3 ðxÞ and f4 ðxÞ are:

f1 ðxÞ ¼ 1 þ x þ x2 þ x3 þ x4 þ x5 þ x6 þ   ; (8.74)

f2 ðxÞ ¼ 1  x þ x2  x3 þ x4  x5 þ x6    ; (8.75)

1 x x2 x3 x4 x5 x6
f3 ðxÞ ¼ þ 2 þ 3 þ 4 þ 5 þ 6 þ 7 þ   ; (8.76)
2 2 2 2 2 2 2

1 x x2 x3 x4 x5 x6
f4 ðxÞ ¼  2 þ 3  4 þ 5  6 þ 7 þ   ; (8.77)
2 2 2 2 2 2 2

So, gðxÞ function can be expressed as follows:

 a3 þ a4   a3  a4 
gðxÞ ¼ a1 þ a2 þ þ a6 þ a1  a2 þ þ a5 x
2 4
 a3 þ a4  2  a3  a4  3
þ a1 þ a2 þ x þ a1  a2 þ x
8 16
 a3 þ a4  4  a3  a4  5
þ a1 þ a2 þ x þ a1  a2 þ x
32 64
 
a3 þ a4 6
þ a1 þ a2 þ x þ   : (8.78)
128

Considering that the Taylor expansion of f ðxÞ function is:

f ðxÞ ¼ bO þ b1 x þ b2 x2 þ b3 x3 þ b4 x4 þ b5 x5 þ b6 x6 þ   ; (8.79)

b0  b6 being constant coefficients of the expansion (known, because f ðxÞ

function is also known), the condition that gðxÞ function must represent the fifth-
order approximation of f ðxÞ function can be written as follows:

a3 þ a 4
b0 ¼ a1 þ a2 þ þ a6 ; (8.80)
2
384 8 Multifunctional Structures

a3  a 4
b1 ¼ a1  a2 þ þ a5 ; (8.81)
4

a3 þ a4
b2 ¼ a1 þ a2 þ ; (8.82)
8

a3  a4
b3 ¼ a1  a2 þ ; (8.83)
16

a3 þ a 4
b4 ¼ a1 þ a2 þ (8.84)
32

and:

a3  a4
b5 ¼ a1  a2 þ ; (8.85)
64

resulting:

2 1
a1 ¼ ðb4 þ b5 Þ  ðb2 þ b3 Þ; (8.86)
3 6

1 2
a2 ¼ ðb3  b2 Þ  ðb5  b4 Þ; (8.87)
6 3

16 32
a3 ¼ ðb2  b4 Þ þ ðb3  b5 Þ; (8.88)
3 3

16 32
a4 ¼ ðb2  b4 Þ  ðb3  b5 Þ; (8.89)
3 3

a5 ¼ b1 þ 4b5  5b3 (8.90)

and:

a6 ¼ b0 þ 4b4  5b2 : (8.91)

So, gðxÞ function that fifth-order approximates f ðxÞ will have the following
expression:

a1 a2 a3 a4
gðxÞ ¼ þ þ þ þ a5 x þ a6 : (8.92)
1x 1þx 2x 2þx
8.2 Analysis and Design of Multifunctional Structures 385

8.2 Analysis and Design of Multifunctional Structures

8.2.1 Multifunctional Structures Based on the First Mathematical

Principle

8.2.1.1 First Implementation of PR 8.1

The first implementation of PR 8.1 is based on the multifunctional core presented in

Fig. 8.15 [2]. This circuit uses the principle of the constant sum of gate-source
voltages in order to obtain the required function. It presents the advantage of a
symmetrical structure that strongly reduce the intrinsic nonlinearity of the entire
circuit.
The output currents of the multifunctional core presented in Fig. 8.15 have the
following expressions:

K K
IOUT1 ¼ ðVO  VT Þ2 þ K ðVO  VT Þ ðV1  V2 Þ þ ðV1  V2 Þ2 (8.93)
2 2

and:

K K
IOUT2 ¼ ðVO  VT Þ2  K ðVO  VT ÞðV1  V2 Þ þ ðV1  V2 Þ2 : (8.94)
2 2

The VO sources are usually implemented as current-controlled voltage sources.

An example of a possible realization of VO uses the gate-source voltages of MOS
transistors biased in saturation region (VGS3 and VGS5 from Fig. 8.16) [8, 9].
Comparing with other circuits, the structure presented in Fig. 8.16 has an extremely
high input impedance.

IOUT1 IOUT2

M1 M2
V1 IO IO V2

VO VO IOUT2
IOUT1 - + + -

IO IO
IO IO

Fig. 8.15 First implementation of the MFC core based on PR 8.1 – principle circuit
386 8 Multifunctional Structures

VDD

IO

IOUT1 IOUT2

V1 M1 M3 M5 M2 V2

VO VO
IO + IOUT1 IO + IOUT2
M4 M6

Fig. 8.16 MFC core based on PR 8.1 – complete implementation (1)

For this particular implementation of VO sources, the expressions of IOUT1 and

IOUT2 currents become:
pffiffiffiffiffiffiffiffiffiffi K
IOUT1 ¼ IO þ 2KIO ðV1  V2 Þ þ ðV1  V2 Þ2 (8.95)
2
and:
pffiffiffiffiffiffiffiffiffiffi K
IOUT2 ¼ IO  2KIO ðV1  V2 Þ þ ðV1  V2 Þ2 : (8.96)
2
Comparing these relations with the general relations (8.1) and (8.2), for the
implementation of the multifunctional core presented in Fig. 8.16, the a and b
constants will have the following values:
pffiffiffi
a¼ 2 (8.97)

and:

1
b¼ : (8.98)
2
The particular implementation of the multifunctional core presented in Fig. 8.16
can be used as linear differential amplifier, the differential output current of the
circuit being expressed as follows:

IOUT ¼ IOUT1  IOUT2 : (8.99)

8.2 Analysis and Design of Multifunctional Structures 387

VDD

IO
IO IO

IOUT1 IOUT2
IOUT1-IOUT2 IOUT1-IOUT2
V1 V2

Fig. 8.17 Active resistor with positive equivalent resistance based on PR 8.1 – complete imple-
mentation (1)

So:
pffiffiffiffiffiffiffiffiffiffi
IOUT ¼ 8KIO ðV1  V2 Þ: (8.100)

resulting an equivalent transconductance of the circuit having the following

expression:

IOUT pffiffiffiffiffiffiffiffiffiffi
Gm ¼ ¼ 8KIO : (8.101)
V1  V2

In order to obtain two active resistors having positive and negative equivalent
resistances, the concrete implementation of the multifunctional core shown in
Fig. 8.16 must be used in the blocks diagrams presented in Figs. 8.3 and 8.4, the
complete realizations of the active resistor circuits being shown in Figs. 8.17 and
8.18. As a result on their excellent linearity and of their relative small complexity,
the following structures find a multitude of applications in analog signal processing.
The equivalent resistances of the circuits presented in Figs. 8.17 and 8.18 are
expressed by the following relations, respectively:

V1  V2 1
RECH ¼ ¼ pffiffiffiffiffiffiffiffiffiffi (8.102)
IOUT1  IOUT2 8KIO

and:

V1  V2 1
RECH ¼ ¼  pffiffiffiffiffiffiffiffiffiffi : (8.103)
IOUT2  IOUT1 8KIO
388 8 Multifunctional Structures

VDD

IO IO IO

IOUT1 IOUT2
IOUT2-IOUT1 IOUT2-IOUT1
V1 V2

Fig. 8.18 Active resistor with negative equivalent resistance based on PR 8.1 – complete
implementation (1)

VDD

2IO IO
IOUT

IOUT1 IOUT2
V1 V2

Fig. 8.19 Squaring circuit (1) based on PR 8.1 – complete implementation (1)

A squaring circuit can be obtained replacing in the block diagram presented in

Fig. 8.5 the particular realization of the multifunctional core shown in Fig. 8.16, the
implementation of the squaring circuit being presented in Fig. 8.19 [8, 9]. The
design effort for this circuit is relatively small, as the only changing with respect to
the MFC core from Fig. 8.16 is the consideration of the sum of its output currents.
8.2 Analysis and Design of Multifunctional Structures 389

VDD

IO’
IO’ IO’ IOUT

IOUT1 IOUT2
V1 V2

VDD

2IO IO IO
IO
IOUT1’ IOUT2’
V3 V4

Fig. 8.20 Multiplier circuit (1) based on PR 8.1 – complete implementation (1)

The output current of the circuit from Fig. 8.19 is proportional with the square of
the differential input voltage:

IOUT ¼ IOUT1 þ IOUT2  2IO ¼ K ðV1  V2 Þ2 : (8.104)

A multiplier circuit based on the block diagram presented in Fig. 8.6 can be
obtained using the particular implementation of the multifunctional core shown in
Fig. 8.16, the complete multiplier circuit being presented in Fig. 8.20. The structure
can be used for applications that require differential input voltages.
The output current of the circuit from Fig. 8.20 is proportional with the product
between the differential input voltages:
pffiffiffi
IOUT ¼ 2 2 K ðV1  V2 ÞðV3  V4 Þ: (8.105)
390 8 Multifunctional Structures

VDD

IOUT
IO
IOUT1 IOUT2 IOUT1’ IOUT2’
V1 -V2V1 V2

Fig. 8.21 Multiplier circuit (2) based on PR 8.1 – complete implementation (1)

VDD

IO IO 2IO IO
8I2
I1 8I1 IOUT I2
I1 I2
IOUT1 IOUT2

V1 V2

-VDD

Fig. 8.22 Square-root circuit based on PR 8.1 – complete implementation (1)

The principle illustrated by the block diagram presented in Fig. 8.7 can be
implemented replacing the multifunctional cores with the same circuit described
in Fig. 8.16, this alternative realization of the multiplier circuit being presented in
Fig. 8.21 [2].
The output current of the alternative realization of the multiplier circuit
presented in Fig. 8.21 is proportional with the product between the input voltages,
IOUT ¼ 4 KV1 V2 .
A current-mode square-root circuit, having many applications in analog signal
processing, can be obtained combining the block diagram from Fig. 8.8 with the
multifunctional core from Fig. 8.16 (Fig. 8.22) [2].
The expression of the output current is:
pffiffiffiffiffiffiffiffi
IOUT ¼ 16 I1 I2 : (8.106)

The current squaring circuit based on the block diagram shown in Fig. 8.9 and on
the multifunctional core from Fig. 8.16 is shown in Fig. 8.23 [2]. This circuit is
useful for a current-mode signal processing, presenting relatively small errors as a
result of the independence of the output variable on technological parameters.
8.2 Analysis and Design of Multifunctional Structures 391

VDD

2IO 8IIN
I1 8I1 IO IO IIN/2 IIN

IOUT
I1
IOUT1 IOUT2
I2
V1 V2

I2/4

-VDD

Fig. 8.23 Squaring circuit (2) based on PR 8.1 – complete implementation (1)

VDD

IO IO

IOUT1 IOUT2

M1 M2

V1 M3
M4
V2

Fig. 8.24 MFC core based on PR 8.1 – complete implementation (2)

The expression of the output current is:

2
IIN
IOUT ¼ : (8.107)
4IO

An alternative realization of VO voltage sources from Fig. 8.15, presenting the

advantage of simplicity, uses gate-source voltages of MOS transistors biased in
392 8 Multifunctional Structures

saturation region (VGS3 and VGS4 from Fig. 8.24 [8]). For this particular implemen-
tation of VO sources, the expressions of IOUT1 and IOUT2 currents become:
pffiffiffiffiffiffiffiffiffiffi K
IOUT1 ¼ IO þ 2KIO ðV1  V2 Þ þ ðV1  V2 Þ2 (8.108)
2
and:
pffiffiffiffiffiffiffiffiffiffi K
IOUT2 ¼ IO  2KIO ðV1  V2 Þ þ ðV1  V2 Þ2 : (8.109)
2
Comparing these relations with the general relations (8.1) and (8.2), it results
that for the implementation of the multifunctional core presented in Fig. 8.24, the a
and b constants have the following values:
pffiffiffi
a¼ 2 (8.110)

and:

1
b¼ : (8.111)
2
The particular implementation of the multifunctional core presented in Fig. 8.24
can be used as linear differential amplifier, the differential output current of the
circuit being expressed as follows:
pffiffiffiffiffiffiffiffiffiffi
IOUT1  IOUT2 ¼ 8KIO ðV1  V2 Þ; (8.112)

resulting an equivalent transconductance of the circuit, having the following

expression:

IOUT pffiffiffiffiffiffiffiffiffiffi
Gm ¼ ¼ 8KIO : (8.113)
V1  V2

In order to obtain two active resistors having positive or negative equivalent

resistances, the concrete implementation of the multifunctional core shown in
Fig. 8.24 must be used in the blocks diagrams presented in Figs. 8.3 and 8.4, the
complete realizations of the active resistor circuits being shown in Figs. 8.25 and 8.26.
The replacing of classical input–output connections (Fig. 8.25) with two input–output
cross-connections (Fig. 8.26) offers the possibility of obtaining a negative resistance
active resistor circuit, finding a multitude of applications in VLSI designs.
The equivalent resistances of the circuits presented in Figs. 8.25 and 8.26 are
expressed by the following relations, respectively:

V1  V2 1
RECH ¼ ¼ pffiffiffiffiffiffiffiffiffiffi (8.114)
IOUT1  IOUT2 8KIO
8.2 Analysis and Design of Multifunctional Structures 393

VDD

IO IO

IOUT1 IOUT2 IOUT1

IOUT2
IOUT1IOUT2

IOUT1 - IOUT2 IOUT 1- IOUT2

V1
IOUT1 - IOUT2 V2
IOUT1 - IOUT2

Fig. 8.25 Active resistor with positive equivalent resistance based on PR 8.1 – complete imple-
mentation (2)

VDD

IO IO

IOUT1 IOUT2 IOUT1

IOUT2

IOUT1IOUT2

IOUT2 - IOUT1 IOUT2 - IOUT1

V1
V2
IOUT2 - IOUT1
IOUT2 - IOUT1

Fig. 8.26 Active resistor with negative equivalent resistance based on PR 8.1 – complete
implementation (2)

and:

V1  V2 1
RECH ¼ ¼  pffiffiffiffiffiffiffiffiffiffi : (8.115)
IOUT2  IOUT1 8KIO

A squaring circuit can be obtained replacing in the block diagram presented in

Fig. 8.5 the particular realization of the multifunctional core shown in Fig. 8.24, the
realization of the squaring circuit being presented in Fig. 8.27 [8, 9].
394 8 Multifunctional Structures

VDD

IO 2IO IOUT IO IO

IOUT1 IOUT2

V1 V2

Fig. 8.27 Squaring circuit (1) based on PR 8.1 – complete implementation (2)

The output current of the circuit from Fig. 8.27 is proportional with the squaring
of the differential input voltage:

IOUT ¼ IOUT1 þ IOUT2  2IO ¼ K ðV1  V2 Þ2 : (8.116)

A multiplier circuit based on the block diagram presented in Fig. 8.6 can be
obtained using the particular implementation of the multifunctional core shown in
Fig. 8.24, the complete multiplier circuit being presented in Fig. 8.28.
The output current of the circuit from Fig. 8.28 is proportional with the product
between the differential input voltages:
pffiffiffi
IOUT ¼ 2 2K ðV1  V2 ÞðV3  V4 Þ: (8.117)

The principle illustrated by the block diagram presented in Fig. 8.7 can be
implemented replacing the multifunctional cores with the same circuit described
in Fig. 8.24, this alternative realization of the multiplier circuit being presented in
Fig. 8.29 [2].
The output current of the alternative realization of the multiplier circuit
presented in Fig. 8.29 is proportional with the product between the input voltages:

IOUT ¼ 4KV1 V2 : (8.118)

The square-root circuit obtained combining the block diagram from Fig. 8.8 and
the multifunctional core from Fig. 8.24 is shown in Fig. 8.30 [2].
8.2 Analysis and Design of Multifunctional Structures 395

VDD

IO ’ IOUT IO ’
IO ’
IOUT1 IOUT2

V1 V2

VDD

IO ’
IO 2IO IO
IO

IOUT1’ IOUT2’

V3 V4

Fig. 8.28 Multiplier circuit (1) based on PR 8.1 – complete implementation (2)

The expression of the output current is:

pffiffiffiffiffiffiffiffi
IOUT ¼ 16 I1 I2 : (8.119)

The current squaring circuit based on the block diagram shown in Fig. 8.9 and on
the multifunctional core from Fig. 8.24 is shown in Fig. 8.31 [2].
396 8 Multifunctional Structures

VDD

IO
IOUT

-V2 V1
V1 V2

Fig. 8.29 Multiplier circuit (2) based on PR 8.1 – complete implementation (2)

VDD

IO IO
IO 2IO
8I1 8I2 IOUT
I1 I1 I2 I2
IOUT1 IOUT2

V1 V2

-VDD

Fig. 8.30 Square-root circuit based on PR 8.1 – complete implementation (2)

VDD

IO
IO 2IO 8IIN IO
I1 8I1 IIN/2
IIN
IOUT I1
IOUT1 IOUT2

I2 I2/4
V1 V2

-VDD

Fig. 8.31 Squaring circuit (2) based on PR 8.1 – complete implementation (2)
8.2 Analysis and Design of Multifunctional Structures 397

VDD

IOUT1 IO IO IOUT2

M1 M3 M4 M2
V1 V2
VO VO

IO IO

Fig. 8.32 MFC core based on PR 8.1 – complete implementation (3)

VDD

M5 M6 M7 M15 M16 M17

IOUT1 IOUT1 IOUT2 IOUT2

M1 M2 M3 M4 M13 M14
V1 V2
IO IO
A VO VO B
I’
IOUT1 2IOUT1 2IOUT1 I
2IOUT2 2IOUT2 IOUT2
IO IO
M10 M9 M8 M12 M11 M18

Fig. 8.33 MFC core based on PR 8.1 – complete implementation (4)

The expression of the output current is:

2
IIN
IOUT ¼ : (8.120)
4IO

Two other alternative implementations of the multifunctional core based on the

same principle are presented in Fig. 8.32 [2] and Fig. 8.33 [10].
398 8 Multifunctional Structures

V1 M V2

IO IO
T T
V
V1T V2T
DA

IOUT1 IOUT2

Fig. 8.34 Second implementation of the MFC core based on PR 8.1 – block diagram

Fig. 8.35 MFC core based V

on PR 8.1 – DA block
implementation

V1T V2T

IOUT1 IOUT2

8.2.1.2 Second Implementation of PR 8.1

Another possible implementation of PR 8.1 is based on the multifunctional core

presented in Fig. 8.34 [11]. The “DA” block represents a classical differential
amplifier, having the common-sources point biased at a V potential fixed by the
circuit “M”. This circuit computes the arithmetical mean of input potentials,
implementing a very good linearity of the entire structure, with the contribution
of “T” blocks (which are used for introducing a DC shifting of input potentials).
The “DA” block has the concrete realization presented in Fig. 8.35.
The DC shifting of the V potential could be obtained using “T” blocks, with an
implementation proposed in Fig. 8.36 [12, 13].
Because the same current IO is passing through all transistors from Fig. 8.36, it
can write that:

rffiffiffiffiffiffiffi
2IO
V1 ¼ V1T þ VT þ (8.121)
K
8.2 Analysis and Design of Multifunctional Structures 399

Fig. 8.36 MFC core based

on PR 8.1 – T block
implementation IO IO

V1 V2

V1T V2T

IO/2 IO/2

V1 V2

IO IO
V

Fig. 8.37 MFC core based on PR 8.1 – M block implementation

and:
rffiffiffiffiffiffiffi
2IO
V2 ¼ V2T þ VT þ : (8.122)
K
So, both V1 and V2 input potentials are shifted with the same amount,
pffiffiffiffiffiffiffiffiffiffiffiffiffi
VT þ 2IO =K .
In order to obtain the arithmetic mean of input potentials, the circuit from
Fig. 8.37 [12, 13] can be used.
V1 þ V2
V¼ : (8.123)
2
The complete implementation of the multifunctional circuit is presented in
Fig. 8.38 [11].
The expressions of IOUT1 and IOUT2 currents are:
" rffiffiffiffiffiffiffi! #2
K 2 K 2IO
IOUT1 ¼ ðV  V1T  VT Þ ¼ V  V1  VT   VT
2 2 K
rffiffiffiffiffiffiffi!2 rffiffiffiffiffiffiffi!2
K V1 þ V2 2IO K V1  V2 2IO
¼  V1 þ ¼  þ
2 2 K 2 2 K
rffiffiffiffiffiffiffiffi
KIO K
¼ IO  ðV1  V2 Þ þ ðV1  V2 Þ2 (8.124)
2 8
400 8 Multifunctional Structures

VDD

M11 M12 M12’ M11’

M10 M13 M13’ M10’

IO/2 “M” IO/2
“T” “T”M9’
M9 M14 M15 M15’ M14’
V1 V2
0
2IOUT1 IO 2IOUT2
IO
V
IOUT1 IOUT2
V1T V2T
M1 M2
IO M5 M5’ IO
IO IOUT1 IOUT2
M4 M3 M3’ M4’
M6’
M16 M6 M8 “DA” M8’

Fig. 8.38 MFC core based on PR 8.1 – complete implementation

and:
rffiffiffiffiffiffiffiffi
KIO K
IOUT2 ¼ IO þ ðV1  V2 Þ þ ðV1  V2 Þ2 : (8.125)
2 8

Comparing the previous relations with (8.1) and (8.2), it results:

1
a ¼  pffiffiffi (8.126)
2

and:

1
b¼ : (8.127)
8
The implementation of a linear differential amplifier using the multifunctional
core shown in Fig. 8.34 is identical with the structure presented in Fig. 8.38, the
equivalent transconductance of the differential structure being defined as follows:

IOUT1  IOUT2 pffiffiffiffiffiffiffiffiffiffi

Gm ¼ ¼  2KIO : (8.128)
V1  V2

In order to obtain two active resistors having positive and negative equivalent
resistances, the concrete implementation of the multifunctional core shown in
Fig. 8.38 must be used in the blocks diagrams presented in Figs. 8.3 and 8.4, the
complete realizations of the active resistor circuits being shown in Fig. 8.39 [12, 13]
and Fig. 8.40 [12, 13].
8.2 Analysis and Design of Multifunctional Structures 401

VDD

IO/2 “M” IO/2

“T” “T”
V1 V2
0
3IOUT1 3IOUT2
IO IO
V
IOUT1 IOUT2
V1T V2T
IOUT1 IOUT2
IO IOUT1IOUT2 IO
IO

“DA”
IOUT IOUT

Fig. 8.39 Active resistor with positive equivalent resistance based on PR 8.1 – complete
implementation

VDD

IO/2 “M” IO/2

“T”
“T”
V1 V2
0
3IOUT1 IO 3IOUT2
IO
V
IOUT
IOUT1 IOUT2
V1T V2T
IOUT1 IOUT2
IO IOUT1 IOUT2 IO
IO

“DA”
IOUT

Fig. 8.40 Active resistor with negative equivalent resistance based on PR 8.1 – complete
implementation
402 8 Multifunctional Structures

VDD

V1 M7 M1 M2 M8 V2

M3 M6

M4 M5

IO IOUT1 IOUT2 IO

Fig. 8.41 Third implementation of the MFC core based on PR 8.1

The equivalent resistances of the circuits presented in Figs. 8.39 and 8.40 are
expressed by the following relations, respectively:

V1  V2 1
RECH ¼ ¼ pffiffiffiffiffiffiffiffiffiffi (8.129)
IOUT2  IOUT1 2KIO

and:

V1  V2 1
RECH ¼ ¼  pffiffiffiffiffiffiffiffiffiffi : (8.130)
IOUT1  IOUT2 2KIO

8.2.1.3 Third Implementation of PR 8.1

The third implementation of PR 8.1 is based on the multifunctional core presented

in Fig. 8.41 [14].
The differential input voltage can be expressed as follows:
rffiffiffiffi
2 pffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffi
V1  V2 ¼ 2 IO  IOUT1 ; (8.131)
K

resulting:
rffiffiffiffiffiffiffiffi
KIO K
IOUT1 ¼ IO  ðV1  V2 Þ þ ðV1  V2 Þ2 (8.132)
2 8
8.2 Analysis and Design of Multifunctional Structures 403

IOUT1 IO IO IOUT2

2IO
V1 M5 M6 M7 M8 V2

IOUT1 +IO IOUT2 +IO

IO IO

M1 M2 M3 M4
V

2IO 2IO

Fig. 8.42 Fourth implementation of the MFC core based on PR 8.1

and:
rffiffiffiffiffiffiffiffi
KIO K
IOUT2 ¼ IO þ ðV1  V2 Þ þ ðV1  V2 Þ2 : (8.133)
2 8

Comparing the previous relations with (8.1) and (8.2), it results:

1
a ¼  pffiffiffi (8.134)
2

and:

1
b¼ : (8.135)
8

8.2.1.4 Fourth Implementation of PR 8.1

The fourth implementation of PR 8.1 is based on the multifunctional core presented

in Fig. 8.42.
404 8 Multifunctional Structures

As M1–M4 transistors implement an arithmetical mean circuit, the expression of

V potential will be:

V1 þ V2
V¼ : (8.136)
2

For M5–M6 differential amplifier, the differential input voltage can be expressed
as follows:
rffiffiffiffi
2 pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffi
V1  V ¼ IOUT1  IO : (8.137)
K

Replacing (8.136) in (8.137), it results:

rffiffiffiffiffiffiffiffi
KIO K
IOUT1 ¼ IO þ ðV1  V2 Þ þ ðV1  V2 Þ2 : (8.138)
2 8

Similarly, for M7–M8 differential amplifier, it can be obtained:

rffiffiffiffiffiffiffiffi
KIO K
IOUT2 ¼ IO  ðV1  V2 Þ þ ðV1  V2 Þ2 : (8.139)
2 8

Comparing the previous relations with (8.1) and (8.2), it results:

1
a ¼ pffiffiffi (8.140)
2

and:

1
b¼ : (8.141)
8

8.2.1.5 Fifth Implementation of PR 8.1

The fifth implementation of PR 8.1 is based on the multifunctional core presented in

Fig. 8.43 [15].
For M1–M2 differential amplifier, the differential input voltage can be expressed
as follows:
rffiffiffiffi
2 pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffi
V 1  V2 ¼ IOUT1  IO : (8.142)
K
8.2 Analysis and Design of Multifunctional Structures 405

IOUT1 IO IO IOUT2

V1 M1 M2 M3 M4 V2

Fig. 8.43 Fifth implementation of the MFC core based on PR 8.1

So:
pffiffiffiffiffiffiffiffiffiffi K
IOUT1 ¼ IO þ 2KIO ðV1  V2 Þ þ ðV1  V2 Þ2 : (8.143)
2

Similarly, for M3–M4 differential amplifier, the expression of IOUT2 current will be:

pffiffiffiffiffiffiffiffiffiffi K
IOUT2 ¼ IO  2KIO ðV1  V2 Þ þ ðV1  V2 Þ2 : (8.144)
2

Comparing the previous relations with (8.1) and (8.2), it results:

pffiffiffi
a¼ 2 (8.145)

and:

1
b¼ : (8.146)
2

8.2.1.6 Sixth Implementation of PR 8.1

The sixth implementation of PR 8.1 is based on the multifunctional core presented

in Fig. 8.44 [16].
It was demonstrated in Chap. 3 (“Squaring Circuits”) – Fig. 3.17 that:

pffiffiffiffiffiffiffiffiffiffi K
IOUT1 ¼ IO þ 2KIO ðV1  V2 Þ þ ðV1  V2 Þ2 (8.147)
2
406 8 Multifunctional Structures

2IO

V2 V1
M3 M4

IOUT1 VDD IOUT2

IO
M1 M5 M6 M7 M8 M2

M9
2IO 2IO

Fig. 8.44 Sixth implementation of the MFC core based on PR 8.1

and:

pffiffiffiffiffiffiffiffiffiffi K
IOUT2 ¼ IO  2KIO ðV1  V2 Þ þ ðV1  V2 Þ2 : (8.148)
2

Comparing the previous relations with (8.1) and (8.2), it results:

pffiffiffi
a¼ 2 (8.149)

and:

1
b¼ : (8.150)
2

8.2.1.7 Seventh Implementation of PR 8.1

The seventh implementation of PR 8.1 is based on the multifunctional core

presented in Fig. 8.45 [17].
The differential input voltage can be expressed as follows:
rffiffiffiffi
2 pffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffi
V1  V2 ¼ 2 IO  IOUT1 ; (8.151)
K
8.2 Analysis and Design of Multifunctional Structures 407

VDD

IO IO

M3 M8 M6 M4

V1 V2
M1 M5 M7 M2

IOUT1 IOUT2

Fig. 8.45 Seventh implementation of the MFC core based on PR 8.1

resulting:
rffiffiffiffiffiffiffiffi
KIO K
IOUT1 ¼ IO  ðV1  V2 Þ þ ðV1  V2 Þ2 (8.152)
2 8

and, similarly:
rffiffiffiffiffiffiffiffi
KIO K
IOUT2 ¼ IO þ ðV1  V2 Þ þ ðV1  V2 Þ2 : (8.153)
2 8

Comparing the previous relations with (8.1) and (8.2), it results:

1
a ¼  pffiffiffi (8.154)
2

and:

1
b¼ : (8.155)
8

8.2.1.8 Eighth Implementation of PR 8.1

The eighth implementation of PR 8.1 uses the multifunctional core presented in

Fig. 8.46 [18].
An alternative realization of the same circuit is presented in Fig. 8.47 [18] and it
uses FGMOS transistors for implementing the arithmetical mean of the input
potentials.
408 8 Multifunctional Structures

Fig. 8.46 Eighth

implementation (1) of the IOUT1 IO IOUT2
MFC core based on PR 8.1 M

M1 M3 M2
V1 V2
V

ISS

-VDD

Fig. 8.47 Eighth (2)

implementation of the MFC IOUT1 IO IOUT2
core based on PR 8.1

M1 M3 M2
V1 V2
V

ISS

-V DD

The expressions of IOUT1 and IOUT2 currents are:

K
IOUT1 ¼ ðV1  V  VT Þ2 (8.156)
2

and:

K
IOUT2 ¼ ðV2  V  VT Þ2 : (8.157)
2

The drain current of M3 transistor can be expressed as follows:

 2
K V1 þ V2
IO ¼  V  VT : (8.158)
2 2
8.2 Analysis and Design of Multifunctional Structures 409

Thus:
rffiffiffiffiffiffiffi
V1 þ V2 2IO
V¼  VT  : (8.159)
2 K

It results:

rffiffiffiffiffiffiffi!2
K V1  V2 2IO
IOUT1 ¼ þ (8.160)
2 2 K

and:

rffiffiffiffiffiffiffi!2
K V 1  V2 2IO
IOUT1 ¼ þ ; (8.161)
2 2 K

or:
rffiffiffiffiffiffiffiffi
KIO K
IOUT1 ¼ IO þ ðV1  V2 Þ þ ðV1  V2 Þ2 (8.162)
2 8

and:
rffiffiffiffiffiffiffiffi
KIO K
IOUT2 ¼ IO  ðV1  V2 Þ þ ðV1  V2 Þ2 : (8.163)
2 8

Comparing the previous relations with (8.1) and (8.2), it can be obtained:

1
a ¼ pffiffiffi (8.164)
2

and:

1
b¼ : (8.165)
8

8.2.2 Multifunctional Structures Based on the Second

Mathematical Principle

The implementation of the multifunctional core using the second mathematical

principle is presented in Fig. 8.48 [3].
410 8 Multifunctional Structures

Fig. 8.48 MFC core based

on PR 8.2 IO IO IOUT

ID2

M1 M2 V2
V1

M3

Replacing the square-root dependence of the gate-source voltage on the drain

current for a MOS transistor biased in saturation and considering identical
transistors, it results:
rffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffi
2IO 2ID2
V1  V 2 ¼  ; (8.166)
K K

equivalent with:

pffiffiffiffiffiffiffiffiffiffi K
ID2 ¼ IO  2KIO ðV1  V2 Þ þ ðV1  V2 Þ2 : (8.167)
2

Thus, the output current of the multifunctional core presented in Fig. 8.48, IOUT ,
will have the following expression:

pffiffiffiffiffiffiffiffiffiffi K
IOUT ¼ ID2  IO ¼  2KIO ðV1  V2 Þ þ ðV1  V2 Þ2 : (8.168)
2

The complete implementation of a linear differential amplifier circuit based on

the second mathematical principle is presented in Fig. 8.11 [3]. MFC 1 from
Fig. 8.49 is realized using M3 and M4 transistors, while MFC 2 from the same
figure is composed from M1 and M2 transistors.
The complete circuit of the multiplier circuit based on the second mathematical
principle is presented in Fig. 8.50 [3].
The implementation in CMOS technology of the squaring circuit based on the
second mathematical principle is also presented in Fig. 8.49, the difference between
the differential amplifier and the squaring circuit being the consideration of the
difference, respectively the sum of the output currents.
8.2 Analysis and Design of Multifunctional Structures 411

VDD

M5 M6 M7 M8 M9

IO IO IO IO IO IOUT1

IOUT2

M3 M1 M2 M4
V1 V2

Fig. 8.49 Differential amplifier based on PR 8.2 – complete implementation

VDD

V3 V4
M5 M5’ M6 M6’ M7 M8
IO1 IO2 IO2 IOUT1 IOUT1
IO1
IOUT
IOUT1

V1 M3 M1 M2 M4 V2

Fig. 8.50 Multiplier circuit based on PR 8.2 – complete implementation

412 8 Multifunctional Structures

Fig. 8.51 MFC core based VDD

on PR 8.3

IOUT

IOUT1 IOUT2

V1 V2

IO’
i1

I
IO

SQ

8.2.3 Multifunctional Structures Based on the Third

Mathematical Principle

Considering a classical CMOS differential amplifier biased at IO 0 current and

having all MOS transistors working in saturation region, the IOUT differential output
current will present a strong nonlinear dependence on the differential input voltage,
V1  V2 , that can be expressed as follows:
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
KðV1  V2 Þ2 K 2 ðV1  V2 Þ4
IOUT ¼ IOUT1  IOUT2 ¼ IO 0  ; (8.169)
IO 0 4IO 02

equivalent with:
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
V1  V2
IOUT ¼ 4KIO 0  K 2 ðV1  V2 Þ2 : (8.170)
2

So, superior-order distortions will characterize the behavior of the classical

differential structure, imposing the design of a linearization technique for removing
the superior-order terms from the transfer characteristic.
The method illustrated in Fig. 8.51 [19] (based on the third mathematical
principle) for obtaining a linear transfer characteristic of the differential amplifier
is to obtain the bias current, IO 0 , of the entire differential structure as a sum of a
8.2 Analysis and Design of Multifunctional Structures 413

VDD

IOUT1
IOUT2

IOUT1 IOUT1 IOUT2 IOUT2

IOUT IOUT
V1 V2

IO ’
i1

I
IO

SQ

Fig. 8.52 Active resistor with positive equivalent resistance based on PR 8.3

main constant term, IO and an additional term proportional with the square of the
differential input voltage, I ¼ KðV1  V2 Þ2 =4:

K
IO 0 ¼ IO þ I ¼ IO þ ðV1  V2 Þ2 ; (8.171)
4
resulting, in this case, a perfect linear behavior of the optimized differential
amplifier:
pffiffiffiffiffiffiffiffi
IOUT ¼ IOUT1  IOUT2 ¼ KIO ðV1  V2 Þ ¼ Gm ðV1  V2 Þ; (8.172)

Gm being the equivalent transconductance of the proposed structure, that can be

controlled by the biasing current, IO .
The improved linearity differential amplifier presented in Fig. 8.51 can be re-
used in order to obtain a linear active resistor, having the circuit presented in
Fig. 8.52 [19].
For this circuit, the current passing through the input pins, IOUT , can be expressed as:
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
V 1  V2
IOUT ¼ IOUT1  IOUT2 ¼ 4KIO 0  K 2 ðV1  V2 Þ2 : (8.173)
2
414 8 Multifunctional Structures

Because the biasing current of the circuit core, IO 0 , was designed to be the sum of
a main constant term IO and an additional term, proportional with the squaring of
the differential input voltage (8.171), IOUT current will have the following
expression:
pffiffiffiffiffiffiffiffi
IOUT ¼ KIO ðV1  V2 Þ: (8.174)

Defining the equivalent resistance of the circuit from Fig. 8.52 as the ration
between the differential input voltage, V1  V2 , and the current passing through the
input pins, IOUT , it results:

V1  V2 1
RECH ¼ ¼ pffiffiffiffiffiffiffiffi : (8.175)
IOUT KIO

Starting from the active resistor with positive equivalent resistance presented
in Fig. 8.52, in order to obtain a circuit with a controllable negative equivalent
resistance circuit, the method consists in the utilization of two cross-connections
between input and output, resulting the circuit presented in Fig. 8.53. Because
now IOUT ¼ IOUT2  IOUT1 , the equivalent resistance of the circuit from Fig. 8.53
[19] is:

1
RECH 0 ¼ RECH ¼  pffiffiffiffiffiffiffiffi : (8.176)
KIO

In order to obtain a voltage multiplier starting from the differential linearized

structure presented in Fig. 8.51, a similar squaring circuit will be re-used for
generating a current proportional with the squaring of another differential voltage,
V3  V4 , resulting the circuit presented in Fig. 8.54 [19].
This current, named IOX , will be further used for replacing the IO constant
current, which was biasing the differential amplifier presented in Fig. 8.51. Thus:

K
IOX ¼ ðV3  V4 Þ2 : (8.177)
4

Replacing IO from (8.174) with IOX given by (8.177), it results that the circuit
presented in Fig. 8.54 implements the multiplying function:

K
IOUT ¼ ðV1  V2 ÞðV3  V4 Þ: (8.178)
2
8.2 Analysis and Design of Multifunctional Structures 415

VDD

IOUT2 IOUT1

IOUT1 IOUT1 IOUT2 IOUT2

IOUT IOUT
V1
V2

IO’
i1

I
IO

SQ

Fig. 8.53 Active resistor with negative equivalent resistance based on PR 8.3

8.2.4 Multifunctional Structures Based on the Fourth

Mathematical Principle

8.2.4.1 Implementation of the Multifunctional Circuit Based on the Second-

Order Approximation of a Continuous Mathematical Function

In order to obtain the second-order approximation of a function, a “C” coefficient

block (Fig. 8.55) can be used, a0 , a1 and a2 coefficients corresponding to the Taylor
series expansion (8.38).
The output current of the circuit presented in Fig. 8.55 will be:

I2
IOUT ¼ a0 IO þ a1 IIN þ a2 IN
IO
"   # 
2
IIN IIN IIN
¼ IO a0 þ a1 þ a2 ffi IO f ¼ IO f ðxÞ: (8.179)
IO IO IO
416 8 Multifunctional Structures

Fig. 8.54 Multiplier circuit VDD

based on PR 8.3

IOUT

IOUT1 IOUT2

V1 V2

I O’
i1

IOX I

SQ I

V3 SQ II V4

Fig. 8.55 The “C” block for IO

PR 8.4
IIN IOUT
2
C
IIN /IO

8.2.4.2 Implementation of the Multifunctional Circuit Based on the Third-

Order Approximation of a Continuous Mathematical Function

The block diagram of the multifunctional circuit is presented in Fig. 8.56. The
MULT/DIV circuit has the implementation presented in Fig. 8.59.
The expression of IOUT 0 current of MULT/DIV circuit is:

I1
IOUT 0 ¼ IO : (8.180)
I2
So:
 
p2 IIN
ðp2 =qÞIIN q IO
IOUT 0 ¼ IO ¼ IO  : (8.181)
IO  qIIN =p 1  q IINp IO
8.2 Analysis and Design of Multifunctional Structures 417

I1=p2IIN/q
mIO
IO IOUT’ IOUT
MULT / DIV
IO I2
(n - p2/q)IIN

qIIN/p

Fig. 8.56 MFC core for second-order approximation based on PR 8.4 – block diagram

The output current of the circuit having the block diagram presented in Fig. 8.56
will have the following expression:

p2
IOUT ¼ IOUT 0  n  IIN þ mIO
q
2 p2   3
IIN  2

p I
¼ IO 4 þ m5
q IO
  n IN
(8.182)
1  q IIN q IO
p IO
" p2  #
q x p2
¼ IO  n xþm :
1  qp x q

Using the notation x ¼ IIN =IO and (8.44) relation, it results that IOUT current
represents the third-order approximation of f ðxÞ function:

IIN
IOUT ¼ IO gðxÞ ¼ IO g ffi IO f ðxÞ: (8.183)
IO

8.2.4.3 Implementation of the Multifunctional Circuit Based on the Third-

Order Approximation of a Continuous Mathematical Function Using
Two Primitive Functions

The block diagram of the multifunctional circuit is presented in Fig. 8.57. The
MULT/DIV circuit has the implementation presented in Fig. 8.59.The expressions
of IOUTa and IOUTb currents are:

I1a
IOUTa ¼ IO (8.184)
I2a
418 8 Multifunctional Structures

I1a=(2q – p)IO
(m + 6q−7p) IO
IO IOUTa
MULT / DIV a
IO I2a

IIN IOUT

I1b =16(p – q) IO

IO IOUTb
MULT / DIV b
2IO I2b
(n+ 2q− 3p) IIN

IIN

Fig. 8.57 MFC core for third-order approximation based on PR 8.4 – block diagram

and:

I1b
IOUTb ¼ IO : (8.185)
I2b

So:

ð2q  pÞIO 2q  p
IOUTa ¼ IO ¼ IO   (8.186)
IO  IIN 1  IIN IO

and:

16ðp  qÞIO 16ðp  qÞ

IOUTb ¼ IO ¼ IO  : (8.187)
2IO  IIN 2  IIN IO

The output current of the circuit having the block diagram presented in Fig. 8.57
will have the following expression:

IOUT ¼ IOUTa þ IOUTb þ ðn þ 2q  3pÞIIN þ ðm þ 6q  7pÞIO : (8.188)

8.2 Analysis and Design of Multifunctional Structures 419

Thus:
2 3

4 2q  p 16ðp  qÞ I
IOUT ¼ IO  þ   þ ðn þ 2q  3pÞ IN þ ðm þ 6q  7pÞ5:
1  IO
IIN
2  IO
IIN IO

(8.189)

Using the notation x ¼ IIN =IO and (8.44) relation, it results that IOUT current
represents the third-order approximation of f ðxÞ function:
 
2q  p 16ðp  qÞ
IOUT ¼ IO þ þ ðn þ 2q  3pÞx þ ðm þ 6q  7pÞ
1x 2x (8.190)
¼ IO gðxÞ ffi IO f ðxÞ:

8.2.4.4 Implementation of the Multifunctional Circuit Based on the Fifth-

Order Approximation of a Continuous Mathematical Function Using
Four Primitive Functions

The block diagram of the multifunctional circuit is presented in Fig. 8.58. The
MULT/DIV circuit has the implementation presented in Fig. 8.59.
The expressions of IOUTa , IOUTb ,IOUTc and IOUTd currents are:

I1a
IOUTa ¼ IO ; (8.191)
I2a

I1b
IOUTb ¼ IO ; (8.192)
I2b

I1c
IOUTc ¼ IO (8.193)
I2c

and:

I1d
IOUTd ¼ IO (8.194)
I2d

So:

a1 IO a1
IOUTa ¼ IO ¼ IO  ; (8.195)
IO  IIN 1  IIN
IO
420 8 Multifunctional Structures

I1a=a1 IO
a6 I O
IO IOUTa
MULT / DIV a
IO I2a

IIN

I1b=a2 IO

IO IOUTb
MULT / DIV b
IO I2b

IIN
IOUT

I1c=a3 IO

IO IOUTc
MULT / DIV c
2IO I2c

IIN

I1d=a4 IO

IO IOUTd
MULT / DIV d
2IO I2d a5 IIN

IIN

Fig. 8.58 MFC core for fifth-order approximation based on PR 8.4 – block diagram

a2 IO a2
IOUTb ¼ IO ¼ IO  ; (8.196)
IO þ IIN 1 þ IIN
IO

a3 I O a3
IOUTc ¼ IO ¼ IO   (8.197)
2IO  IIN 2  IIN
IO
8.2 Analysis and Design of Multifunctional Structures 421

and:

a4 IO a4
IOUTd ¼ IO ¼ IO  : (8.198)
2IO þ IIN 2 þ IINIO

The output current of the circuit having the block diagram presented in Fig. 8.58
will have the following expression:

IOUT ¼ IOUTa þ IOUTb þ IOUTc þ IOUTd þ a5 IIN þ a6 IO : (8.199)

Thus:
2 3

a1 a2 a3 a4 I
IOUT ¼ IO 4  þ  þ  þ   þ a5 IN þ a6 5:
1 IIN
1þ IIN
2 IIN
2þ IIN IO
IO IO IO IO

(8.200)

Using the notation x ¼ IIN =IO and (8.44) relation, it results that IOUT current
represents the fifth-order approximation of f ðxÞ function:

a1 a2 a3 a4
IOUT ¼ IO þ þ þ þ a5 x þ a6 ¼ IO gðxÞ ffi IO f ðxÞ:
1x 1þx 2x 2þx
(8.201)

A possible implementation of the MULT/DIV circuit from the previous block

diagrams uses as circuit cores two current squaring circuits, having the realization
shown in Fig. 8.59.
For the MOS transistors from Fig. 8.59a, the equation of the translinear loop can
be expressed as follows:

2VGS ðIO Þ ¼ VGS ðID1 Þ þ VGS ðID1 þ IIN Þ; (8.202)

resulting:
pffiffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 IO ¼ ID1 þ ID1 þ IIN : (8.203)

So:

IIN I2
ID1 ¼ IO  þ IN : (8.204)
2 16IO

The expression of the output current will be:

IIN I2
IOUT ¼ ID1 þ  IO ¼ IN : (8.205)
2 16IO
422 8 Multifunctional Structures

a
VDD

K/2 K

IIN/2 IIN/2
IIN
IO IO IOUT

ID1 ID1
IIN/2

CM
IOUT

IOUT1 IOUT2
IOUT IOUT
SQ I SQ II
IO IIN IO IIN

I2 2(I1+IO) I2 2(I1 -IO)

Fig. 8.59 (a) The functional core of the MULT/DIV circuit and (b) the block diagram of the
MULT/DIV circuit

The output current of the MULT/DIV circuit from Fig. 8.59b has the following
expression:

IOUT ¼ IOUT1  IOUT2 ; (8.206)

resulting:

ðI1 þ IO Þ2 ðI1  IO Þ2 I1
IOUT ¼  ¼ IO : (8.207)
4I2 4I2 I2
8.2 Analysis and Design of Multifunctional Structures 423

Fig. 8.60 The IOUT ðIIN Þ simulation for the squaring circuit

Table 8.3 Comparison IIN (mA) IOUT th. (mA) IOUT sim (mA)
between the simulated and the
theoretical estimated results 50 0.156 0.110
for the current squarer 100 0.625 0.660
presented in Fig. 8.59a 150 1.406 1.461
200 2.500 2.574
250 3.906 3.991
300 5.625 5.711
350 7.656 7.719
400 10.000 10.089
450 12.656 12.713
500 15.625 15.714
550 18.906 18.956
600 22.500 22.587
650 26.406 26.446
700 30.625 30.707
750 35.156 35.184
800 40.000 40.077
850 45.156 45.171
900 50.625 50.596
950 56.406 56.407
1,000 62.500 62.564

The IOUT ðIIN Þ simulation of the squaring circuit presented in Fig. 8.59a is shown
in Fig. 8.60. The IO current is equal with 1 mA, while the range of IIN current was
chosen to be between 0 and 1 mA.
A comparison between the simulated and the theoretical estimated results for the
current squarer presented in Fig. 8.59a is shown in Table 8.3.
Fig. 8.61 The simulated approximation error eSQ ðIIN Þ for the squaring circuit

Fig. 8.62 The IOUT ðI1 Þ simulation for the MULT/DIV circuit from Fig. 8.59b

The simulated approximation error, eSQ ðIIN Þ, for the squaring circuit from
Fig. 8.59a is shown in Fig. 8.61. The error is smaller than 0:0049% for an extended
range of the input current.
The IOUT ðI1 Þ simulation for the MULT/DIV circuit presented in Fig. 8.59b is
shown in Fig. 8.62. The IO and I2 currents have the following values:
IO ¼ 500 mA and I2 ¼ 1 mA, while the range of I1 current was chosen to be
between 0 and 1 mA.
8.2 Analysis and Design of Multifunctional Structures 425

Fig. 8.63 The simulated linearity error of IOUT ðI1 Þ characteristic for the MULT/DIV circuit from
Fig. 8.59b

Fig. 8.64 The IOUT ðtÞ simulation for the MULT/DIV circuit from Fig. 8.59b

The simulated linearity error of IOUT ðI1 Þ characteristic for the MULT/DIV
circuit from Fig. 8.59b is shown in Fig. 8.63. The linearity error is smaller than
0:006% for an extended range of the input currents.
For the same MULT/DIV circuit presented in Fig. 8.59b, a transient analysis was
performed. The IO current is a sinusoidal current with an amplitude of 50 mA and a
frequency equal with 1 kHz, while I1 current is a sinusoidal current having an
amplitude of 0:3 mA and a frequency of 30 kHz. The I2 current is a continuous
current, equal with 1 mA. The simulation of the output current is presented in
Fig. 8.64.
426 8 Multifunctional Structures

Fig. 8.65 The IOUT ðI2 Þ simulation for the MULT/DIV circuit presented in Fig. 8.59b

Table 8.4 Comparison I2 (mA) IOUT th. (mA) IOUTsim (mA)

between the simulated and the
theoretical estimated results 0.2 750.00 545.45
for the MULT/DIV circuit 0.4 375.00 375.01
from Fig. 8.59b 0.6 250.00 249.99
0.8 187.50 187.49
1 150.00 149.983
1.2 125.00 124.984
1.4 107.14 107.932
1.6 93.75 93.734
1.8 83.33 83.318
2 75.00 74.985
2.2 68.18 68.167
2.4 62.50 62.451
2.6 57.69 57.678
2.8 53.57 53.557
3 50.00 49.987
3.2 46.87 46.862
3.4 44.12 44.105
3.6 41.67 41.654
3.8 39.47 39.460
4 37.50 37.487

The IOUT ðI2 Þ simulation for the MULT/DIV circuit presented in Fig. 8.59b is
presented in Fig. 8.65. The IO and I1 currents have the following values: IO ¼
0:5 mA and I1 ¼ 0:3 mA, while the range of I2 current was chosen to be between 0
and 4 mA.
References 427

A comparison between the simulated and the theoretical estimated results for the
previously presented MULT/DIV circuit is shown in Table 8.4.

8.3 Conclusions

Chapter introduces the original concept of multifunctional structures – active

circuits that are able to implement, starting from the same circuit core, both linear
and nonlinear mathematical functions. The approach of analog signal processing
from the perspective of using multifunctional cores presents the very important
advantages of reducing the power consumption and silicon area per implemented
function. As the design effort is mainly concentrated for improving the
performances of the functional core, the design costs for a circuit function can be
strongly reduced using this design method.

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Index

A Amplifier
Accuracy current, 1, 2, 6, 13, 15, 62–64, 117, 118,
active resistor structures, 46, 323, 328, 120, 122–124, 126, 130–132,
329, 341, 344, 360 134–135, 149, 157–161, 172, 195,
computational circuits, 171 200, 201, 205, 206, 220–222, 323,
differential amplifiers, 30, 31 324, 327, 338, 344, 346, 352, 364,
exponential circuits, 285, 291, 292 372–373, 386, 392
multifunctional structures, 47, 376 operational, 1, 3, 10, 44, 50, 364–365,
square-root circuits, 288, 375 371–372, 434
squaring circuits, 288, 292, 375 transconductance, 23, 27, 30, 33, 41, 44,
VLSI designs, 130, 246, 306, 322, 387 55, 69, 71, 75, 77–80, 112, 129,
Active bulk, 66–67, 143–144, 172, 327, 325, 327, 344, 346, 400, 435
335, 344 voltage, 1, 2, 6, 7, 9, 23, 38–40, 55, 61,
Active filter, 27 71, 73, 112, 113, 190, 200, 324,
Active load 326, 327, 346, 352, 404, 435
current-mirror, 122–123 Analog, 82, 139, 246, 264, 387, 390, 427
diode-connected MOS transistor, 122–123 design, 4
Active resistor circuit signal processing, 82, 139, 246, 264,
CMOS circuits, 346, 360 387, 390, 427
equivalent resistance, 323–325, 328, 329, Analog computational circuits
331, 332, 334, 336–338, 340, 341, linear, 180, 433
344–346, 349, 352–355, 357, 358, nonlinear, 4
360, 365–366 Analysis
error, 327 computational structures, 246, 431
linearity, 323–327, 335, 338–339, 341, VLSI designs, 246, 392
344, 346–352, 354, 356–358 Anti-parallel connection
error, 332, 333, 425 differential amplifiers, 3, 62, 64
range, 332, 346 multiplier circuits, 62
negative resistance, 325, 328, 330, 332, Applications
333, 340, 345, 349, 354, 360, analog signal processing circuits, 82, 139,
365–366, 387, 388, 392, 393, 400, 246, 387, 390, 427
401, 415 computational structures, vii–ix, 181, 264
positive resistance, 325, 326, 328–331, low-power circuits, 171, 182
334–337, 339–344, 346–348, 350, low-voltage circuits, 436
353, 355–360, 365, 387, 392, 393, VLSI designs, 130, 246,
400, 401, 413, 414 322, 392

441
442 Index

Approximation function, 267–274, 276–278, Cascode current source, 436

280, 281, 284, 286, 288, 289, 291, Channel length, 133–134, 431, 434, 436
293–295, 297, 298, 300–306, Channel-length modulation
374–384, 415–427, 437 MOS model, 433, 435
Arithmetical mean MOS transistor, 431, 433–434, 436
CMOS computational circuits, 62, 240, 285 Characteristic equation
current squarer, 164, 187, 229, 243, 255, 309 gate-source voltage, 10, 13, 18, 23–24, 28,
Aspect ratios 36, 40, 51, 113, 175, 177, 178, 180,
NMOS transistors, 291, 435 204, 231, 236, 259
PMOS transistors, 291, 435 MOS transistors, 168, 174, 179, 222,
Asymmetry 231–234, 238, 252, 260, 288, 295,
differential amplifiers, 3, 62–64, 66, 157, 313, 319
158, 188, 222, 223 saturation operation, 168, 179, 231–234,
MOS transistors geometries, 157, 158, 222, 223 252, 255, 260, 288
translinear loop, 11, 13, 17, 35, 42, 51,
167–169, 174, 177–179, 199, 203,
B 220, 225, 226, 230, 232–235, 244,
Bias current, 3, 6, 25, 32, 41, 42, 61–64, 72, 77, 252, 253, 255, 258, 260, 261, 288,
112, 126, 129, 130, 134, 136, 174, 295, 312, 319
254–255, 290, 325, 327, 328, 338–340, Chip
349, 353, 364–367, 372, 413, 414, 434 analog design, 4
Biasing VLSI circuits, 360
saturation, 1, 10–11, 39–41, 53, 78, 84, 113, Circuit
126, 142, 152, 165, 168, 179, 191, accuracy, 30, 31, 59, 288, 375
202, 207, 215, 216, 224, 231–234, analysis, 4, 22, 109, 122, 153, 181–182,
246, 252, 257, 280, 286, 288, 313, 185–245, 249–264, 267–306, 309–360
315, 334, 341, 350 behavior, 76, 92
strong inversion, 433 complexity, 95–96, 143–144, 171, 251,
weak inversion, 66, 92, 171, 174–176, 178, 291, 318, 375
187, 237, 238, 283, 286, 289, 298, operation, 1, 4, 9, 10, 72, 75, 164, 170, 231,
299, 306, 319 244, 254, 260, 264, 288, 295, 299,
Bias reference current, 27, 89, 179, 195, 229, 352, 354, 366–373, 432, 434–436
238, 280, 288, 315, 353, 370, 372 synthesis, 1, 71, 89, 185–187, 249–250,
Bias voltage, 17, 23, 25, 36, 42, 55, 60, 61, 267–280, 309–311, 323–324
85, 102, 115, 135, 146, 323 Common-mode input voltage
Bipolar transistor active resistor structures, 328, 341
logarithmic law, 238 differential amplifiers, 6, 7, 69–71, 73–74,
Building block, viii 77–80, 352
Bulk-driven maximal range, 69–71, 73, 79, 288
circuits, 143–146, 335 multiplier circuits, 94, 134–135, 352
MOS transistors, 145, 171 rail-to-rail operation, 3, 69, 77, 78, 85
Bulk-source voltage, 144–146, 175, 431 Compensation
linearity, 8, 85, 289, 346, 434, 435
squaring characteristic, 8, 10, 124, 434
C Complementary MOS transistors (CMOS)
Carriers’ mobility, 434 analog integrated circuits, 246
Cascode circuits computational circuits, 171, 246, 432
current mirrors, 31, 133–134, 436 NMOS devices, 47, 69, 71, 74, 75,
current sources, 436 435–436
minimal output voltage, 436 PMOS devices, 47, 69, 71, 74, 75, 435–436
minimal supply voltage, 436 technology, 181, 226, 241, 246, 269, 285,
power supply rejection ratio, 436 306, 322, 360, 410
Cascode current mirror, 31, 133–134, 436 VLSI designs, 130, 246, 306, 322, 360, 433
Index 443

Complexity, 27, 95–96, 143–144, 171, 172, Cross-coupling

251, 291, 318, 354, 375, 387 active resistor structures, 328
Computation, 37, 84, 134, 171, 181, 200, 218, differential amplifiers, 158, 223
228, 240, 246, 260, 262, 264, 286, linearity increasing, 158
289, 293, 315, 431–434 multiplier circuits, 158
Computational circuits second-order effects, 223
active resistor structures, 323, 328, 329, Current
341, 344, 360 balance, 180
complexity, 171 gain, 6, 64, 67, 73–75, 299, 431
Euclidean distance circuits, 309–322 mirror, 7, 30, 31, 33, 49–51, 99,
exponential circuits, 433, 434 107, 122–124, 133–134, 156,
multifunctional structures, 432 188, 192, 210, 241, 242, 253,
multipliers, 171 285, 291, 295, 318, 319,
square-root circuits, 249–264 324–325, 329, 336, 346, 353,
squaring circuits, 432, 434 356, 357, 369, 370, 375,
Computational structures, 181, 246, 264 434, 436
Configuration, 50, 97, 115, 117, 118 multiplier circuits, 89–182, 296
Connection, 3, 16, 19, 32, 35, 45, 46, 50, 62, ratio, 3, 153, 157, 172, 175, 286, 289,
64, 66, 69, 71, 73, 77–79, 122, 135, 325, 340, 353, 354, 374, 376,
139, 140, 144, 147, 153, 158–159, 377, 414
165, 203, 205, 210, 220, 262, 284, source, 7, 25, 35, 172, 203, 434, 436
292, 296, 323–325, 327–329, 332, squaring circuits, 169, 170, 185–188,
337, 340, 355, 365, 368, 370, 373, 192, 195, 199, 224–245, 285,
392, 414, 433 289, 295, 305, 312, 314, 317,
Constant coefficients, 63, 91, 295, 374, 319, 320, 322, 350, 354,
378–380, 383 369–371, 374, 375, 390, 395, 421
Constant sum of gate-source voltages, 40, 48, Current-controlled voltage sources
113, 190, 326, 385 differential amplifiers, 25, 41, 42, 49, 327
Continuity multifunctional circuits, 385
mathematical function, 374–384, multipliers, 47
415–427, 437 squaring circuits, 191
MOS transistor model, 89, 144, 431, 433 Current-input variable, 181–182, 246
Continuous mathematical function Current-mode operation
Euclidean distance function, 309–310 improvement of frequency response, 264
exponential function, 267, 271, 273, low-voltage operation, 132
274, 277, 278, 280, 282, 284, Current-pass circuit, 147, 324, 339, 340,
297, 298, 433 346, 349, 352, 354, 355
multiplying function, 112
square-root function, 15, 241, 254, 255,
285, 368 D
squaring function, 34, 187, 189, 238, 257 DC offset, 434
Controllability, 157, 158, 188, 222, 223, DC shifting, 52, 54, 128, 343, 398
325–326, 340, 354, 363, 414 DDA. See Differential difference amplifier;
Controllable equivalent resistance, 62, 324, Double differential amplifier
325, 329, 331–334, 340, 349, Design
352–354, 357, 358, 360, 363, computational circuits, 171, 431
365, 414 costs, 427
Controllable transconductance, 25, 27, 28, linear structure, 4, 6, 20, 33, 42, 130, 226
34, 41, 42, 46, 51, 62, 325, 327, methods, 85, 427
339, 364, 365, 413 nonlinear structure, 4–6, 65, 154–155,
Cross-connection 346, 385
current references, 89, 195, 238 silicon area, 20, 360
power supply rejection, 436 techniques, 85, 182, 434
444 Index

Device, 1, 20, 47, 53, 61, 69, 84–85, 95–96, 175, 176, 179, 181, 188, 195, 197,
106, 126, 137, 145, 171, 175, 177, 206–208, 210, 211, 213, 215–218,
181, 191, 197, 207, 215, 216, 245, 224, 230, 238, 241–243, 251, 263,
255, 314, 321, 322, 341, 347, 350, 280, 283, 298, 311, 314, 318, 329,
351, 354, 433, 435 336, 350, 359, 368, 408, 410
Difference circuit, 27, 34, 36, 103, 144, 151, Drain-source voltage, 150, 436
204, 367, 410, 432, 433
Different-biased differential structures, 433
Differential amplifier, 1, 100, 188, 323, 363 E
Differential difference amplifier (DDA), 27, 28 Elementary differential amplifier, ix, 1, 22
Differential input voltage, 1, 2, 4, 6, 9, 11, Elementary mathematical principles, viii, ix,
16, 17, 22, 23, 25, 27, 36–40, 49, 1, 89, 93, 185
50, 53, 61, 62, 90, 100, 102, 107, Equation, 4, 11, 13, 17, 20, 21, 35, 45, 46,
110, 112, 114, 120–122, 124, 51, 100, 158, 167–169, 174,
125, 127, 130–132, 134–137, 177–179, 199, 203, 220,
139, 140, 146, 157, 159–160, 223–226, 230, 232–235, 244,
189, 191, 195, 200–202, 206, 252, 253, 255, 258, 260, 261,
209, 215, 216, 219, 222, 223, 288, 295, 312, 319, 421
245, 262, 311, 325, 326, Equivalent resistance, ix, 62, 112, 323–325,
338–341, 346, 348, 349, 351, 328–360, 363, 365–366, 387, 388,
353, 354, 365, 368, 372–373, 392, 393, 400–402, 413–415, 431
389, 394, 402, 404, 406, Equivalent transconductance, 17, 18, 25–28,
412–414, 432 30–34, 37, 41, 42, 44–46, 48, 50,
Differential-mode 51, 55, 62, 69, 71–73, 75–80, 129,
input voltage, 6, 95, 134, 145 325, 327, 339, 344, 364, 365, 387,
output voltage, 64, 83, 95, 146, 213 392, 400, 413, 435
Differential output current, 5, 10, 11, 13–19, Error mechanisms, 431–436
24–26, 29, 33, 37, 40–42, 44, 45, Error sources
48–50, 52, 58, 60–65, 68, 79, 81, current mirror mismatch, 434
83, 84, 96, 98, 99, 105, 107–110, layout errors, 433
112, 114, 115, 124, 130–132, 136, technological limitations, 170, 244
143–145, 147, 149, 160–162, 164, Euclidean distance circuit, vii, ix, 309–322
178, 210, 211, 219, 220, 229, 250, Even-order distortions, 63
257–260, 311, 324–326, 386, 392, Even-order term, 63
412, 434, 435 Expansion, 5, 63–66, 68, 146, 153, 267–269, 271,
Differential output voltage, 69 273, 274, 277, 279, 280, 288–290,
Differential structure, 1–85, 107, 115, 130, 295, 306, 374–380, 383, 415
136, 338, 346, 400, 412–413, 433 Exponential characteristic
Distortions, 1, 4, 61–66, 68, 69, 136, 154–155, bipolar transistor, 306
372, 412, 433, 434 subthreshold-operated MOS transistor,
Divider circuit, 166, 168, 169, 295, 354, 355 viii–ix, 175
Doping, 433 Exponential circuits, viii–ix, 267–306
Double differential amplifier (DDA), 79–81 Exponential converter, 298
Double drive Exponential function, 267, 268, 270, 271,
bulk effect, 171, 335 273, 274, 276–278, 280–282, 284,
bulk-source voltage, 171, 175 286, 288–295, 297, 298, 300–304,
exponential characteristic, 306 306, 433
MOS transistor, 171
weak inversion operation, 171
Drain current, 6, 13, 20, 21, 23–24, 26, 28, F
30–33, 42, 45, 49, 55, 57, 60, 67, 68, Fermi potential, 146
78, 82, 93–95, 97, 100–103, 106, FGMOS transistor, 20–23, 57, 83, 84, 98,
108, 109, 121, 123, 124, 135, 144, 205, 208, 213, 215, 216, 241, 242,
145, 148, 150–152, 158–160, 162, 251, 280, 311, 318, 332, 354, 407
Index 445

Fifth-order H
approximation, 380–384, 419–427 Harmonic distortions, 63, 65, 66, 69, 151,
approximation function, 383–384, 421 153, 155, 346
derivate, 277, 279
distortions, 66
term, 65, 66, 277, 280 I
First-order Identical MOS transistors, 10, 232, 233,
analysis, 22, 348 252, 257
derivate, 5, 268, 269, 274 Implementation
model, 431, 435 computational circuits, 171, 432
term, 6, 64 silicon area, ix, 427
Flipped voltage follower, 105 Input current, ix, 11, 13, 15, 89, 92, 164, 165,
Floating gate 180–182, 185, 195, 225–226, 236,
arithmetical mean of input 238, 240, 241, 243, 246, 250–251,
potentials, 37 253, 254, 258, 262, 263, 280, 288,
capacitive coupling, 20, 21 296, 309–310, 312–322, 351, 355,
MOS transistors, 20 368–370, 374, 377, 424, 425
Folded multiplier, 134–135 sources, 13, 92
Folded structure, 132 Input-output connections, 323–325, 365, 392
Four-quadrant multiplier, 110, 141, Input-output cross-connections, 325, 328, 329,
175, 177 340, 365, 392
Fourth-order Input variable, viii, ix, 89, 181–182, 246, 374
approximation, 274, 277, 278, 303, 304, Input voltage, 1, 89, 188, 262, 309, 325, 365
306, 437 sources, 54
approximation function, 278 Integrated circuit
derivate, 273, 276 current mirrors, 31, 156, 192, 210, 241,
term, 273, 274, 378, 380 285, 319, 329, 336, 370, 434
Frequency behavior, 264 frequency response, vii, ix, 147, 167, 182, 246
Frequency response, vii–ix, 147, 164, 182,
246, 255, 306, 354
Functional basis, 1, 93, 139, 246 J
Functional core Junction leakage, 434
computational circuits, 422, 427
differential amplifiers, 422
multifunctional circuits, 422 L
squaring circuits, viii, 422 Layout, 433
Functionality, vii, ix, 1, 4, 85, 93, Limited Taylor series expansion, 68,
96, 100, 139, 181, 246, 267–269, 271, 273, 274, 277,
422, 427 280, 290, 295, 306, 374, 376–377
Functional relations, viii, 93, 96 Linear circuits, 64–68, 153, 335
Fundamental Linearity
block, ix, 4 error, 85, 93, 332, 333, 425
structure, viii superior-order terms, 61, 136, 412
Taylor series, 66, 68, 290, 378
total harmonic distortions, 65, 69, 346
G Linearization techniques
Gate leakage, 434 active resistor circuits, 323, 324, 327, 341
Gate oxide thickness, 433 differential amplifier, vii, 30, 62, 66, 130,
Gate-source voltage 323, 341, 352–353
nonlinear characteristic, 160, 385 multiplier circuits, vii, 130–132, 136, 154
temperature dependence, 435 Linearly dependent, 2, 6, 30, 39, 113, 115,
Gilbert cell, 151 217, 232, 240, 346
446 Index

Linear transfer characteristic, 8, 16, 22, 28, 38, linear region, 150, 356
41, 42, 53, 55, 57, 61, 82, 127, 136, mobility, 20–21
327, 338, 341, 346, 348, 412–413 mobility degradation, 431
Low-power, vii, viii, 66, 171, 182 NMOS transistor, 47, 435
designs, 66 PMOS transistor, 75, 435
operation, viii saturation, viii, ix, 8, 10, 23, 39–41, 54,
Low-voltage, 132 61, 78, 89, 96, 102, 103, 105, 108,
operation, 132 113, 115, 121, 123, 124, 128, 142,
144, 147, 151, 165, 168, 179, 182,
191, 195, 202, 224, 231–233, 236,
M 241, 251, 252, 257, 260, 263, 280,
Mathematical analysis, 1–4, 89–93, 185–188, 286, 288, 289, 295, 306, 313, 315,
249–250, 267–280, 309–311, 318, 324, 326, 327, 334, 343, 346,
323–324, 363–384 354, 356, 358, 368, 385, 391–392,
Maximal range 410, 412, 431, 432
of common-mode input voltage, 69–71, 73, 79 second-order effects, 431–433
of differential input voltage, 69–73 short-channel effect, 434
extended range, 79, 254, 424, 425 strong inversion, 433
Maximum circuit, 69, 76, 77, 79 subthreshold operation, vii–ix, 171,
Method, 3, 8, 9, 20, 22, 32, 48, 50, 61, 64, 69, 175, 182
78, 85, 112, 113, 115, 130, 132, 136, transconductance, 20, 23, 41, 42, 45,
139, 157, 158, 188, 190, 222, 262, 46, 57, 69, 71–73, 75, 77, 78,
284, 323, 324, 326, 338, 346, 353, 346, 431, 435
354, 366–369, 372–374, 378, 380, weak inversion, 66, 92, 171, 174–177,
412, 414, 427 187, 237, 238, 289, 306, 319, 433
Mirroring Multifunctional circuit, 363, 371, 399,
current mirrors, 31, 50, 107, 123, 134, 156, 415–427
192, 197, 210, 241, 242, 253, 285, Multifunctional computational structure, viii
291, 318, 319, 325, 329, 336, 357, Multifunctional core, 363–366, 368, 371, 372,
369, 370, 375, 434 385–390, 392–395, 397, 398, 400,
mirroring the Ohm law, 324, 352, 354 402–407, 409, 410, 427
Mismatch, 434 Multiple current mirrors, 192, 242, 318, 336,
Mixed-signal integrated circuits, viii 346, 375
Mobility degradation, 431 Multiplication circuit, 110, 151, 367
Modeling Multiplier/divider circuit
active devices, 1 four-quadrant, 110, 141, 175, 177
large signal model, 4 two-quadrant, 177
MOS transistor, 89, 144, 146, 187, 431–434 Multiplying function, 62, 89, 92, 100, 102, 103,
small signal model, 1, 146, 387, 390, 433 106, 121, 122, 139, 140, 144, 151,
technological parameters, 25, 66, 170, 158, 177, 180, 353, 372, 373, 414
180, 228, 229, 243, 375, 390
MOS
differential amplifier, 4, 188 N
model N-channel MOS transistor, 20
gate oxide capacitance, 20–21, 433 Negative equivalent resistance, 62, 112, 325,
mobility, 20, 431 328, 330, 332, 333, 340, 345, 349,
threshold voltage, 45, 46, 145, 146, 191, 354, 360, 365, 366, 387, 388, 392,
332, 431–435 393, 400, 401, 414, 415
transconductance parameter, 20–21, NMOS transistor, 47, 71, 435
431, 435–436 Nonlinear behavior, 4, 61
transistor Nonlinear circuits
bulk effect, 41, 145, 327, 431–434 Euclidean distance circuits, vii
channel-length modulation, 431, 434, 436 exponential circuits, viii
Index 447

polynomial functions, 268, 270 PMOS transistor, 435

square-root circuits, viii, 346 Polynomial series expansion
squaring circuits, viii approximation error, 268, 375
Nonlinear dependence, 91, 136, 160, 412 continuous mathematical function,
Nonlinearity, vii–ix, 4–6, 64, 65, 154, 159, 374–384, 415–427
346, 385, 427 distortions, 1, 4, 61–66, 68, 69, 136,
cancellation, 65, 91, 160 151, 153, 155, 346, 372, 412,
Nonlinear term 433, 434
distortions, 4, 61, 64, 65, 136, 154–155, superior-order approximation,
346, 412 374–376
polynomial series expansion, 375 Positive equivalent resistance, 325, 328–331,
superior-order distortions, 61, 136, 412 334–337, 339–344, 346–348, 350,
Taylor series expansion, 5–6 351, 353, 355–359, 365, 387, 393,
401, 413, 414
Potential, 1, 10, 11, 18, 24, 27, 32, 37,
O 45, 51, 52, 54, 55, 57, 62, 82,
Odd-order distortions, 66, 68, 154–155, 433 83, 89, 94, 97, 102, 103, 106,
Odd-order terms, 63–66, 154, 268, 269, 271, 107, 126, 128, 137, 146, 151,
277, 280, 288–290, 433 180, 185, 200, 205, 206, 208,
Offset voltage, 83, 85 211, 213, 214, 217, 218, 238,
Ohm law, 324, 352, 354 240, 243, 250, 257, 262, 281,
Operational amplifier 285, 323, 329, 331, 332, 342,
transconductance, 22, 23, 44, 50, 69, 77–79, 343, 357, 367, 368, 398, 399,
346, 364, 365, 435 404, 407, 434
voltage gain, 6, 64, 67 Power consumption, vii, viii,
Opposite-excited differential structures, 433 182, 427
Output current, 1, 89, 185, 249, 281, 311, Power supply rejection ratio, 436
324, 363 Primitive function, 378–384, 417–427
Output differential current, 5, 10, 11, 13–19, Principle, 1, 89, 185, 249, 267, 323, 363
25, 26, 29, 33, 37, 40–42, 44, 45, diagram, 48
48–50, 52, 58, 60, 61, 63–65, 68, of operation, 10, 40, 44, 48, 50, 179,
79, 81, 83, 84, 96, 98, 99, 105, 181, 231, 364–373
107–110, 112, 114, 115, 124, Product
130–132, 136, 143–145, 147, of input currents, 89, 92, 164, 181, 251,
149, 160–162, 164, 178, 210, 253, 354
211, 219, 220, 229, 250, of input voltages, 89, 90, 93, 95, 96,
257–260, 311, 324, 326, 386, 100, 112, 145, 146, 150, 161,
392, 412, 434, 435 389, 390, 394
Output differential voltage, 69, 89, 113, 136
Output resistance, 323–329, 332, 340, 346,
348, 349, 355, 365, 366, 392 Q
Output voltage, 9, 69, 135, 312 Quadratic law, 61, 145
Quadratic term, 121–122, 290, 372, 373

P
Pair R
differential input voltage, 15, 49, 102, 110, Rail-to-rail operation, 3, 69, 77, 78, 85
135, 329 Reference current, 27, 89, 179,
differential pair, 68, 71, 105, 110 185, 195, 226, 229, 238,
MOS transistors, 66, 102, 105, 150, 179 280, 288, 315, 324,
Parallel-connected 352–355, 360, 370, 372,
differential amplifier, 19, 32, 71, 122, 329 374, 377
multiplier circuit, 122 Reference voltage, 28, 324, 352–355
448 Index

S Squaring function, 34, 121, 187, 189, 203, 226,

Saturation limit, 286 231, 238, 240, 241, 257, 285, 318,
Saturation region, vii–ix, 4, 20–21, 23, 54, 61, 369, 373, 433
78, 89, 96–97, 103, 105, 108–109, Stacked architecture, 132
115, 124, 128, 147, 182, 191, 236, Stacked stage, 189
241, 246, 255, 260, 286, 288, 289, Substrate, 433
306, 343, 346, 351, 356, 385, Subthreshold current, 171, 175, 241, 433
391–392, 412, 432 Subthreshold leakage, 433
Schematic, 241 Subthreshold-off current, 434
Second-order Subthreshold operation, viii, 171, 175, 182
analysis, 432 Superior-order
approximation, 270, 377 distortion, 4, 61, 62, 136, 412
approximation function, 268, 270, 284, 297, term, 61, 136, 412
300, 376–377, 415–416 Supply voltage
derivate, 268, 269, 275 power supply rejection ratio, 436
effects utilization efficiency, 85
bulk effect, 431–434 Symbolic representation
channel-length modulation, 134, 431, computational circuit, 314–315
436 functional block, viii, ix, 112
mobility degradation, 431 Symmetrical structure, 59, 93, 108, 122,
term, 121 137, 150, 207, 214, 216, 347,
Self-biased 350, 385
circuit, 120 Symmetry, 23, 58, 63, 147, 222, 347, 350, 385
current source, 436 Synthesis
differential amplifier, 120, 122 analog signal processing circuits, vii
voltage source, 120, 122–123 computational structures, vii–ix
Series-connection, 45, 46, 50, 332, 337 VLSI designs, viii–ix
Short-channel effects, 434
Signal processing
analog designs, 82, 139, 246, 264, 387, T
390, 427 Taylor series expansion
digital designs, vii approximation error, 268, 291, 375, 378
Silicon area, viii, ix, 350, 354, 360, 427, 446 linearity evaluation, 66, 68
Simulation, 6, 7, 62, 72–74, 112, 254, 255, superior-order derivates, 5, 268–274, 277
332, 333, 357, 360, 423–427 superior-order terms, 268, 269, 306, 376
Speed, vii Technological errors, 169, 170, 180, 244, 436
Square-law Technological parameters, 25, 170, 180, 228,
MOS transistor model, 433 229, 243, 375, 390
saturation region, 431, 432 Technology, 171, 181, 226, 241, 246, 269, 285,
Square-root circuits 306, 322, 360, 410
approximation error, vii Temperature dependence
MOS transistors, 10, 23, 124, 251, 252, 255, output current, 25, 434, 435
257, 260, 262, 263, 346 output voltage, 25, 435
saturation, 8, 10, 21, 23, 251, 252, 255, 257, technological parameters, 25
260, 263, 346, 351 THD, 63, 65, 66, 69, 151, 153, 155
Square-root dependence, 11, 78, 121, 123, Theoretical estimated results, 254, 255,
195, 254, 258, 263, 348, 368, 423, 426, 427
369, 410 Thermal voltage
Square-root function, 15, 241, 254, 285, 368 linear temperature variation, 433
Squaring circuits, 63, 107, 185, 258, 269, 311, temperature dependence, 433–434
350, 366 Third-order
Squaring dependence, 13, 15, 18, 19, 21, 108, approximation, 272, 285–287, 289, 291,
124, 148, 160, 189, 245 378, 380, 418, 437
Index 449

approximation function, 268, 269, 271, Translinear circuits

273, 284, 286, 288, 291, 301, 302, CMOS circuits, viii, 432
377–379, 416–419, 437 computational structures, viii–ix, 181
derivate, 268, 269, 271, 275 Translinear loop, 11, 13, 17, 35, 42, 51,
distortions, 65, 68, 155, 433 52, 69, 77, 78, 92, 167–169,
term, 63, 64, 154, 268, 269, 271, 174, 177–180, 199, 203,
288–290, 433 220, 224–226, 230–235, 237,
Threshold voltage, 21, 25, 30, 33, 45, 46, 50, 244, 252–253, 255, 258, 260,
145, 146, 181, 191, 332, 337, 338, 261, 288, 295, 312, 313,
344, 431, 434, 435 319, 421
Transconductance Tunneling current, 434
amplifier, 22, 23, 25, 27, 28, 30–33, 37, Two-quadrant multiplier, 177
42, 44, 46, 50, 51, 62, 69, 71, 73,
75, 78–80, 112, 129, 325, 327,
344, 346, 348, 364, 392, 400, U
413, 435 Unbalanced differential amplifier, 188
MOS transistor, 20, 23, 41–46, 62, 69,
72–75, 77, 78, 346, 431, 435
Transfer characteristic, 3, 6–8, 11, 16, 22, V
23, 28, 34, 38–42, 53, 55, 57, 59, Vector summation, vii
61, 64–66, 72–75, 82, 113, 127, VLSI circuits, viii, 130, 246, 306,
136, 190, 323, 326, 327, 338, 360, 392
341, 346, 348, 352, 412–413, 433 Voltage
Transistor divider, 180
MOS transistor, vii–ix, 8, 10, 20, 23, 39–42, gain, 6, 64, 67, 73–75, 431
45–47, 54, 61, 66, 67, 78, 84, 89, 92, multiplier, viii
96, 102, 103, 105, 113, 115, 121, shifting, 1, 89, 107, 185, 209
123, 124, 128, 142, 144–147, 150, squarer, 112, 113, 158, 185, 207, 216
151, 157, 165, 168, 171, 174–176, Voltage amplifier
179, 182, 187, 188, 191, 195, 202, differential, 346
218, 222, 224, 229, 231–234, transconductance, 37, 50, 51
236–238, 241, 251, 252, 257, 260, Voltage-controlled amplifiers, 42
262–264, 280, 286, 288, 289, 295, Voltage-input variable, 182, 246
306, 313, 314, 318, 319, 324, 326, Voltage-mode operation, 354
327, 332, 334, 343, 346, 347, 354,
356, 358, 368, 385, 391–392, 410,
412, 421, 431–436 W
Translation blocks Weak inversion, viii–ix, 66, 92, 171,
active resistor circuits, 342–344 172, 174–178, 187, 237, 238,
differential amplifiers, 52, 126, 129, 344 254, 283, 286, 289, 298, 299,
multiplier circuits, 126, 128, 129 306, 319, 433