ĐẠI HỌC QUỐC GIA TP.
HỒ CHÍ MINH
TRƯỜNG ĐẠI HỌC BÁCH KHOA
KHOA ĐIỆN-ĐIỆN TỬ
BỘ MÔN KỸ THUẬT ĐIỆN TỬ
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ASIC AND IP CORE DESIGN
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Chapter 0: Course Introduction
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Course Information
• Instructor
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– Truong Quang Vinh, Ph.D.
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– Department of Electronics
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http://www.dee.hcmut.edu.vn/vn/bomon/bmdientu
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– Email: [email protected]
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– Homepage: http://www4.hcmut.edu.vn/~tqvinh
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– Office: 116B1, IC Design Lab, Monday 9-11am
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Textbooks
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1. Wayne Wolf, Modern VLSI Design – IP-Based Design, Prentice-Hall, 4
edition, 2008
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2. Michael Smith, Application-Specific Integrated Circuits, Addison Wesley,
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1997
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3. Razak Hossain, High Performance ASIC Design, Cambridge, 2008.
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4. Mead C. and Conway L., Introduction to VLSI Systems, Addison Wiley, 2005.
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5. Neil Weste and David Harris, CMOS VLSI Design A Circuits and Systems
Perspective, Addison Wesley, 2010
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Course Description
• Provide students general and detail knowledge of chip
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design on ASIC and FPGA
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• Master the Verilog (or VHDL) language for hardware
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programming
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• Master the necessary tools for ASIC chip design
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Course Outcomes
• Skills to use the Synopsys tools for simulation, verification and
layout design.
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• Skills to design a IC with Verilog language from a defined
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specifications.
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• Skills to design and optimize architecture of the design
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• Skills to use the Modelsim (VCS or NCSim) for IC verification.
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• Skills to write the scripts to automate the testbench (testcase)
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during the verification process.
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• Skills to check, compile & synthesize the IC design toward ASIC
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technology (Leda, Compiler).
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• Skills to verify the timing constraint during IC physical design
(PrimeTime).
• Skills to verify the layout with tools: Hercule & Astro.
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Syllabus
Chapter Content Hours
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1 Introduction: ASIC chip design & IP design 3
1.1 ASIC and FPGA-based chip design flow
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1.2 IP design
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1.3 ASIC chip: analog versus digital
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2 IC Fabrication 6
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2.1 Fabrication process
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2.2 Transistors
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2.3 Layout and design tools
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3 Architecture design 6
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3.1 Design Entry
3.2 Design Constraints
3.3 Hardware Description Language
3.3 Design Synthesis
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Syllabus
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Chapter Content Hours
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4 Verification process 6
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4.1 Test environment
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4.2 Testbench
4.3 Formal verification
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4.4 Boundary-scan test
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5 Physical design 6
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5.1 System partitioning
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5.2 Floorplanning and placement
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5.3 Routing
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Grading
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• Assignment: 20%
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• Final exam: 50%
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• Project: 30%
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– 1 - 2 students for one group
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– Select project’s topic at week 1-2
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– Submit project at week 13
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Schedule
Week Lecture Week Lecture
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1 Chapter 0 10 Chapter 4
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2 Chapter 1 11 Chapter 5
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3 Chapter 2 12 Chapter 5
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4 Chapter 2 13 Present project
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5 Chapter 3 14 Present project
6 Chapter 3
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7 Chapter 4 16 Present project
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8 Midterm 17 Extra
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9 Midterm 18-19 Final exam
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Course Preparation
• Textbooks:
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– download at least 3 required textbooks
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• Software tools:
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– ModelSim, Quartus II
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– Synopsys
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– Virtuoso
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• Programming knowledge:
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– VHDL/Verilog
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Project’s Topics
1. Viterbi decoder
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2. Color correction IP core
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3. Color interpolation IP core
4. Edge detection using Prewitt and Sobel operator
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5. SDR SDRAM controller
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6. DDR SDRAM controller
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7. AHB interface
8. AES encryption
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9. DES encryption
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10. DCT transform
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11. Wavelet transform
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12. Contourlet transform
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Project’s requirements
• Report in MS Word
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• Simulate the design in Modelsim or VCS
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• Verify the design on FPGA
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– Altera DE2 kit
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• Synthesize by Synopsys tool ng
• Present the design in class (option, bonus score)
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