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 CISC RISC

1. Complex instructions, taking multiple clock Simple instructions, taking single clock
2. Emphasis on hardware, complexity is in the 2. Emphasis on software, complexity is in the
micro-program/processor complier
3. Complex instructions, instructions executed by 3. Reduced instructions, instructions executed by
micro-program/processor hardware

4. Variable format instructions, single register set Fixed format Instructions, multiple register sets
and many instructions and few Instructions

5. Many instructions and many addressing modes Fixed instructions and few addressing modes
6. Conditional jump is usually based on status6. Conditional jump can be based on a bit
register bit anywhere in memory
7. Memory reference Is embedded in many Memory reference Is embedded In

Instructions LOADSTORE Instructions

The RISC philosophy is Implemented with four major design rules:

1. Instructions-RISC processors have a reduced number of instruction classes. These classes
provide simple operations that can each execute in a single cycle. The compiler or programmer
synthesizes complicated operations (for example, a divide operation) by combining several
simple Instructions. Each Instruction is having fixed length to allow the pipeline to fetch future
Instructions before decoding the current instruction.
O In contrast, n CISC processors the instructions are often of varlable slze and take many
cycles to execute.

Dr. MAHESH PRASANNA K.., VCET, PUTTUR

18CS44
MICROCONTROLLER AND EMBEDDED SYSTEMS
2. PipelinesThe processing of instructions is broken down into smaller units that can be executed
in parallel by pipelines. Ideally the pipeline advances by one step on each cycle for maximum
throughput. Instructions can be decoded in one pipeline stage.
o There Is no need for an nstruction to be executed by a minl-program called microcode as
on CISC processors.

3. RegistersRISC machines have a large general-purpose register set. Any register can contain
either data or an address. Registers act as the fast local memory store for all data processing
operations.
In contrast, CISC processors have dedicated registers for specific purposes.
4. Load-store architecture The processor operates on data held in registers. Separate load and
store Instructlons transfer data between the register bank and external memory. Memory accesses
are costly, so separating memory accesses from data processing provides an advantage because
you can use data items held in the register bank multiple times without needing multiple memory
accesses.

o In contrast, with a CISC design the data processing operations can act on memory
directly.
These design rules allow a RISC processor to be simpler, and thus the core can operate at higher
clock frequencies.
o In contrast, traditional CISC processors are more complex and operate at lower clock
frequencies.

THE ARM DESIGN PHYLOSOPHY:

There are a number of physical features that have driven the ARM processor design.
Portable embedded systems require battery power. The ARM processor has been speclally
designed to be small to reduce power consumption and extend battery operation-essential for
applications such as mobile phones and personal digital assistants (PDAS).
High code density is another major requirement since embedded systems have limited memory
due to cost and/or physical sBze restrictions-useful for applications that have limited on-board
memory, such as mobile phones and mass storage devices.
Embedded systems are price sensitive
o Hence, use slow and low-cost memory devices to get substantial savingsessential for
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 satisfied. This feature improves performance and code density by reducing branch instructions.
Enhanced instructions-The enhanced digital signal processor (DSP) instructions were added to
the standard ARM instruction set to support fast 16x16-bit multiplier operations. These
instructions allowa faster-performing ARMprocessor.
These additional features have made the ARM processor one of the most commonly used 32-bit
embedded processor cores.

EMBEDDED SYSTEM HARDWARE:

Embedded systems can control many different devices, from small sensors found on a production line, to
the real-time control systems used on a NASA space probe. All these devices use a combination of
software and hardware components.
The following Figure shows a typical embedded device based on an ARM core. Each box represents a
feature or function. The lines connecting the boxes are the buses carrying data.
Dr. MAHESH PRASANNA K., VCET, PUTTUR

CS44 MICROCONTROLLER AND EMBEDDED SYSTEMS

ROM
ARM SRAM
processor FLASHROM
Memory controller
DRAM
Interrupt controller External bus
AHB-external bridge
AHB arbiter

|AHB-APB bridge

Ethernet Ethernet
Real-time clock
physical
Countertimers driver
Console Serial UARTS

ARM Controllers Peripherals Bus

Figure: An ARM-based Embedded Device, a Microcontroller

We can separate the device into four main hardware components:
1. The ARM processor controls the embedded device. Different versions of the ARM processor are
available to suit the desired operating characteristics. An ARM processor comprises a core (the
execution engine that processes instructions and manipulates data) plus the surrounding
components (memory and cache) that interface it with a bus.
2. Controllers coordinate important functional blocks of the system. Two commonly found
controllers are interrupt and memory controllers.
3. The peripherals provide all the input-output capability external to the chip and are responsible for
the uniqueness of the embedded device.
4. A bus is used to communicate between different parts of the device.

ARM Bus Technology:

Embedded devices use an on-chip bus that is internal to the chip and that allows different peripheral
devices to be interconnected with an ARM core.
There are two different classes of devices attached to the bus:
1. The ARM processor core is a bus master-a logical device capable of initiating a data transfer
with another device across the same bus.

2. Peripherals tend to be bus slaves -logical devices capable only of responding to a transfer
request from a bus master device.
A bus has two architecture levels:

A physical leve! -covers the electrical characteristics and bus width (16, 32, or 64 bits).
The protocol the logical rules that govern the communication between the processor and a peripheral.
Dr. MAHESH PRASANNA K., VCET, PUTTUR
 O Register rl3 is traditionally used as the stack pointer (sp) and rl4h

stores the head of the stack in the current processor mode. rl5pc
o Register rl4 is called the link register (Ir) and is where the core |cpsr
puts the return address whenever it calls a subroutine.
o Register rl5 is the program counter (pc) and contains the
address of the next instruction to be fetched by the processor.
V In ARM state the registers rO to rl3 are orthogonalany instruction that you can apply to rð you
can equally well apply to any of the other registers.
In addition to the 16 data registers, there are two program status registers: cpsr (current program
status register) and spsr (saved program status register).

CURRENT PROGRAMSTATUS REGISTER:

The ARM core uses the cpsr to monitor and control internal operations. The cpsr is a dedicated 32-bit
register and resides in the register file. The following Figure shows the basic layout of a generic program
status register. Note that the shaded parts are reserved for future expansion.

Flags Status Extension Control

Ficlds
Bit 31 30 29 28 76 5 4

NZcv Z|FT Mode

Function
Condition Interrupt Processor
flags Masks mode
Thumb
state

Figure: AGeneric Program Status Register (psr)

Dr. MAHESH PRASANNA K., VCET, PUTTUR

15

MICROCONTROLLERAND EMBEDDED SYSTEMS

8CS44
The cpsr is divided into four fields, each 8 bits wide: lags, status, extension, and control. In current
designs the extension and status fields are reserved for future use.
The control field contains the processor mode, state, and interrupt mask bits.
The Aags field contains the condition lags.
Some ARM processor cores have extra bits allocated. For example, the J bit, which can be found in the
flags field, is only available on Jazelle-enabled processors, which execute 8-bit instructions.
It is highly probable that future designs will assign extra bits for the monitoring and control of new
features.
Processor Modes:

The processor mode determines which registers are active and the access rights to the cpsr
register itself. Each processor mode is either privileged or non-privileged:
o Aprivileged mode allows full read-write access to the cpsr.
o A non-privileged mode only allows read access to the control field in the cpsr, but still
allows read-write access to the condition flags.
There are seven processor modes in total:
o six privileged modes (abort, fast interrupt request, interrupt request, supervisor, system,
and undefined)
The processor enters abort mode when there is a failed attempt to access
memory.
" Fast interrupt request and interrupt request modes corespond to the two
interrupt levels available on the ARM processor.
Supervisor mode is the mode that the processor is in after reset and is generally
the mode that an operating system kernel operates in.
System mode is a special version of user mode that allows full read-write access
to the cpsr.

Undefined mode is used when the processor encounters an instruction that is

undefined or not supported by the implementation.
 PIPELINEA
A pipeline is the mechanism in a RISC processor, which is used to execute instructions.
VPipeline speeds up execution by fetching the next instructlon while other instructions are being
decoded and executed.

Dr. MAHESH PRASANNA K., VCET, PUTTUR

18CS44 MICROCONTROLLER AND EMBEDDEDSYSTEMS

Fetch Decode)Execute)
Figure: ARM7 Three-stage Pipeline
The above Flgure shows a three-stage pipeline:
o Fetch loads an instruction from memory.
o Decode ldentifies the instruction to be executed.
o Execute processes the instruction and writes the result back to a register.
The following Figure illustrates pipeline using a simple example.

Fetch Decode Execute

Time Cycle 1 ADD

Cycle 2 () sUB ADD

Cycle 3 ) CMP SUB H ADD

Figure: Pipelined Instruction Seguence

The Figure shows a sequence of three instructions being fetched, decoded, and executed by the
processor

o The three Instructions are laced into the plpeline sequentlally.

o In the first cycle, the core fetches the ADD Instruction from memory.

o In the second cycle, the core fetches the SUB instruction and decodes the ADD
Instruction.

o In the third cycle, both the SUB and ADD Instructions are moved along the pipeline. The
ADD instruction is executed, the SUB instruction is decoded, and the CMP Instruction is
fetched.

This procedure is called filling the pipeline.

The pipeline allows the core to execute an instruction every cycle.
o As the plpeline length increases, the amount of work done at each stage is reduced, which allows
the processor to attain a higher operating frequency. This in turn increases the performance
o The increased pipeline length also means increased system latency and there can be data
dependency between certain stages.

o The pipeline design for each ARM family differs. For example, The ARM9 core Increases the
plpeline length to five stages, as shown in Figure.
Dr. MAHESH PRASANNA K., VCET, PUTTUR

MICROCONTROLLER AND EMBEDDED SYSTEMS