STM32H730AB STM32H730IB

STM32H730VB STM32H730ZB
Arm® Cortex®-M7 32b 550 MHz MCU, 128 KB Flash, 564 KB RAM,
Ethernet, USB, 3xFD-CAN, Graphics, 2x16b ADCs, crypto/hash
Datasheet - production data

Features
FBGA
Includes ST state-of-the-art patented
technology
LQFP100 (14 x 14 mm)
TFBGA100 (8 x 8 mm)
Core LQFP144 (20 x 20 mm)
LQFP176 (24 x 24 mm)
• 32-bit Arm® Cortex®-M7 CPU with DP-FPU, L1
cache: 32-Kbyte data cache and 32-Kbyte FBGA

instruction cache allowing 0-wait state

execution from embedded Flash memory and
external memories, frequency up to 550 MHz,
UFBGA144 (7 x 7 mm)
MPU, 1177 DMIPS/2.14 DMIPS/MHz UFBGA 169 (7 x 7 mm)
(Dhrystone 2.1), and DSP instructions UFBGA 176+25 (10 x 10 mm)

Memories
• 128 Kbytes of embedded Flash memory with Clock, reset and supply management
ECC
• 1.62 V to 3.6 V application supply and I/O
• SRAM: total 564 Kbytes all with ECC, including
128 Kbytes of data TCM RAM for critical real- • POR, PDR, PVD and BOR
time data + 432 Kbytes of system RAM (up to • Dedicated USB power
256 Kbytes can remap on instruction TCM • Embedded DCDC and LDO regulator
RAM for critical real time instructions) +
4 Kbytes of backup SRAM (available in the • Internal oscillators: 64 MHz HSI, 48 MHz
lowest-power modes) HSI48, 4 MHz CSI, 32 kHz LSI

• Flexible external memory controller with up to • External oscillators: 4-50 MHz HSE,
24-bit data bus: SRAM, PSRAM, 32.768 kHz LSE
SDRAM/LPSDR SDRAM, NOR/NAND
memories Low power
• 2 x Octo-SPI interface with XiP and on-the-fly • Sleep, Stop and Standby modes
decryption support • VBAT supply for RTC, 32×32-bit backup
• 2 x SD/SDIO/MMC interface registers
• Bootloader with security services support (SFI Analog
and SB-SFU)
• 2×16-bit ADC, up to 3.6 MSPS in 16-bit: up to
Graphics 22 channels and 7.2 MSPS in double-
interleaved mode
• Chrom-ART Accelerator graphical hardware
accelerator enabling enhanced graphical user • 1 x 12-bit ADC, up to 5 MSPS in 12-bit, up to 12
interface to reduce CPU load channels
• LCD-TFT controller supporting up to XGA • 2 x comparators
resolution • 2 x operational amplifier GBW = 8 MHz

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 STM32H730xB

• 2× 12-bit D/A converters DMA, on-chip FS PHY and ULPI for external
HS PHY
Digital filters for sigma delta modulator • SWPMI single-wire protocol master I/F
(DFSDM)
• MDIO slave interface
• 8 channels/4 filters
Mathematical acceleration
4 DMA controllers to offload the CPU
• CORDIC for trigonometric functions
• 1 × MDMA with linked list support acceleration
• 2 × dual-port DMAs with FIFO • FMAC: Filter mathematical accelerator
• 1 × basic DMA with request router capabilities
Digital temperature sensor
24 timers
Cryptographic/HASH acceleration
• Seventeen 16-bit (including 5 x low power
16-bit timer available in stop mode) and four • AES 128, 192, 256, TDES, HASH (MD5, SHA-
32-bit timers, each with up to 4 IC/OC/PWM or 1, SHA-2), HMAC
pulse counter and quadrature (incremental) • 2x OTFDEC AES-128 in CTR mode for Octo-
encoder input SPI memory encryption/decryption
• 2x watchdogs, 1x SysTick timer
True random number generator
Debug mode
CRC calculation unit
• SWD and JTAG interfaces
• 2-Kbyte embedded trace buffer RTC with sub-second accuracy and
hardware calendar
Up to 128 I/O ports with interrupt
capability ROP, PC-ROP, tamper detection, secure
firmware upgrade support
Up to 35 communication interfaces
• Up to 5 × I2C FM+ interfaces 96-bit unique ID
(SMBus/PMBus™)
All packages are ECOPACK2 compliant
• Up to 5 USARTs/5 UARTs (ISO7816 interface,
LIN, IrDA, modem control) and 1 x LPUART
• Up to 6 SPIs with 4 with muxed duplex I2S for
audio class accuracy via internal audio PLL or
external clock and up to 5 x SPI (from 5 x
USART when configured in synchronous
mode)
• 2x SAI (serial audio interface)
• 1× FD/TT-CAN and 2x FD-CAN
• 8- to 14-bit camera interface
• 16-bit parallel slave synchronous interface
• SPDIF-IN interface
• HDMI-CEC
• Ethernet MAC interface with DMA controller
• USB 2.0 high-speed/full-speed
device/host/OTG controller with dedicated

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Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1 Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.1 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.2 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Error code correction (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

3.4 Secure access mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.5 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.6 CORDIC co-processor (CORDIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
CORDIC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

3.7 Filter mathematical accelerator (FMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . 26

FMAC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

3.8 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.8.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.8.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.8.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.9 Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.10 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.10.1 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.10.2 System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.11 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.12 Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.13 DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.14 Chrom-ART Accelerator (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.15 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 34
3.16 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 34
3.17 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 34
3.18 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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3.19 Octo-SPI memory interface (OCTOSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.20 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.21 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.22 Digital temperature sensor (DTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.23 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.24 Digital-to-analog converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.25 Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.26 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.27 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 39
3.28 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.29 PSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.30 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.31 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.32 Cryptographic acceleration (CRYP and HASH) . . . . . . . . . . . . . . . . . . . . 42
3.33 On-the-fly decryption engine (OTFDEC) . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.34 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.34.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.34.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.34.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.34.4 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . 47
3.34.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.34.6 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.34.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.35 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 48
3.36 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.37 Universal synchronous/asynchronous receiver transmitter (USART) . . . 49
3.38 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 50
3.39 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 51
3.40 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.41 SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.42 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 52
3.43 Management data input/output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . . 53
3.44 SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . . . 53
3.45 Controller area network (FDCAN1, FDCAN2, FDCAN3) . . . . . . . . . . . . . 53

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3.46 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 54

3.47 Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . . 54
3.48 High-definition multimedia interface (HDMI)
- consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.49 Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5 Pinouts, pin descriptions and alternate functions . . . . . . . . . . . . . . . . 57

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3.2 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.3.3 SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.3.4 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 114
6.3.5 Embedded reset and power control block characteristics . . . . . . . . . . 115
6.3.6 Embedded reference voltage characteristics . . . . . . . . . . . . . . . . . . . . 116
6.3.7 Embedded USB regulator characteristics . . . . . . . . . . . . . . . . . . . . . . 117
6.3.8 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Typical and maximum current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Typical SMPS efficiency versus load current and temperature . . . . . . . . . . . . .125
I/O system current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
On-chip peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
6.3.9 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 135
6.3.10 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 136
High-speed external user clock generated from an external source . . . . . . . . .136
Low-speed external user clock generated from an external source . . . . . . . . . .137
High-speed external clock generated from a crystal/ceramic resonator. . . . . . .138

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Low-speed external clock generated from a crystal/ceramic resonator . . . . . . .139

6.3.11 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 140
48 MHz high-speed internal RC oscillator (HSI48) . . . . . . . . . . . . . . . . . . . . . . .140
64 MHz high-speed internal RC oscillator (HSI) . . . . . . . . . . . . . . . . . . . . . . . . .141
4 MHz low-power internal RC oscillator (CSI) . . . . . . . . . . . . . . . . . . . . . . . . . .142
Low-speed internal (LSI) RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
6.3.12 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
6.3.13 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
6.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . . . . . . . .148
Designing hardened software to avoid noise problems . . . . . . . . . . . . . . . . . . .148
Electromagnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
6.3.15 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 150
Electrostatic discharge (ESD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
Static latchup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
6.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Functional susceptibility to I/O current injection . . . . . . . . . . . . . . . . . . . . . . . . .151
6.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
General input/output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
Output voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
Output buffer timing characteristics (HSLV option disabled) . . . . . . . . . . . . . . .156
Output buffer timing characteristics (HSLV option enabled). . . . . . . . . . . . . . . .158
Analog switch between ports Pxy_C and Pxy . . . . . . . . . . . . . . . . . . . . . . . . . .159
6.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
6.3.19 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Asynchronous waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
Synchronous waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
NAND controller waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
SDRAM waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
6.3.20 Octo-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.3.21 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
6.3.22 16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
General PCB design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
6.3.23 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
6.3.24 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
6.3.25 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 206
6.3.26 Analog temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . 207
6.3.27 Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . 208

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6.3.28 Temperature and VBAT monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

6.3.29 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
6.3.30 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
6.3.31 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 210
6.3.32 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 213
6.3.33 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 215
6.3.34 Parallel synchronous slave interface (PSSI) characteristics . . . . . . . . 216
6.3.35 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 217
6.3.36 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
6.3.37 Low-power timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
6.3.38 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
USART interface characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
I2S Interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
MDIO characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
SD/SDIO MMC card host interface (SDMMC) characteristics . . . . . . . . . . . . . .231
USB OTG_FS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
USB OTG_HS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234
Ethernet interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

7.1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Device marking for LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244

7.2 TFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Device marking for TFBGA100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247

7.3 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Device marking for LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251

7.4 UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Device marking for UFBGA144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254

7.5 UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Device marking for UFBGA169 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257

7.6 LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Device marking for LQFP176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261

7.7 UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Device marking for UFBGA176+25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264

DS13315 Rev 3 7/270

8
Contents STM32H730xB

7.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

7.8.1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

8/270 DS13315 Rev 3

STM32H730xB List of tables

List of tables

Table 1. STM32H730xB features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 2. System versus domain low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 3. DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 4. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 5. USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 6. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 7. STM32H730xB pin and ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 8. STM32H730xB pin alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 9. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 10. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 11. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 12. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 13. Supply voltage and maximum temperature configuration. . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 14. VCAP operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 15. Characteristics of SMPS step-down converter external components . . . . . . . . . . . . . . . . 111
Table 16. SMPS step-down converter characteristics for external usage . . . . . . . . . . . . . . . . . . . . 111
Table 17. Inrush current and inrush electric charge characteristics for LDO and SMPS . . . . . . . . . 112
Table 18. Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 19. Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 20. Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 21. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 22. USB regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 23. Typical and maximum current consumption in Run mode,
code with data processing running from ITCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 24. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 25. Typical and maximum current consumption in Run mode,
code with data processing running from Flash memory, cache OFF. . . . . . . . . . . . . . . . 121
Table 26. Typical consumption in Run mode and corresponding performance
versus code position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 27. Typical current consumption in Autonomous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 28. Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . 122
Table 29. Typical and maximum current consumption in System Stop mode . . . . . . . . . . . . . . . . . 123
Table 30. Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . 124
Table 31. Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 124
Table 32. Peripheral current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 33. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 34. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 35. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 36. 4-50 MHz HSE oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 37. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 38. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 39. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 40. CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 41. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 42. PLL1 characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 43. PLL1 characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 44. PLL2 and PLL3 characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . 145

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11
List of tables STM32H730xB

Table 45. PLL2 and PLL3 characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . 146
Table 46. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 47. Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 48. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 49. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 50. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 51. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 52. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 53. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 54. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 55. Output voltage characteristics for all I/Os except PC13, PC14 and PC15 . . . . . . . . . . . . 154
Table 56. Output voltage characteristics for PC13, PC14 and PC15 . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 57. Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 58. Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 59. Pxy_C and Pxy analog switch characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 60. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 61. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 162
Table 62. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 162
Table 63. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 164
Table 64. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 164
Table 65. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 66. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 166
Table 67. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 68. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 167
Table 69. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 70. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 71. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 72. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 73. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 74. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 75. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 76. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 77. SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 78. LPSDR SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 79. OCTOSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 80. OCTOSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 81. OCTOSPI characteristics in DTR mode (with DQS)/Octal and Hyperbus . . . . . . . . . . . . 185
Table 82. Delay Block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 83. 16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 84. Minimum sampling time vs RAIN (16-bit ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 85. 16-bit ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 86. 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 87. Minimum sampling time vs RAIN (12-bit ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 88. 12-bit ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 89. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 90. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 91. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 92. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 93. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 94. Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 95. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 96. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

10/270 DS13315 Rev 3

STM32H730xB List of tables

Table 97. Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Table 98. Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 99. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 100. Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 101. DFSDM measured timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 102. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 103. PSSI transmit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 104. PSSI receive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 105. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 106. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 107. LPTIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 108. Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 109. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 110. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 111. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 112. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 113. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 114. MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 115. Dynamics characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V . . . . . . . . . . . . 231
Table 116. Dynamics characteristics: eMMC characteristics VDD = 1.71V to 1.9V . . . . . . . . . . . . . . 232
Table 117. USB OTG_FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 118. Dynamics characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 119. Dynamics characteristics: Ethernet MAC signals for SMI . . . . . . . . . . . . . . . . . . . . . . . . 235
Table 120. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 236
Table 121. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 237
Table 122. Dynamics JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 123. Dynamics SWD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 124. LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 125. TFBGA100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Table 126. TFBGA100 - Recommended PCB design rules (0.8 mm pitch BGA) . . . . . . . . . . . . . . . . 247
Table 127. LQFP144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Table 128. UFBGA144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Table 129. UFBGA144 - Recommended PCB design rules (0.50 mm pitch BGA). . . . . . . . . . . . . . . 253
Table 130. UFBGA169 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Table 131. UFBGA169 - Recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . 256
Table 132. LQFP176 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Table 133. UFBGA176+25 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Table 134. UFBGA176+25 - Recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . 263
Table 135. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Table 136. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

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List of figures STM32H730xB

List of figures

Figure 1. STM32H730xB block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 2. Power-up/power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 3. STM32H730xB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 4. TFBGA100 pinout (without SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 5. LQFP100 pinout (without SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 6. TFBGA144 ballout (without SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 7. LQFP144 pinout (without SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 8. LQFP176 pinout (with SMPS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 9. UFBGA169 ballout (with SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 10. UFBGA176+25 ballout (with SMPS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 11. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 12. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 13. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 14. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 15. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 16. External components for SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 17. Typical SMPS efficiency (%) vs load current (A) in Run mode at TJ = 30 °C. . . . . . . . . . 125
Figure 18. Typical SMPS efficiency (%) vs load current (A) in Run mode at TJ = TJmax . . . . . . . . . 125
Figure 19. Typical SMPS efficiency (%) vs load current (A) in Stop and
DStop modes at TJ = 30 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 20. Typical SMPS efficiency (%) vs load current (A) in low-power mode at TJ = TJmax . . . 126
Figure 21. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 22. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 23. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 24. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 25. VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 26. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 27. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 161
Figure 28. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 163
Figure 29. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 30. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 31. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 32. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 33. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 34. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 35. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 36. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 177
Figure 37. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 178
Figure 38. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 39. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 40. OCTOSPI SDR read/write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 41. OCTOSPI DTR mode timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 42. OCTOSPI Hyperbus clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 43. OCTOSPI Hyperbus read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 44. OCTOSPI Hyperbus write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 45. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 46. Typical connection diagram when using the ADC with FT/TT pins
featuring analog switch function194

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Figure 47. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 195
Figure 48. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 195
Figure 49. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 50. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 51. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 52. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 53. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 54. USART timing diagram in Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Figure 55. USART timing diagram in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Figure 56. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 57. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 58. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 59. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 60. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 61. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Figure 62. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 63. MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 64. SD high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 65. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 66. SDMMC DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 67. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure 68. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 69. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 70. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 71. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Figure 72. SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Figure 73. LQFP100- Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
LQFP100 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 74. LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Figure 75. TFBGA100 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Figure 76. TFBGA100 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Figure 77. TFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Figure 78. LQFP144 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Figure 79. LQFP144 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Figure 80. LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Figure 81. UFBGA144 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Figure 82. UFBGA144 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Figure 83. UFBGA144 marking example (package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Figure 84. UFBGA169 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Figure 85. UFBGA169 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Figure 86. UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Figure 87. LQFP176 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 88. LQFP176 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Figure 89. LQFP176 marking example (package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Figure 90. UFBGA176+25 - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Figure 91. UFBGA176+25 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Figure 92. UFBGA176+25 marking example (package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

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Introduction STM32H730xB

1 Introduction

This document provides information on STM32H730xB microcontrollers, such as

description, functional overview, pin assignment and definition, packaging, and ordering
information.
This document should be read in conjunction with the STM32H730xB reference manual
(RM0468), available from the STMicroelectronics website www.st.com.
For information on the Arm®(a) Cortex®-M7 core, refer to the Cortex®-M7 Technical
Reference Manual, available from the http://www.arm.com website.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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STM32H730xB Description

2 Description

STM32H730xB devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC
core operating at up to 550 MHz. The Cortex® -M7 core features a floating point unit (FPU)
which supports Arm® double-precision (IEEE 754 compliant) and single-precision data-
processing instructions and data types. The Cortex -M7 core includes 32 Kbytes of
instruction cache and 32 Kbytes of data cache. STM32H730xB devices support a full set of
DSP instructions and a memory protection unit (MPU) to enhance application security.
STM32H730xB devices incorporate high-speed embedded memories with 128 Kbytes of
Flash memory, up to 564 Kbytes of RAM (including 192 Kbytes that can be shared between
ITCM and AXI, plus 64 Kbytes exclusively ITCM, plus 128 Kbytes exclusively AXI,
128 Kbyte DTCM, 48 Kbytes AHB and 4 Kbytes of backup RAM), as well as an extensive
range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit
multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external
memory access. To improve application robustness, all memories feature error code
correction (one error correction, two error detections).
The devices embed peripherals allowing mathematical/arithmetic function acceleration
(CORDIC coprocessor for trigonometric functions and FMAC unit for filter functions). All the
devices offer three ADCs, two DACs, two operational amplifiers, two ultra-low power
comparators, a low-power RTC, 4 general-purpose 32-bit timers, 12 general-purpose 16-bit
timers including two PWM timers for motor control, five low-power timers, a true random
number generator (RNG), and a cryptographic acceleration cell, and a HASH processor.
The devices support four digital filters for external sigma-delta modulators (DFSDM). They
also feature standard and advanced communication interfaces.
• Standard peripherals
– Five I2Cs
– Five USARTs, five UARTs and one LPUART
– Six SPIs, four I2Ss in Half-duplex mode. To achieve audio class accuracy, the I2S
peripherals can be clocked by a dedicated internal audio PLL or by an external
clock to allow synchronization (note that the five USARTs also provide SPI slave
capability).
– Two SAI serial audio interfaces
– One SPDIFRX interface with four inputs
– One SWPMI (Single Wire Protocol Master Interface)
– Management Data Input/Output (MDIO) slaves
– Two SDMMC interfaces
– A USB OTG high-speed interface with full-speed capability (with the ULPI)
– Two FDCANs plus one TT-FDCAN interface
– An Ethernet interface
– Chrom-ART Accelerator
– HDMI-CEC

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56
Description STM32H730xB

• Advanced peripherals including

– A flexible memory control (FMC) interface
– Two Octo-SPI memory interfaces with on-the-fly decryption (OTFDEC)
– A camera interface for CMOS sensors
– An LCD-TFT display controller
Refer to Table 1: STM32H730xB features and peripheral counts for the list of peripherals
available on each part number.
To reduce the power consumption some STM32H730xB devices include an optional step-
down converter that can be used either for internal or external supply, or both.
STM32H730xB devices operate in the –40 to +85 °C ambient temperature range from a
1.62 to 3.6 V power supply. The supply voltage can drop down to 1.62 V by using an
external power supervisor (see Section 3.8.2: Power supply supervisor) and connecting the
PDR_ON pin to VSS. Otherwise the supply voltage must stay above 1.71 V with the
embedded power voltage detector enabled.
Dedicated supply inputs for USB are available to allow a greater power supply choice.
A comprehensive set of power-saving modes allows the design of low-power applications.
STM32H730xB devices are offered in several packages ranging from 100 to 176 pins/balls.
The set of included peripherals changes with the device chosen.
These features make STM32H730xB microcontrollers suitable for a wide range of
applications:
• Motor drive and application control
• Medical equipment
• Industrial applications: PLC, inverters, circuit breakers
• Printers, and scanners
• Alarm systems, video intercom, and HVAC
• Home audio appliances
• Mobile applications, Internet of Things
• Wearable devices: smart watches.
Figure 1 shows the device block diagram.

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Figure 1. STM32H730xB block diagram

D[7:0],DP, DM, STP,
MII / RMII D123DIR, NXT,ULPI:CK
To APB1-2 MDIO
peripherals D0DIR, , D[7:0], DIR,
as AF
CMD, CKas AF ID, VBUS

AHB1 (275MHz)
D-TCM D-TCM
64KB 64KB PHY
I-TCM 64KB
ETHER
Shared AXI
DMA1 DMA2 SDMMC2 OTG_HS
MAC
I-TCM 192KB
AHBP
128 KB AXI
8 Stream 8 Stream DMA/ DMA/
NJTRST, JTDI, SRAM FIFO
Arm CPU FIFOs FIFOs FIFO FIFO
JTCK/SWCLK JTAG/SW AXI/AHB12 (275MHz)
Cortex-M7
JTDO/SWDIO, JTDO AXIM
550 MHz 128KB
TRACECLK ETM FLASH 32-bit AHB BUS-MATRIX
TRACED[3:0] I-Cache D-Cache FMC

AHB1 (275MHz)
32KB 32KB DMA
FMC_signals
AHBS

OCTOSPI1
OTFDEC1
Mux1 SRAM1 SRAM2
OCTOSPI1
16 KB 16 KB

AHB2 (275MHz)
16 Streams signals
MDMA

64-bit AXI BUS-MATRIX

FIFO RNG ADC1

OCTOSPIM
Up to 20 analog inputs Most
HASH are common to ADC1 & 2
CHROM-ART ADC2
FIFO
(DMA2D) 3DES/AES AHB/APB

OCTOSPI2
OTFDEC2
CORDIC
LCD_R[7:0], LCD_G[7:0], LCD-TFT FIFO 32b TIM2 CH[4;1], ETR as AF
APB3 (138MHz)

OCTOSPI2
LCD_B[7:0], LCD_HSYNC,
signals
FMAC
LCD_VSYNC, LCD_DE, LCD_CLK 16b TIM3 CH[4;1], ETR as AF

WWDG 16b TIM4 CH[4;1], ETR as AF

DLYBOS1-2
AHB/APB 32b TIM5 CH[4;1], ETR as AF
DLYBSD1

AHB3
TIM6 32b TIM23 CH[4;1], ETR as AF
16b
D[7:0], D123DIR, D0DIR, 32b TIM24 CH[4;1], ETR as AF
CMD, CKas AF SDMMC1 FIFO AXI/AHB34 (275MHz) TIM7 16b CH[2;1] as AF
16b TIM12
DLYBSD2 AHB2 (275MHz) SWPMI 16b TIM13 CH1 as AF
AHB4

DCMI 16b TIM14 CH1 as AF

HSYNC, VSYNC, PIXCLK, D[13:0]
PDCK, DE, RDY, D[15:0] PSSI AHB/APB USART2 RX, TX, CK, CTS, RTS, DE as AF
USART3 RX, TX, CK, CTS, RTS, DE as AF

UART4 RX, TX, CTS, RTS, DE as AF

CKOUT, DATIN[7:0], CKIN[7:0] DFSDM RX, TX, CTS, RTS, DE as AF
UART5
FIFO

SD_[A;B], SCK_[A;B], FS_[A;B], SAI1 UART7 RX, TX, CTS, RTS, DE as AF

MCLK_[A;B], D[3:1], CK[2:1] as AF
UART8 RX, TX, CTS, RTS, DE as AF
MOSI, MISO, SCK, NSS as AF SPI5 MOSI, MISO, SCK, NSS /
1 compl. chan.(TIM17_CH1N), SPI2/I2S2 SDO, SDI, CK, WS, MCK, as AF
1 chan. (TIM17_CH1, BKIN as AF
TIM17 A P B 10 MHz
SPI3/I2S3 MOSI, MISO, SCK, NSS /
3
1 compl. chan.(TIM16_CH1N), SDO, SDI, CK, WS, MCK, as AF
1 chan. (TIM16_CH1, BKIN as AF TIM16
I2C1/SMBUS SCL, SDA, SMBA as AF
AHB4_MEMD3 (275MHz)
APB2 138 MHz (max)

2 compl. chan.(TIM15_CH1[1:2]N), TIM15

Digital filter
2 chan. (TIM_CH15[1:2], BKIN as AF SCL, SDA, SMBA as AF
I2C2/SMBUS
APB1 138 MHz (max)

MOSI, MISO, SCK, NSS as AF SPI4

MOSI, MISO, SCK, NSS / I2C3/SMBUS SCL, SDA, SMBA as AF
SPI1/I2S1
10 KB SRAM

SDO, SDI, CK, WS, MCK, as AF DMA

AHB4

Mux2 I2C5/SMBUS SCL, SDA, SMBA as AF

AHB4

RX, TX, CTS, RTS, DE as AF UART9

AHB4 DAP USBCR
BDMA
RX, TX, CK, CTS, RTS, DE as AF USART10
MDIOS MDC, MDIO as AF
AHB4

RX, TX, CK, CTS, RTS, DE as AF USART6

32-bit AHB BUS-MATRIX RAM TX, RX, RXFD_MODE,
TT-FDCAN1 TXFD_MODE as AF
RX, TX, CK, CTS, RTS, DE as AF USART1 I/F
FIFO

TX, RX, RXFD_MODE,

FDCAN2
TXFD_MODE as AF
AHB4 (275MHz)

CH[1:4]N, CH[1:4], ETR, BKIN, BKIN2 TIM1/PWM TX, RX, RXFD_MODE,

as AF 16b FDCAN3
TXFD_MODE as AF
HSEM
CH[1:4]N, CH[1:4], ETR, BKIN, BKIN2
TIM8/PWM 16 KB SRAM 4 KB BKP SPDIFRX1 IN[1:4] as AF
as AF 16b CRC RAM
Up to 17 analog inputs HDMI-CEC CEC as AF
Some common to ADC1 and 2 ADC3
DAC OUT1, OUT2 as AF
AHB4

PA..H[15:0] GPIO PORTA.. H

LPTIM1 IN1, IN2, ETR, OUT as AF
16b
PJ,PK[11:0] GPIO PORTJ,K RCC OPAMP1 VINM, VINP, VOUT as AF
Reset &
AHB4 (275MHz)

OPAMP2 VINM, VINP, VOUT as AF

control
@VDD
SD_[A;B], SCK_[A;B], FS_[A;B],
MCLK_[A;B], D[3:1], CK[2:1] as AF
SAI4 VCORE BBgen + POWER MNGT
VDD
PWRCTRL

COMPx_INP, COMPx_INM, COMP1&2 Voltage VSS

COMPx_OUT as AF regulator VCAP, VDDLDO
VDDSMPS, VSSSMPS,
OUT as AF LPTIM5 16b
3.3 to 1.2V VLXSMPS, VFBSMPS
VREF AHB/APB
OUT as AF LPTIM4 VBAT
16b @VSW
SYSCFG
APB4 138 MHz (max)

LPTIM3 XTAL 32 kHz OSC32_IN

OUT as AF 16b OSC32_OUT
EXTI WKUP
LS

RTC
(max)

SCL, SDA, SMBA as AF I2C4

IWDG @VDD
(max)

MOSI, MISO, SCK, NSS / Backup registers TS, TAMP1, TAMP3,

SPI6/I2S6 OUT, REFIN
MHz

SDO, SDI, CK, WS, MCK, as AF AWU

HSI RC
LS

HSI
Temperature
MHz

sensor
138138

RX, TX, CK, CTS, RTS as AF LPUART1 HSI48 HSI48 RC

APB4

LPTIM2 CSI CSI RC

IN1, IN2, ETR, OUT as AF 16b
APB4

@VDD
LSI LSI RC
XTAL OSC OSC_IN
PLL1+PLL2+PLL3 4- 48 MHz OSC_OUT

@VDD
SUPPLY SUPERVISION
POR VDDA, VSSA
reset POR/PDR/BOR NRESET
Int PVD WKUP[1;2;4;6]

MSv65314V2

DS13315 Rev 3 17/270

56
Description STM32H730xB

Table 1. STM32H730xB features and peripheral counts

no SMPS SMPS

STM32H730ABI6Q

STM32H730IBK6Q

STM32H730IBT6Q
STM32H730VBH6
STM32H730VBT6

STM32H730ZBT6

STM32H730ZBI6
Peripherals

Flash memory (Kbytes) 128

SRAM mapped
128
onto AXI bus
SRAM1
16
SRAM (D2 domain)
(Kbytes) SRAM2
16
(D2 domain)
SRAM4
16
(D3 domain)
RAM shared between ITCM
192
and AXI (Kbytes)
ITCM RAM
64
TCM RAM (instruction)
in Kbytes DTCM RAM
128
(data)
Backup SRAM (Kbytes) 4
Interface 1
NOR Flash
memory/RAM - - yes yes yes yes yes
controller
Multiplexed I/O
NOR Flash yes yes yes yes yes yes yes
FMC memory
16-bit NAND
yes yes yes yes yes yes yes
Flash memory
16-bit SDRAM
- - yes yes yes yes yes
controller
24-bit SDRAM
- - - - - yes -
controller(1)
GPIO 80 112 114 121 128 119

18/270 DS13315 Rev 3

STM32H730xB Description

Table 1. STM32H730xB features and peripheral counts (continued)

no SMPS SMPS

STM32H730ABI6Q

STM32H730IBK6Q

STM32H730IBT6Q
STM32H730VBH6
STM32H730VBT6

STM32H730ZBT6

STM32H730ZBI6
Peripherals

Octo-SPI interface 1 1 2 2 2 2 2
OTFDEC yes
Cordic yes
FMAC yes
General purpose
4 4 4 4 4 4 4
32 bits
General purpose
10 10 10 10 10 10 10
16 bits
Advanced control
2 2 2 2 2 2 2
(PWM)
Timers Basic 2 2 2 2 2 2 2
Low-power 5 5 5 5 5 5 5
RTC 1 1 1 1 1 1 1
Window
watchdog /
2 2 2 2 2 2 2
independent
watchdog
Wakeup pins 4 4 4 4 4 4 4
Tamper pins 2 2 2 2 2 2 2
Random number generator yes
Cryptographic accelerator yes

DS13315 Rev 3 19/270

56
Description STM32H730xB

Table 1. STM32H730xB features and peripheral counts (continued)

no SMPS SMPS

STM32H730ABI6Q

STM32H730IBK6Q

STM32H730IBT6Q
STM32H730VBH6
STM32H730VBT6

STM32H730ZBT6

STM32H730ZBI6
Peripherals

SPI / I2S 5/4 5/4 6/4 6/4 6/4 6/4 6/4

I2C 5 5 5 5 5 5 5
USART/UART/
5/5/1 5/5/1 5/5/1 5/5/1 5/5/1 5/5/1 5/5/1
LPUART
SAI/PDM 2/1(2) 2/1(2) 2/1 2/1 2/1 2/1 2/1
SPDIFRX 1
HDMI-CEC 1
Communic
SWPMI 1
ation
interfaces MDIO 1
SDMMC 2
FDCAN/TT-
2/1 2/1 2/1 2/1 2/1 2/1 2/1
FDCAN
USB
[OTG_HS(ULPI)/ 1 [1/1] 1 [1/1] 1 [1/1] 1 [1/1] 1 [1/1] 1 [1/1] 1 [1/1]
FS(PHY)]
Ethernet
1 [1/1] 1 [1/1] 1 [1/1] 1 [1/1] 1 [1/1] 1 [1/1] 1 [1/1]
[MII/RMII]
Camera interface/PSSI yes
LCD-TFT yes
Chrom-ART Accelerator
yes
(DMA2D)
Number of ADCs 2
Number of Direct
channels 0 2/2 0 2/2 2/2 2/2 0
ADC1/ADC2
16-bit Number of Fast
ADCs channels 3/2 3/2 4/3 4/3 6/5 6/5 4/3
ADC1/ADC2
Number of Slow
channels 11/10 9/8 12/11 12/11 12/11 12/11 12/11
ADC1/ADC2

20/270 DS13315 Rev 3

STM32H730xB Description

Table 1. STM32H730xB features and peripheral counts (continued)

no SMPS SMPS

STM32H730ABI6Q

STM32H730IBK6Q

STM32H730IBT6Q
STM32H730VBH6
STM32H730VBT6

STM32H730ZBT6

STM32H730ZBI6
Peripherals

Number of ADCs 1
Number of Direct
2 2 2 2 2 2 2
channels
12-bit
ADCs Number of Fast
2 6 6 6 6 6 6
channels
Number of Slow
0 9 4 9 9 9 4
channels
Present in IC yes
12-bit DAC Number of
2
channels
Comparators 2
Operational amplifiers 2
DFSDM Present in IC yes
Maximum CPU frequency 550 MHz
USB separate supply pad - yes yes yes yes yes yes
USB internal regulator - - - - yes yes yes
LDO yes
SMPS step-down converter no yes
1.71 to
Operating voltage 1.62 to 3.6 V
3.6 V
Operating temperature -40°C to +85°C
LQFP TFBGA LQFP UFBGA UFBGA UFBGA
Package LQFP176
100 100 144 144 169 176+25
1. The 24-bit SDRAM controller is a 32-bit controller with only a 24-bit data bus and without NBL2-3. It can be used for
graphical purposes to access aligned 32-bit words ignoring upper 8 bits.
2. For limitations on peripheral features depending on packages, check the available pins/balls in Table 7: STM32H730xB pin
and ball descriptions.

DS13315 Rev 3 21/270

56
Functional overview STM32H730xB

3 Functional overview

3.1 Arm® Cortex®-M7 with FPU

The Arm® Cortex®-M7 with double-precision FPU processor is the latest generation of Arm
processors for embedded systems. It was developed to provide a low-cost platform that
meets the needs of MCU implementation, with a reduced pin count and optimized power
consumption, while delivering outstanding computational performance and low interrupt
latency.
The Cortex®-M7 processor is a highly efficient high-performance featuring:
• Six-stage dual-issue pipeline
• Dynamic branch prediction
• Harvard architecture with L1 caches (32 Kbytes of I-cache and 32 Kbytes of D-cache)
• 64-bit AXI interface
• 64-bit ITCM interface
• 2x32-bit DTCM interfaces
The following memory interfaces are supported:
• Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency
• Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM
accesses
• AXI Bus interface to optimize Burst transfers
• Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
It also supports single and double precision FPU (floating point unit) speeds up software
development by using metalanguage development tools, while avoiding saturation.
Figure 1 shows the general block diagram of the STM32H730xB family.

3.2 Memory protection unit (MPU)

The memory protection unit (MPU) manages the CPU access rights and the attributes of the
system resources. It has to be programmed and enabled before use. Its main purposes are
to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by
a privileged task, but also to protect data processes or read-protect memory regions.
The MPU defines access rules for privileged accesses and user program accesses. It
allows defining up to 16 protected regions that can in turn be divided into up to 8
independent subregions, where region address, size, and attributes can be configured. The
protection area ranges from 32 bytes to 4 Gbytes of addressable memory.
When an unauthorized access is performed, a memory management exception is
generated.

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STM32H730xB Functional overview

3.3 Memories

3.3.1 Embedded Flash memory

The STM32H730xB devices embed 128 Kbytes of Flash memory that can be used for
storing programs and data.
The Flash memory is organized as 266-bit Flash words memory that can be used for storing
both code and data constants. Each word consists of:
• one Flash word (8 words, 32 bytes or 256 bits)
• 10 ECC bits (single-error correction and double-error detection).
The Flash memory is organized as follows:
• One sector of 128 Kbytes of user Flash memory (4 K Flash memory words)
• 128 Kbytes of system Flash memory from which the device can boot
• 2 Kbytes (64 Flash words) of user option bytes for user configuration

3.3.2 Embedded SRAM

All devices feature:
• from 128 to 320 Kbytes of AXI-SRAM mapped onto the AXI bus on D1 domain
• SRAM1 mapped on D2 domain: 16 Kbytes
• SRAM2 mapped on D2 domain: 16 Kbytes
• SRAM4 mapped on D3 domain: 16 Kbytes
• 4 Kbytes of backup SRAM
The content of this area is protected against possible unwanted write accesses, and
can be retained in Standby or VBAT mode.
• RAM mapped to TCM interface (ITCM and DTCM):
Both ITCM and DTCM RAMs are 0 wait state memories. They can be accessed either
from the CPU or the MDMA (even in Sleep mode) through a specific AHB slave of the
Cortex®-M7CPU(AHBSAHBP):
– 64 to 256 Kbytes of ITCM-RAM (instruction RAM)
This RAM is connected to ITCM 64-bit interface designed for execution of critical
real-times routines by the CPU.
– 128 Kbytes of DTCM-RAM (2x 64-Kbyte DTCM-RAMs on 2x32-bit DTCM ports)
The DTCM-RAM could be used for critical real-time data, such as interrupt service
routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for
load/store operations) thanks to the Cortex®-M7 dual issue capability.
The MDMA can be used to load code or data in ITCM or DTCM RAMs. As reflected
above, 192 Kbyte of RAM can be used either for AXI SRAM or ITCM, with a 64Kbyte
granularity.

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56
Functional overview STM32H730xB

Error code correction (ECC)

Over the product lifetime, and/or due to external events such as radiations, invalid bits in
memories may occur. They can be detected and corrected by ECC. This is an expected
behavior that has to be managed at final-application software level in order to ensure data
integrity through ECC algorithms implementation.
SRAM data are protected by ECC:
• 7 ECC bits are added per 32-bit word.
• 8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM.
The ECC mechanism is based on the SECDED algorithm. It supports single-error correction
and double-error detection.

3.4 Secure access mode

In addition to other typical memory protection mechanism (RDP, PCROP), STM32H730xB
devices introduce the Secure access mode, a new enhanced security feature. This mode
allows developing user-defined secure services by ensuring, on the one hand code and
data protection and on the other hand code safe execution.
Two types of secure services are available:
• STMicroelectronics Root Secure Services:
These services are embedded in System memory. They provide a secure solution for
firmware and third-party modules installation. These services rely on cryptographic
algorithms based on a device unique private key.
• User-defined secure services:
These services are embedded in user Flash memory. Examples of user secure
services are proprietary user firmware update solution, secure Flash integrity check or
any other sensitive applications that require a high level of protection.
The secure firmware is embedded in specific user Flash memory areas configured
through option bytes.
Secure services are executed just after a reset and preempt all other applications to
guarantee protected and safe execution. Once executed, the corresponding code and data
are no more accessible.
The above secure services is activated for the next reset exits through an option bit.

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STM32H730xB Functional overview

3.5 Boot modes

At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option
bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF
which includes:
• All Flash address space
• All RAM address space: ITCM, DTCM RAMs and SRAMs
• The System memory bootloader
The boot loader is located in non-user System memory. It is used to reprogram the Flash
memory through a serial interface (USART, I2C, SPI, FDCAN, USB-DFU). Refer to
application note AN2606 “STM32 microcontroller System memory Boot mode” for details.

3.6 CORDIC co-processor (CORDIC)

The CORDIC co-processor provides hardware acceleration of certain mathematical
functions, notably trigonometric, commonly used in motor control, metering, signal
processing and many other applications.
It speeds up the calculation of these functions compared to a software implementation,
allowing a lower operating frequency, or freeing up processor cycles in order to perform
other tasks.
The filter mathematical accelerator unit performs arithmetic operations on vectors. It
comprises a multiplier/accumulator (MAC) unit, together with address generation logic,
which allows it to index vector elements held in local memory.
The unit includes support for circular buffers on input and output, which allows digital filters
to be implemented. Both finite and infinite impulse response filters can be realized.
The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing
up the processor for other tasks. In many cases it can accelerate such calculations
compared to a software implementation, resulting in a speed-up of time critical tasks.

CORDIC features
• 24-bit CORDIC rotation engine
• Circular and Hyperbolic modes
• Rotation and Vectoring modes
• Functions: Sine, Cosine, Sinh, Cosh, Atan, Atan2, Atanh, Modulus, Square root,
Natural logarithm
• Programmable precision up to 20-bit
• Fast convergence: 4 bits per clock cycle
• Supports 16-bit and 32-bit fixed point input and output formats
• Low latency AHB slave interface
• Results can be read as soon as ready without polling or interrupt
• DMA read and write channels

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56
Functional overview STM32H730xB

3.7 Filter mathematical accelerator (FMAC)

The filter mathematical accelerator unit performs arithmetic operations on vectors. It
comprises a multiplier/accumulator (MAC) unit, together with address generation logic,
which allows it to index vector elements held in local memory.
The unit includes support for circular buffers on input and output, which allows digital filters
to be implemented. Both finite and infinite impulse response filters can be realized.
The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing
up the processor for other tasks. In many cases it can accelerate such calculations
compared to a software implementation, resulting in a speed-up of time critical tasks.

FMAC features
• 16 x 16-bit multiplier
• 24+2-bit accumulator with addition and subtraction
• 16-bit input and output data
• 256 x 16-bit local memory
• Up to three areas can be defined in memory for data buffers (two input, one output),
defined by programmable base address pointers and associated size registers
• Input and output sample buffers can be circular
• Buffer “watermark” feature reduces overhead in interrupt mode
• Filter functions: FIR, IIR (direct form 1)
• AHB slave interface
• DMA read and write data channels

3.8 Power supply management

3.8.1 Power supply scheme

STM32H730xB power supply voltages are the following:
• VDD = 1.62 to 3.6 V: external power supply for I/Os, provided externally through VDD
pins.
• VDDLDO = 1.62 to 3.6 V: supply voltage for the internal regulator supplying VCORE
• VDDA = 1.62 to 3.6 V: external analog power supplies for ADC, DAC, COMP and
OPAMP.
• VDD33USB: allows the support of a VDD supply different from 3.3 V while powering the
USB transceiver with 3.3V on VDD33USB.
• VDD50USB can be supplied through the USB cable to generate the VDD33USB via the
USB internal regulator. This allows support of a VDD supply different to 3.3 V.
The USB regulator can be bypassed to supply directly VDD33USB if VDD = 3.3 V.
• VBAT = 1.2 to 3.6 V: power supply for the VSW domain when VDD is not present.
• VCAP: VCORE supply voltage, which values depend on voltage scaling (1.0 V, 1.1 V,
1.2 V or 1.35 V). They are configured through VOS bits in PWR_D3CR register. The

26/270 DS13315 Rev 3

STM32H730xB Functional overview

VCORE domain is split into the following power domains that can be independently
switch off.
– D1 domain containing some peripherals and the Cortex®-M7 core
– D2 domain containing a large part of the peripherals
– D3 domain containing some peripherals and the system control
• VDDSMPS= 1.62 V to 3.6 V: SMPS step-down converter power supply VDDSMPS
must be kept at the same voltage level as VDD
• VLXSMPS = SMPS step-down converter output coupled to an inductor
• VFBSMPS = VCORE or 1.8 V or 2.5 V external SMPS step-down converter feedback
voltage sense input.
During power-up and power-down phases, the following power sequence requirements
must be respected (see Figure 2):
• When VDD is below VDDmin, other power supplies (VDDA, VDD33USB, VDD50USB) must
remain below VDD + 300 mV.
• When VDD is above VDDmin, all power supplies are independent.
During the power-down phase, VDD can temporarily become lower than other supplies only
if the energy provided to the microcontroller remains below 1 mJ. This allows external
decoupling capacitors to be discharged with different time constants during the power-down
transient phase.

Figure 2. Power-up/power-down sequence

3.6
VDDX(1)

VDD

VBOR0

0.3

Power-on Operating mode Power-down time

Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
MSv47490V1

1. VDDx refers to any power supply among VDDA, VDD33USB, VDD50USB.

DS13315 Rev 3 27/270

56
Functional overview STM32H730xB

3.8.2 Power supply supervisor

The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry:
• Power-on reset (POR)
The POR supervisor monitors VDD power supply and compares it to a fixed threshold.
The devices remain in Reset mode when VDD is below this threshold,
• Power-down reset (PDR)
The PDR supervisor monitors VDD power supply. A reset is generated when VDD drops
below a fixed threshold.
The PDR supervisor can be enabled/disabled through PDR_ON pin.
• Brownout reset (BOR)
The BOR supervisor monitors VDD power supply. Three BOR thresholds (from 2.1 to
2.7 V) can be configured through option bytes. A reset is generated when VDD drops
below this threshold.

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STM32H730xB Functional overview

3.8.3 Voltage regulator

The same voltage regulator supplies the 3 power domains (D1, D2 and D3). D1 and D2 can
be independently switched off.
Voltage regulator output can be adjusted according to application needs through 6 power
supply levels:
• Run mode (VOS0 to VOS3)
– Scale 0: boosted performance
– Scale 1: high performance
– Scale 2: medium performance and consumption
– Scale 3: optimized performance and low-power consumption
• Stop mode (SVOS3 to SVOS5)
– Scale 3: peripheral with wakeup from Stop mode capabilities (UART, SPI, I2C,
LPTIM) are operational
– Scale 4 and 5 where the peripheral with wakeup from Stop mode is disabled. The
peripheral functionality is disabled but wakeup from Stop mode is possible through
GPIO or asynchronous interrupt.

3.9 Low-power strategy

There are several ways to reduce power consumption on STM32H730xB:
• Decrease the dynamic power consumption by slowing down the system clocks even in
Run mode and by individually clock gating the peripherals that are not used.
• Save power when the CPU is idle, by selecting among the available low-power modes
according to the user application needs. This allows the best compromise between
short startup time and low power consumption to be achieved, according to the
available wakeup sources.
The devices feature several low-power modes:
• CSleep (CPU clock stopped)
• CStop (CPU sub-system clock stopped)
• DStop (Domain bus matrix clock stopped)
• Stop (System clock stopped)
• DStandby (Domain powered down)
• Standby (System powered down)
CSleep and CStop low-power modes are entered by the MCU when executing the WFI
(Wait for Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of
the Cortex®-Mx core is set after returning from an interrupt service routine.
A domain can enter low-power mode (DStop or DStandby) when the processor, its
subsystem and the peripherals allocated in the domain enter low-power mode.
If part of the domain is not in low-power mode, the domain remains in the current mode.
Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared
and the power domains are in DStop or DStandby mode.

DS13315 Rev 3 29/270

56
Functional overview STM32H730xB

Table 2. System versus domain low-power mode

System power mode D1 domain power mode D2 domain power mode D3 domain power mode

Run DRun/DStop/DStandby DRun/DStop/DStandby DRun

Stop DStop/DStandby DStop/DStandby DStop
Standby DStandby DStandby DStandby

3.10 Reset and clock controller (RCC)

The clock and reset controller is located in D3 domain. The RCC manages the generation of
all the clocks, as well as the clock gating and the control of the system and peripheral
resets. It provides a high flexibility in the choice of clock sources and allows to apply clock
ratios to improve the power consumption. In addition, on some communication peripherals
that are capable to work with two different clock domains (either a bus interface clock or a
kernel peripheral clock), thus the system frequency can be changed without modifying the
baudrate.

3.10.1 Clock management

The devices embed four internal oscillators, two oscillators with external crystal or
resonator, two internal oscillators with fast startup time and three PLLs.
The RCC receives the following clock source inputs:
• Internal oscillators:
– 64 MHz HSI clock
– 48 MHz RC oscillator
– 4 MHz CSI clock
– 32 kHz LSI clock
• External oscillators:
– HSE clock: 4-50 MHz (generated from an external source) or 4-48 MHz(generated
from a crystal/ceramic resonator)
– LSE clock: 32.768 kHz
The RCC provides three PLLs: one for system clock, two for kernel clocks.
The system starts on the HSI clock. The user application can then select the clock
configuration.

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STM32H730xB Functional overview

3.10.2 System reset sources

Power-on reset initializes all registers while system reset reinitializes the system except for
the debug, part of the RCC and power controller status registers, as well as the backup
power domain.
A system reset is generated in the following cases:
• Power-on reset (pwr_por_rst)
• Brownout reset
• Low level on NRST pin (external reset)
• Window watchdog
• Independent watchdog
• Software reset
• Low-power mode security reset
• Exit from Standby

3.11 General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
After reset, all GPIOs (except debug pins) are in Analog mode to reduce power
consumption (refer to GPIOs register reset values in the device reference manual).
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.

3.12 Bus-interconnect matrix

The devices feature an AXI bus matrix, two AHB bus matrices and bus bridges that allow
the interconnection of bus masters with bus slaves (see Figure 3).

DS13315 Rev 3 31/270

56
 Figure 3. STM32H730xB bus matrix

32/270

Functional overview
AHBS
ITCM
CPU 64 Kbyte
Cortex-M7 OR
ITCM
I$ D$ 192 Kbyte
DMA1 DMA2 Ethernet SDMMC2 USBHS1
32KB 32KB DTCM MAC
128 Kbyte

AXIM

AHBP

DMA1_PERIPH

DMA2_PERIPH
DMA1_MEM

DMA2_MEM
SDMMC1 MDMA DMA2D LTDC
D1-to-D2 AHB

AXI SRAM
192K byte SRAM1 16
Kbyte

SRAM2 16
Kbyte
Flash A
128 Kbytes
AHB1
AXI SRAM
128 Kbyte
DS13315 Rev 3

AHB2
OTFDEC1 OCTOSPI1

OTFDEC2 OCTOSPI2 APB1

FMC APB2

AHB3 APB3

64-bit AXI bus matrix 32-bit AHB bus matrix

D1 domain D2 domain

D2-to-D1 AHB
D2-to-D3 AHB
D1-to-D3 AHB
BDMA
32-bit AHB bus matrix
D3 domain

Legend

STM32H730xB
AHB4 APB4
TCM AHB
32-bit bus AXI APB SRAM4
64-bit bus Master interface 16 Kbyte

Bus multiplexer Slave interface Backup

SRAM
4 Kbyte
MSv65315V1
STM32H730xB Functional overview

3.13 DMA controllers

The devices feature four DMA instances and a DMA request router to unload CPU activity:
• A master direct memory access (MDMA)
The MDMA is a high-speed DMA controller, which is in charge of all types of memory
transfers (peripheral to memory, memory to memory, memory to peripheral), without
any CPU action. It features a master AXI interface and a dedicated AHB interface to
access Cortex®-M7 TCM memories.
The MDMA is located in D1 domain. It is able to interface with the other DMA
controllers located in D2 domain to extend the standard DMA capabilities, or can
manage peripheral DMA requests directly.
Each of the 16 channels can perform single block transfers, repeated block transfers
and linked list transfers.
• Two dual-port DMAs (DMA1, DMA2) located in D2 domain, with FIFO and request
router capabilities.
• One basic DMA (BDMA) located in D3 domain, with request router capabilities.
• A DMA request multiplexer (DMAMUX)
The DMA request router could be considered as an extension of the DMA controller. It
routes the DMA peripheral requests to the DMA controller itself. This allowing
managing the DMA requests with a high flexibility, maximizing the number of DMA
requests that run concurrently, as well as generating DMA requests from peripheral
output trigger or DMA event.

3.14 Chrom-ART Accelerator (DMA2D)

The Chrom-Art Accelerator (DMA2D) is a specialized DMA dedicated to image manipulation.
It can perform the following operations:
• Filling a part or the whole of a destination image with a specific color
• Copying a part or the whole of a source image into a part or the whole of a destination
• image
• Copying a part or the whole of a source image into a part or the whole of a destination
• image with a pixel format conversion
• Blending a part and/or two complete source images with different pixel format and copy
• the result into a part or the whole of a destination image with a different color format.
• All the classical color coding schemes are supported from 4-bit up to 32-bit per pixel
with indexed or direct color mode, including block based YCbCr to handle JPEG
decoder output.
• The DMA2D has its own dedicated memories for CLUTs (color look-up tables).
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automated and are running independently from the CPU or the
DMAs.

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3.15 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller which is able to manage 16
priority levels, and handle up to 140 maskable interrupt channels plus the 16 interrupt lines
of the Cortex®-M7 with FPU core.
• Closely coupled NVIC gives low-latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Allows early processing of interrupts
• Processing of late arriving, higher-priority interrupts
• Support tail chaining
• Processor context automatically saved on interrupt entry, and restored on interrupt exit
with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.

3.16 Extended interrupt and event controller (EXTI)

The EXTI controller performs interrupt and event management. In addition, it can wake up
the processor, power domains and/or D3 domain from Stop mode.
The EXTI handles up to 80 independent event/interrupt lines split as 26 configurable events
and 54 direct events.
Configurable events have dedicated pending flags, active edge selection, and software
trigger capable.
Direct events provide interrupts or events from peripherals having a status flag.

3.17 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
programmable polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.

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3.18 Flexible memory controller (FMC)

The FMC controller main features are the following:
• Interface with static-memory mapped devices including:
– Static random access memory (SRAM)
– NOR Flash memory/OneNAND Flash memory
– PSRAM (4 memory banks)
– NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
• Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
• 8-,16-, 24-bit data bus width
• Independent Chip Select control for each memory bank
• Independent configuration for each memory bank
• Write FIFO
• Read FIFO for SDRAM controller
• The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is the
FMC kernel clock divided by 2.

3.19 Octo-SPI memory interface (OCTOSPI)

The OCTOSPI is a specialized communication interface targeting single, dual, quad or octal
SPI memories. The STM32H730xB embeds two separate Octo-SPI interfaces.
Each OCTOSPI instance supports single/dual/quad/octal SPI formats. multiplexing of
single/dual/quad/octal SPI over the same bus can be achieved using the integrated Octo-
SPI I/O manager (OCTOSPIM).
The OCTOSPI can operate in any of the three following modes:
• Indirect mode: all the operations are performed using the OCTOSPI registers
• Status-polling mode: the external memory status register is periodically read and an
interrupt can be generated in case of flag setting
• Memory-mapped mode: the external memory is memory mapped and it is seen by the
system as if it was an internal memory supporting both read and write operations.
The OCTOSPI supports two frame formats supported by most external serial memories
such as serial PSRAMs, serial NAND and serial NOR Flash memories, Hyper RAMs and
Hyper Flash memories.
Multi chip package (MCP) combining any of the above mentioned memory types can also
be supported.
• The classical frame format with the command, address, alternate byte, dummy cycles
and data phase
• The HyperBus™ frame format.

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3.20 Analog-to-digital converters (ADCs)

STM32H730xB devices embed three analog-to-digital converters, two of 16-bit resolution,
and the third of 12-bit resolution. The 16-bit resolution ADCs can be configured as 16, 14,
12, 10 or 8 bits. The 12-bit resolution ADC can be configured to 12, 10 or 8 bits.
Each ADC shares up to 20 external channels, performing conversions in Single-shot or
Scan mode. In Scan mode, automatic conversion is performed on a selected group of
analog inputs.
Additional logic functions embedded in the ADC interface allow:
• simultaneous sample and hold
• Interleaved sample and hold
The ADC can be served by the DMA controller, thus allowing automatic transfer of ADC
converted values to a destination location without any software action.
In addition, an analog watchdog feature can accurately monitor the converted voltage of
one, some, or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs can be triggered by any of the TIM1,
TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, TIM23, TIM24, and LPTIM1 timers.

3.21 Temperature sensor

STM32H730xB devices embed a temperature sensor that generates a voltage (VTS) that
varies linearly with the temperature. This temperature sensor is internally connected to
ADC3_IN17. The conversion range is between 1.7 V and 3.6 V. It can measure the device
junction temperature ranging from − 40 to +125°C.
The temperature sensor have a good linearity, but it has to be calibrated to obtain a good
overall accuracy of the temperature measurement. As the temperature sensor offset varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only. To improve the accuracy of
the temperature sensor measurement, each device is individually factory-calibrated by ST.
The temperature sensor factory calibration data are stored by ST in the System memory
area, which is accessible in Read-only mode.

3.22 Digital temperature sensor (DTS)

STM32H730xB devices embed a sensor that converts the temperature into a square wave
the frequency of which is proportional to the temperature. The PCLK or the LSE clock can
be used as the reference clock for the measurements. A formula given in the product
reference manual allows calculation of the temperature according to the measured
frequency stored in the DTS_DR register.

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3.23 VBAT operation

The VBAT power domain contains the RTC, the backup registers and the backup SRAM.
To optimize battery duration, this power domain is supplied by VDD when available or by the
voltage applied on VBAT pin (when VDD supply is not present). VBAT power is switched
when the PDR detects that VDD dropped below the PDR level.
The voltage on the VBAT pin could be provided by an external battery, a supercapacitor or
directly by VDD, in which case, the VBAT mode is not functional.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
When PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no
more available and VBAT pin should be connected to VDD.

3.24 Digital-to-analog converters (DAC)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
• two DAC converters: one for each output channel
• 8-bit or 12-bit monotonic output
• left or right data alignment in 12-bit mode
• synchronized update capability
• noise-wave generation
• triangular-wave generation
• dual DAC channel independent or simultaneous conversions
• DMA capability for each channel including DMA underrun error detection
• external triggers for conversion
• input voltage reference VREF+ or internal VREFBUF reference.
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA streams.

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3.25 Ultra-low-power comparators (COMP)

STM32H730xB devices embed two rail-to-rail comparators (COMP1 and COMP2). They
feature programmable reference voltage (internal or external), hysteresis and speed (low
speed for low-power) as well as selectable output polarity.
The reference voltage can be one of the following:
• An external I/O
• A DAC output channel
• An internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers,
and be combined into a window comparator.

3.26 Operational amplifiers (OPAMP)

STM32H730xB devices embed two rail-to-rail operational amplifiers (OPAMP1 and
OPAMP2) with external or internal follower routing and PGA capability.
The operational amplifier main features are:
• PGA with a non-inverting gain ranging of 2, 4, 8 or 16 or inverting gain ranging of -1, -3,
-7 or -15
• One positive input connected to DAC
• Output connected to internal ADC
• Low input bias current down to 1 nA
• Low input offset voltage down to 1.5 mV
• Gain bandwidth up to 7.3 MHz
The devices embeds two operational amplifiers (OPAMP1 and OPAMP2) with two inputs
and one output each. These three I/Os can be connected to the external pins, thus enabling
any type of external interconnections. The operational amplifiers can be configured
internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 16 or with
inverting gain ranging from -1 to -15.

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3.27 Digital filter for sigma-delta modulators (DFSDM)

The devices embed one DFSDM with 4 digital filters modules and 8 external input serial
channels (transceivers) or alternately 8 internal parallel inputs support.
The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse
Density Modulation) microphones and perform PDM to PCM conversion and filtering in
hardware. DFSDM features optional parallel data stream inputs from internal ADC
peripherals or microcontroller memory (through DMA/CPU transfers into DFSDM).
DFSDM transceivers support several serial interface formats (to support various Σ∆
modulators). DFSDM digital filter modules perform digital processing according user
selected filter parameters with up to 24-bit final ADC resolution.
The DFSDM peripheral supports:
• 8 multiplexed input digital serial channels:
– configurable SPI interface to connect various SD modulator(s)
– configurable Manchester coded 1 wire interface support
– PDM (Pulse Density Modulation) microphone input support
– maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
– clock output for SD modulator(s): 0..20 MHz
• alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution):
– internal sources: ADC data or memory data streams (DMA)
• 4 digital filter modules with adjustable digital signal processing:
– Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
– integrator: oversampling ratio (1..256)
• up to 24-bit output data resolution, signed output data format
• automatic data offset correction (offset stored in register by user)
• continuous or single conversion
• start-of-conversion triggered by:
– software trigger
– internal timers
– external events
– start-of-conversion synchronously with first digital filter module (DFSDM0)
• analog watchdog feature:
– low value and high value data threshold registers
– dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
– input from final output data or from selected input digital serial channels
– continuous monitoring independently from standard conversion
• short circuit detector to detect saturated analog input values (bottom and top range):
– up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream
– monitoring continuously each input serial channel
• break signal generation on analog watchdog event or on short circuit detector event

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• extremes detector:
– storage of minimum and maximum values of final conversion data
– refreshed by software
• DMA capability to read the final conversion data
• interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial
channel clock absence
• “regular” or “injected” conversions:
– “regular” conversions can be requested at any time or even in Continuous mode
without having any impact on the timing of “injected” conversions
– “injected” conversions for precise timing and with high conversion priority
• Pulse skipper feature to support beamforming applications (delay-line like behavior).

Table 3. DFSDM implementation

DFSDM features DFSDM1

Number of filters 4
Number of input
8
transceivers/channels
Internal ADC parallel input X
Number of external triggers 16
Regular channel information in
X
identification register

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3.28 Digital camera interface (DCMI)

The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can achieve a data transfer rate up to 140 Mbyte/s using a 80 MHz pixel clock. It
features:
• Programmable polarity for the input pixel clock and synchronization signals
• Parallel data communication can be 8-, 10-, 12- or 14-bit
• Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
• Supports Continuous mode or Snapshot (a single frame) mode
• Capability to automatically crop the image

3.29 PSSI
The PSSI is a generic synchronous 8-/16-bit parallel data input/output slave interface. It
allows the transmitter to send a data valid signal to indicate when the data is valid, and the
receiver to output a flow control signal to indicate when it is ready to sample the data.
The main PSSI features are:
• Slave mode operation
• 8- or 16-bit parallel data input or output
• 8-word (32-byte) FIFO
• Data enable (DE) alternate function input and Ready (RDY) alternate function output.
When enabled, these signals can either allow the transmitter to indicate when the data is
valid or, the receiver to indicate when it is ready to sample the data, or both.
The PSSI shares most of its circuitry with the digital camera interface (DCMI). It therefore
cannot be used simultaneously with the DCMI.

3.30 LCD-TFT controller

The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024 x 768) resolution with the following features:
• 2 display layers with dedicated FIFO (64x64-bit)
• Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
• Up to 8 input color formats selectable per layer
• Flexible blending between two layers using alpha value (per pixel or constant)
• Flexible programmable parameters for each layer
• Color keying (transparency color)
• Up to 4 programmable interrupt events
• AXI master interface with burst of 16 words

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3.31 True random number generator (RNG)

The RNG is a true random number generator that provides full entropy outputs to the
application as 32-bit samples. It is composed of a live entropy source (analog) and an
internal conditioning component.
The RNG can be used to construct a Non-deterministic Random Bit Generator (NDRBG), as
a NIST SP 800-90B compliant entropy source.
The RNG true random number generator has been tested using German BSI statistical tests
of AIS-31 (T0 to T8), and NIST SP800-90B statistical test suite.

3.32 Cryptographic acceleration (CRYP and HASH)

The devices embed a cryptographic processor that supports the advanced cryptographic
algorithms usually required to ensure confidentiality, authentication, data integrity and non-
repudiation when exchanging messages
with a peer:
• Encryption/Decryption
– DES/TDES (data encryption standard/triple data encryption standard): ECB
(electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64-,
128- or 192-bit key
– AES (advanced encryption standard): ECB, CBC, GCM, CCM, and CTR (counter
mode) chaining algorithms, 128, 192 or 256-bit key
• Universal HASH
– – SHA-1 and SHA-2 (secure HASH algorithms)
– – MD5
– – HMAC
The cryptographic accelerator supports DMA request generation.

3.33 On-the-fly decryption engine (OTFDEC)

The embedded OTFDEC decrypts in real-time the encrypted content stored in the external
Octo-SPI memories used in Memory-mapped mode.
The OTFDEC uses the AES-128 algorithm in counter mode (CTR).
Code execution on external Octo-SPI memories can be protected against fault injection
thanks to
STMicroelectronics enhanced encryption mode (refer to RM0468 for details).

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The OTFDEC main features are as follow:

• On-the-fly 128-bit decryption during STM32 Octo-SPI read operations (single or
multiple).
– AES-CTR algorithm with keystream FIFO (depth= 4)
– Support for any read size
• Up to four independent encrypted regions
– Region definition granularity: 4096 bytes
– Region configuration write locking mechanism
– Two optional decryption modes: execute-only and execute-never
• 128-bit key for each region, two-byte firmware version, and eight-byte application-
defined nonce
• Encryption keys confidentiality and integrity protection
– Write only registers with software locking mechanism
– Availability of 8-bit CRC as public key information
• Support for STM32 Octo-SPI prefetching mechanism.

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3.34 Timers and watchdogs

The devices include two advanced-control timers, twelve general-purpose timers, two basic
timers, five low-power timers, two watchdogs and a SysTick timer.
All timer counters can be frozen in Debug mode.
Table 4 compares the features of the advanced-control, general-purpose and basic timers.

Table 4. Timer feature comparison

Max
Max
DMA Capture/ Comple- timer
Timer Counter Counter Prescaler interface
Timer request compare mentary clock
type resolution type factor clock
generation channels output (MHz)
(MHz) (1)

Any
Up, integer
Advanced TIM1,
16-bit Down, between 1 Yes 4 Yes 137.5 275
-control TIM8
Up/down and
65536
Any
TIM2,
Up, integer
TIM5,
32-bit Down, between 1 Yes 4 No 137.5 275
TIM23,
Up/down and
TIM24
65536
Any
Up, integer
TIM3,
16-bit Down, between 1 Yes 4 No 137.5 275
TIM4
Up/down and
65536
Any
integer
TIM12 16-bit Up between 1 No 2 No 137.5 275
and
General 65536
purpose Any
integer
TIM13,
16-bit Up between 1 No 1 No 137.5 275
TIM14
and
65536
Any
integer
TIM15 16-bit Up between 1 Yes 2 1 137.5 275
and
65536
Any
integer
TIM16,
16-bit Up between 1 Yes 1 1 137.5 275
TIM17
and
65536

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Table 4. Timer feature comparison (continued)

Max
Max
DMA Capture/ Comple- timer
Timer Counter Counter Prescaler interface
Timer request compare mentary clock
type resolution type factor clock
generation channels output (MHz)
(MHz) (1)

Any
integer
TIM6,
Basic 16-bit Up between 1 Yes 0 No 137.5 275
TIM7
and
65536
LPTIM1,
Low- LPTIM2, 1, 2, 4, 8,
power LPTIM3, 16-bit Up 16, 32, No 0 No 137.5 275
timer LPTIM4, 64, 128
LPTIM5
1. The maximum timer clock is up to 550 MHz depending on theTIMPRE bit in the RCC_CFGR register and D2PRE1/2 bits in
RCC_D2CFGR register.

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3.34.1 Advanced-control timers (TIM1, TIM8)

The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
• Input capture
• Output compare
• PWM generation (Edge- or Center-aligned modes)
• One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-
100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.

3.34.2 General-purpose timers (TIMx)

There are ten synchronizable general-purpose timers embedded in the STM32H730xB
devices (see Table 4: Timer feature comparison for differences).
• TIM2, TIM3, TIM4, TIM5, TIM23, TIM24
The devices include 4 full-featured general-purpose timers: TIM2, TIM3, TIM4, TIM5,
TIM23 and TIM24. TIM2, TIM5, TIM23 and TIM24 are based on a 32-bit auto-reload
up/downcounter and a 16-bit prescaler while TIM3 and TIM4 are based on a 16-bit
auto-reload up/downcounter and a 16-bit prescaler. All timers feature 4 independent
channels for input capture/output compare, PWM or One-pulse mode output. This
gives up to 24 input capture/output compare/PWMs on the largest packages.
TIM2, TIM3, TIM4, TIM5, TIM23 and TIM24 general-purpose timers can work together,
or with the other general-purpose timers and the advanced-control timers TIM1 and
TIM8 via the Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5, TIM23, and TIM24 all have independent DMA request
generation. They are capable of handling quadrature (incremental) encoder signals
and the digital outputs from 1 to 4 hall-effect sensors.
• TIM12, TIM13, TIM14, TIM15, TIM16, TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM13, TIM14, TIM16 and TIM17 feature one independent channel, whereas TIM12
and TIM15 have two independent channels for input capture/output compare, PWM or
One-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5,
TIM23, and TIM24 full-featured general-purpose timers or used as simple time bases.

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3.34.3 Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.

3.34.4 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5)

The low-power timers have an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
• 16-bit up counter with 16-bit autoreload register
• 16-bit compare register
• Configurable output: pulse, PWM
• Continuous / One-shot mode
• Selectable software / hardware input trigger
• Selectable clock source:
• Internal clock source: LSE, LSI, HSI or APB clock
• External clock source over LPTIM input (working even with no internal clock source
running, used by the Pulse Counter Application)
• Programmable digital glitch filter
• Encoder mode

3.34.5 Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
A window option allows the device to be reset when a reload operation is made too early
after the previous reload.

3.34.6 Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
Debug mode.

3.34.7 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
• A 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source.

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3.35 Real-time clock (RTC), backup SRAM and backup registers

The RTC is an independent BCD timer/counter. It supports the following features:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
• Two programmable alarms.
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
• Three anti-tamper detection pins with programmable filter.
• Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
• 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby mode.
The RTC clock sources can be:
• A 32.768 kHz external crystal (LSE)
• An external resonator or oscillator (LSE)
• The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
• The high-speed external clock (HSE) divided by 32.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes.
All RTC events (Alarm, Wakeup Timer, Timestamp or Tamper) can generate an interrupt and
wakeup the device from the low-power modes.

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3.36 Inter-integrated circuit interface (I2C)

STM32H730xB devices embed five I2C interfaces.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
• I2C-bus specification and user manual rev. 5 compatibility:
– Slave and Master modes, multimaster capability
– Standard-mode (Sm), with a bitrate up to 100 kbit/s
– Fast-mode (Fm), with a bitrate up to 400 kbit/s
– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
• System Management Bus (SMBus) specification rev 2.0 compatibility:
– Hardware PEC (Packet Error Checking) generation and verification with ACK
control
– Address resolution protocol (ARP) support
– SMBus alert
• Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming.
• Wakeup from Stop mode on address match
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability

3.37 Universal synchronous/asynchronous receiver transmitter

(USART)
STM32H730xB devices have five embedded universal synchronous receiver transmitters
(USART1, USART2, USART3, USART6, and USART10) and five universal asynchronous
receiver transmitters (UART4, UART5, UART7, UART8, and UART9). Refer to Table 5:
USART features for a summary of USARTx and UARTx features.
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire Half-duplex communication mode and
have LIN Master/Slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 Driver Enable. They are able to communicate at speeds of up to
17 Mbit/s.
USART1, USART2, USART3, USART6, and USART10 also provide Smartcard mode (ISO
7816 compliant) and SPI-like communication capability.
The USARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode
is enabled by software and is disabled by default.

DS13315 Rev 3 49/270

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Functional overview STM32H730xB

All USART have a clock domain independent from the CPU clock, allowing the USARTx to
wake up the MCU from Stop mode.The wakeup from Stop mode is programmable and can
be done on:
• Start bit detection
• Any received data frame
• A specific programmed data frame
• Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
All USART interfaces can be served by the DMA controller.

Table 5. USART features

USART modes/features(1) USART1/2/3/6/10 UART4/5/7/8/9

Hardware flow control for modem X X

Continuous communication using DMA X X
Multiprocessor communication X X
Synchronous mode (Master/Slave) X -
Smartcard mode X -
Single-wire Half-duplex communication X X
IrDA SIR ENDEC block X X
LIN mode X X
Dual clock domain and wakeup from low power mode X X
Receiver timeout interrupt X X
Modbus communication X X
Auto baud rate detection X X
Driver Enable X X
USART data length 7, 8 and 9 bits
Tx/Rx FIFO X X
Tx/Rx FIFO size 16
1. X = supported.

3.38 Low-power universal asynchronous receiver transmitter

(LPUART)
The device embeds one Low-Power UART (LPUART1). The LPUART supports
asynchronous serial communication with minimum power consumption. It supports half
duplex single wire communication and modem operations (CTS/RTS). It allows
multiprocessor communication.
The LPUARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO
mode is enabled by software and is disabled by default.

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The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode. The wakeup from Stop mode are programmable and can be done
on:
• Start bit detection
• Any received data frame
• A specific programmed data frame
• Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to
9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame
while having an extremely low energy consumption. Higher speed clock can be used to
reach higher baudrates.
LPUART interface can be served by the DMA controller.

3.39 Serial peripheral interface (SPI)/inter- integrated sound

interfaces (I2S)
The devices feature up to six SPIs (SPI2S1, SPI2S2, SPI2S3, SPI4, SPI5 and SPI2S6) that
allow communicating up to 150 Mbits/s in Master and Slave modes, in Half-duplex, Full-
duplex and Simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the
frame is configurable from 4 to 16 bits. All SPI interfaces support NSS pulse mode, TI mode,
Hardware CRC calculation and 8x 8-bit embedded Rx and Tx FIFOs with DMA capability.
Four standard I2S interfaces (multiplexed with SPI1, SPI2, SPI3 and SPI6) are available.
They can be operated in Master or Slave mode, in Simplex communication modes, and can
be configured to operate as a 16-/32-bit resolution input or output channel (except SPI2S6
which is limited to 16 bits). Audio sampling frequencies from 8 kHz up to 192 kHz are
supported. When either or both of the I2S interfaces is/are configured in Master mode, the
master clock can be output to the external DAC/CODEC at 256 times the sampling
frequency. All I2S interfaces support 16x 8-bit embedded Rx and Tx FIFOs with DMA
capability.

3.40 Serial audio interfaces (SAI)

The devices embed 2 SAIs (SAI1, and SAI4) that allow designing many stereo or mono
audio protocols such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC’97. An SPDIF
output is available when the audio block is configured as a transmitter. To bring this level of
flexibility and reconfigurability, the SAI contains two independent audio sub-blocks. Each
block has it own clock generator and I/O line controller.
Audio sampling frequencies up to 192 kHz are supported.
In addition, up to 8 microphones can be supported thanks to an embedded PDM interface.
The SAI can work in master or slave configuration. The audio sub-blocks can be either
receiver or transmitter and can work synchronously or asynchronously (with respect to the
other one). The SAI can be connected with other SAIs to work synchronously.

DS13315 Rev 3 51/270

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Functional overview STM32H730xB

3.41 SPDIFRX Receiver Interface (SPDIFRX)

The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958
and IEC-61937. These standards support simple stereo streams up to high sample rate,
and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up
to 5.1).
The main SPDIFRX features are the following:
• Up to 4 inputs available
• Automatic symbol rate detection
• Maximum symbol rate: 12.288 MHz
• Stereo stream from 32 to 192 kHz supported
• Supports Audio IEC-60958 and IEC-61937, consumer applications
• Parity bit management
• Communication using DMA for audio samples
• Communication using DMA for control and user channel information
• Interrupt capabilities
The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and
decode the incoming data stream. The user can select the wanted SPDIF input, and when a
valid signal will be available, the SPDIFRX will re-sample the incoming signal, decode the
Manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the
CPU decoded data, and associated status flags.
The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF
sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms.

3.42 Single wire protocol master interface (SWPMI)

The Single wire protocol master interface (SWPMI) is the master interface corresponding to
the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The
main features are:
• Full-duplex communication mode
• automatic SWP bus state management (active, suspend, resume)
• configurable bitrate up to 2 Mbit/s
• automatic SOF, EOF and CRC handling
SWPMI can be served by the DMA controller.

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3.43 Management data input/output (MDIO) slaves

The devices embed an MDIO slave interface it includes the following features:
• 32 MDIO Registers addresses, each of which is managed using separate input and
output data registers:
– 32 x 16-bit firmware read/write, MDIO read-only output data registers
– 32 x 16-bit firmware read-only, MDIO write-only input data registers
• Configurable slave (port) address
• Independently maskable interrupts/events:
– MDIO Register write
– MDIO Register read
– MDIO protocol error
• Able to operate in and wake up from Stop mode

3.44 SD/SDIO/MMC card host interfaces (SDMMC)

Two SDMMC host interfaces are available. They support MultiMediaCard System
Specification Version 4.51 in three different databus modes: 1 bit (default), 4 bits and 8 bits.
Both interfaces support the SD memory card specifications version 4.1. and the SDIO card
specification version 4.0. in two different databus modes: 1 bit (default) and 4 bits.
Each SDMMC host interface supports only one SD/SDIO/MMC card at any one time and a
stack of MMC Version 4.51 or previous.
The SDMMC host interface embeds a dedicated DMA controller allowing high-speed
transfers between the interface and the SRAM.

3.45 Controller area network (FDCAN1, FDCAN2, FDCAN3)

The controller area network (CAN) subsystem consists of two CAN modules, a shared
message RAM memory and a clock calibration unit.
All CAN modules (FDCAN1, FDCAN2, and FDCAN3) are compliant with ISO 11898-1 (CAN
protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0.
FDCAN1 supports time triggered CAN (TT-FDCAN) specified in ISO 11898-4, including
event synchronized time-triggered communication, global system time, and clock drift
compensation. The FDCAN1 contains additional registers, specific to the time triggered
feature. The CAN FD option can be used together with event-triggered and time-triggered
CAN communication.
A 10-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers,
transmit event FIFOs, transmit buffers (and triggers for TT-FDCAN). This message RAM is
shared between the three modules - FDCAN1 FDCAN2 and FDCAN3.
The common clock calibration unit is optional. It can be used to generate a calibrated clock
for FDCAN1, FDCAN2 and FDCAN3 from the HSI internal RC oscillator and the PLL, by
evaluating CAN messages received by the FDCAN1.

DS13315 Rev 3 53/270

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Functional overview STM32H730xB

3.46 Universal serial bus on-the-go high-speed (OTG_HS)

The devices embed an USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral
that supports both full-speed and high-speed operations. It integrates the transceivers for
full-speed operation (12 Mbit/s) and a UTMI low-pin interface (ULPI) for high-speed
operation (480 Mbit/s). When using the USB OTG_HS interface in HS mode, an external
PHY device connected to the ULPI is required.
The USB OTG_HS peripheral is compliant with the USB 2.0 specification and with the OTG
2.0 specification. It features software-configurable endpoint setting and supports
suspend/resume. The USB OTG_HS controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The main features are:
• Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing
• Supports the session request protocol (SRP) and host negotiation protocol (HNP)
• 8 bidirectional endpoints
• 16 host channels with periodic OUT support
• Software configurable to OTG1.3 and OTG2.0 modes of operation
• USB 2.0 LPM (Link Power Management) support
• Battery Charging Specification Revision 1.2 support
• Internal FS OTG PHY support
• External HS or HS OTG operation supporting ULPI in SDR mode The OTG PHY is
connected to the microcontroller ULPI port through 12 signals. It can be clocked using
the 60 MHz output.
• Internal USB DMA
• HNP/SNP/IP inside (no need for any external resistor)
• For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected

3.47 Ethernet MAC interface with dedicated DMA controller (ETH)

The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.

54/270 DS13315 Rev 3

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The devices include the following features:

• Supports 10 and 100 Mbit/s rates
• Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors
• Tagged MAC frame support (VLAN support)
• Half-duplex (CSMA/CD) and full-duplex operation
• MAC control sublayer (control frames) support
• 32-bit CRC generation and removal
• Several address filtering modes for physical and multicast address (multicast and
group addresses)
• 32-bit status code for each transmitted or received frame
• Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
• Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
• Triggers interrupt when system time becomes greater than target time

3.48 High-definition multimedia interface (HDMI)

- consumer electronics control (CEC)
The devices embed a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC
controller to wakeup the MCU from Stop mode on data reception.

3.49 Debug infrastructure

The devices offer a comprehensive set of debug and trace features to support software
development and system integration.
• Breakpoint debugging
• Code execution tracing
• Software instrumentation
• JTAG debug port
• Serial-wire debug port
• Trigger input and output
• Serial-wire trace port
• Trace port
• Arm® CoreSight™ debug and trace components
The debug can be controlled via a JTAG/Serial-wire debug access port, using industry
standard debugging tools. The trace port performs data capture for logging and analysis.

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Memory mapping STM32H730xB

4 Memory mapping

Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.

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5 Pinouts, pin descriptions and alternate functions

Figure 4. TFBGA100 pinout (without SMPS)

1 2 3 4 5 6 7 8 9 10

PC14-
A PC13 PE2 PB9 PB7 PB4 PB3 PA15 PA14 PA13
OSC32_IN

PC15-
B VBAT PE3 PB8 PB6 PD5 PD2 PC11 PC10 PA12
OSC32_OUT

C PH0-OSC_IN VSS PE4 PE1 PB5 PD6 PD3 PC12 PA9 PA11

PH1-
D VDD PE5 PE0 BOOT0 PD7 PD4 PD0 PA8 PA10
OSC_OUT

E NRST PC2_C PE6 VSS VSS VSS VCAP PD1 PC9 PC7

F PC0 PC1 PC3_C VDD VDD VDD33USB PDR_ON VCAP PC8 PC6

G VSSA PA0 PA4 PC4 PB2 PE10 PE14 PD15 PD11 PB15

H VDDA PA1 PA5 PC5 PE7 PE11 PE15 PD14 PD10 PB14

J VSS PA2 PA6 PB0 PE8 PE12 PB10 PB13 PD9 PD13

K VDD PA3 PA7 PB1 PE9 PE13 PB11 PB12 PD8 PD12

MSv52520V1.

1. The above figure shows the package top view.

DS13315 Rev 3 57/270

102
Pinouts, pin descriptions and alternate functions STM32H730xB

Figure 5. LQFP100 pinout (without SMPS)

BOOT0

PC10
PC12
PC11

PA14
PA15
VDD
VSS

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PE0
PE1
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 VDD
PE3 2 74 VSS
PE4 3 73 VCAP
PE5 4 72 PA13
PE6 5 71 PA12
VBAT 6 70 PA11
PC13 7 69 PA10
PC14-OSC32_IN 8 68 PA9
PC15-OSC32_OUT 9 67 PA8
VSS 10 66 PC9
VDD 11 65 PC8
PH0-OSC_IN 12 64 PC7
PH1-OSC_OUT 13 LQFP100 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2_C 17 59 PD12
PC3_C 18 58 PD11
VSSA 19 57 PD10
VREF+ 20 56 PD9
VDDA 21 55 PD8
PA0 22 54 PB15
PA1 23 53 PB14
PA2 24 52 PB13
PA3 25 51 PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDD
VSS
VCAP
PB10
PE15
PE14
PE13
PE12
PE10
PE9
PE8
PE7
PB2
PB1
PB0
PC5
PC4
VDD
VSS

PB11
PE11
PA7
PA6
PA5
PA4

MSv52521V1.

1. The above figure shows the package top view.

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Figure 6. TFBGA144 ballout (without SMPS)

1 2 3 4 5 6 7 8 9 10 11 12

A A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12

B B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12

C C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12

D D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12

E E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12

F F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12

G G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12

H H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12

J J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12

K K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12

L L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12

M M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12

MSv65136V1

1. The above figure shows the package top view.

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Figure 7. LQFP144 pinout (without SMPS)

PDR_ON

BOOT0

PG15

PG14
PG13
PG12

PG10

PC12

PC10
PG11

PC11

PA15
PA14
VDD

VDD

VDD
VSS

PG9

VSS
PD7
PD6

PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8

PB7
PB6
PB5
PB4
PB3
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120

109
119
118
117
116
115
114
113
112

110
111
PE2 1 108 VDD
PE3 2 107 VSS
PE4 3 106 VCAP
PE5 4 105 PA13
PE6 5 104 PA12
VBAT 6 103 PA11
PC13 7 102 PA10
PC14-OSC32_IN 8 101 PA9
PC15-OSC32_OUT 9 100 PA8
PF0 10 99 PC9
PF1 11 98 PC8
PF2 12 97 PC7
PF3 13 96 PC6
PF4 14 95 VDD33USB
PF5 15 94 VSS
VSS 16 93 PG8
VDD 17 92 PG7
PF6 18 91 PG6
PF7 19 LQFP144 90 PG5
PF8 20 89 PG4
PF9 21 88 PG3
PF10 22 87 PG2
PH0-OSC_IN 23 86 PD15
PH1-OSC_OUT 24 85 PD14
NRST 25 84 VDD
PC0 26 83 VSS
PC1 27 82 PD13
PC2_C 28 81 PD12
PC3_C 29 80 PD11
VDD 30 79 PD10
VSSA 31 78 PD9
VREF+ 32 77 PD8
VDDA 33 76 PB15
PA0 34 75 PB14
PA1 35 74 PB13
PA2 36 73 PB12
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VSS

PG0
PG1
VDD

PC4
PC5
PB0
PB1
PB2

PF12
VSS
VDD
PF13
PF14
PF15

PE7
PE8
PE9
VSS
VDD
PE10

PE12
PE13
PE14
PE15
PB10

VCAP
VDD
PA3

PA4
PA5
PA6
PA7

PF11

PE11

PB11

MSv52522V1.

1. The above figure shows the package top view.

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Figure 8. LQFP176 pinout (with SMPS)

VDDLDO
PDR_ON

VDDLDO
BOOT0
VCAP

VCAP
PG12

PG10
PG11
PG15

PG14
PG13

PC12

PC10
PC11

PA15
PA14
VDD

VDD
VDD

VDD
VSS

PG9

VSS
PD7
PD6
PD5
PD4
PD3
PD2
VSS

VSS

VSS
PE1
PE0
PB9

PD1
PD0
PB8

PB7
PB6
PB5
PB4
PB3
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PE2 1 132 PA13
PE3 2 131 PA12
PE4 3 130 PA11
PE5 4 129 PA10
PE6 5 128 PA9
VSS 6 127 PA8
VDD 7 126 VDD
VBAT 8 125 PC9
PC13 9 124 PC8
PC14-OSC32_IN 10 123 PC7
PC15-OSC32_OUT 11 122 PC6
VSS 12 121 VDD33USB
VDD 13 120 VDD50USB
VSSSMPS 14 119 VSS
VLXSMPS 15 118 PG8
VDDSMPS 16 117 PG7
VFBSMPS 17 116 PG6
PF0 18 115 PG5
PF1 19 114 PG4
PF2 20 113 VDD
PF3 21 112 VSS
PF4 22 111 PG3
PF5 23 LQFP176 110 PG2
VSS 24 109 PK2
VDD 25 108 PK1
PF6 26 107 PK0
PF7 27 106 VSS
PF8 28 105 VDD
PF9 29 104 PJ11
PF10 30 103 PJ10
PH0-OSC_IN 31 102 PJ9
PH1-OSC_OUT 32 101 PJ8
NRST 33 100 VSS
PC0 34 99 VDD
PC1 35 98 PD15
PC2_C 36 97 PD14
PC3_C 37 96 PD13
VSSA 38 95 PD12
VREF+ 39 94 PD11
VDDA 40 93 VSS
PA0 41 92 VDD
PA1 42 91 PD10
PA2 43 90 PD9
VDD 44 89 PD8
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
VSS

VSS
VDD

PC4
PC5
PB0
PB1
PB2

PF12
PF13
PF14
PF15
PG0
VSS
VDD
PG1
PE7
PE8
PE9
VSS
VDD
PE10

PE12
PE13
PE14
PE15
PB10

VCAP
VSS
VDDLDO
VSS
VDD
PB12
PB13
PB14
PB15
PA3

PA4
PA5
PA6
PA7

PF11

PE11

PB11

MSv52553V1.

1. The above figure shows the package top view.

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Figure 9. UFBGA169 ballout (with SMPS)

1 2 3 4 5 6 7 8 9 10 11 12 13

A PE4 PE2 VDD VCAP PB6 VDD VDD PG10 PD5 VDD PC12 PC10 PH14

PC15-
B PE3 VSS VDDLDO PB8 PB4 VSS PG11 PD6 VSS PC11 PA14 PH13
OSC32_OUT

PC14-
C PE6 PE5 PDR_ON PB9 PB5 PG14 PG9 PD4 PD1 PA15 VSS VDD
OSC32_IN

D VDD VSS PC13 PE1 PE0 PB7 PG13 PD7 PD3 PD0 PA13 VDDLDO VCAP

E VLXSMPS VSSSMPS VBAT PF1 PF3 BOOT0 PG15 PG12 PD2 PA10 PA9 PA8 PA12

F VDDSMPS VFBSMPS PF0 PF2 PF5 PF7 PB3 PG4 PC6 PC7 PC9 PC8 PA11

G VDD VSS PF4 PF6 PF9 NRST PF13 PE7 PG6 PG7 PG8 VDD50USB VDD33USB

PH1-
H PH0-OSC_IN PF10 PF8 PC2 PA4 PF14 PE8 PG2 PG3 PG5 VSS VDD
OSC_OUT

J PC0 PC1 VSSA PC3 PA0 PA7 PF15 PE9 PE14 PD11 PD13 PD15 PD14

K PC3_C PC2_C PA0_C PA1 PA6 PC4 PG0 PE13 PH10 PH12 PD9 PD10 PD12

L VDDA VREF+ PA1_C PA5 PB1 PB2 PG1 PE12 PB10 PH11 PB13 VSS VDD

M VDD VSS PH3 VSS PB0 PF11 VSS PE10 PB11 VDDLDO VSS PD8 PB15

N PA2 PH2 PA3 VDD PC5 PF12 VDD PE11 PE15 VCAP VDD PB12 PB14

MSv52551V1.

1. The above figure shows the package top view.

Figure 10. UFBGA176+25 ballout (with SMPS)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

A VSS PB8 VDDLDO VCAP PB6 PB3 PG11 PG9 PD3 PD1 PA15 PA14 VDDLDO VCAP VSS

B PE4 PE3 PB9 PE0 PB7 PB4 PG13 PD7 PD5 PD2 PC12 PH14 PA13 PA8 PA12

C PC13 VSS PE2 PE1 BOOT0 PB5 PG14 PG10 PD4 PD0 PC11 PC10 PH13 PA10 PA11

PC15- PC14-
D PE5 PDR_ON VDD VSS PG15 PG12 PD6 VSS VDD PH15 PA9 PC8 PC7
OSC32_OUT OSC32_IN

E VSS VBAT PE6 VDD VDD PC9 PC6 VDD50USB

F VLXSMPS VSSSMPS PF1 PF0 VSS VSS VSS VSS VSS VSS VDD33USB PG6 PG5

G VDDSMPS VFBSMPS PF2 VDD VSS VSS VSS VSS VSS PG8 PG7 PG4 PG2

H PF6 PF4 PF5 PF3 VSS VSS VSS VSS VSS VDD PG3 PD14 PD13

J PH0-OSC_IN PF8 PF7 PF9 VSS VSS VSS VSS VSS PD15 PD11 VSS PD12

PH1-
K VSS PF10 VDD VSS VSS VSS VSS VSS VSS PD9 PB15 PB14
OSC_OUT

L NRST PC0 PC1 VREF- VDD PD10 PD8 PB13

M PC2 PC3 VREF+ VDDA VDD VSS PC5 PB1 VDD VSS PH7 PE14 PH11 PH9 PB12

N PC2_C PC3_C VSSA PH2 PA3 PA7 PF11 PE8 PG1 PF15 PF13 PB10 PH8 PH10 PH12

P PA0 PA1 PA1_C PH4 PA4 PA5 PB2 PG0 PE7 PB11 PF12 PE12 PE13 PE15 PH6

R VSS PA2 PA0_C PH3 PH5 PC4 PA6 PB0 PE10 PF14 PE9 PE11 VCAP VDDLDO VSS

MSv52552V1.

1. The above figure shows the package top view.

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Table 6. Legend/abbreviations used in the pinout table

Name Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during
Pin name
and after reset is the same as the actual pin name
S Supply pin
I Input only pin
Pin type
I/O Input / output pin
ANA Analog-only Input
FT 5 V tolerant I/O
TT 3.3 V tolerant I/O
B Dedicated BOOT0 pin
RST Bidirectional reset pin with embedded weak pull-up resistor

I/O structure Option for TT and FT I/Os

_f I2C FM+ option

_a analog option (supplied by VDDA)
_u USB option (supplied by VDD33USB)
_h High-speed low-voltage I/O
Unless otherwise specified by a note, all I/Os are set as floating inputs during and
Notes
after reset.
Alternate
Functions selected through GPIOx_AFR registers
functions
Pin functions
Additional
Functions directly selected/enabled through peripheral registers
functions

DS13315 Rev 3 63/270

102
Pinouts, pin descriptions and alternate functions STM32H730xB

Table 7. STM32H730xB pin and ball descriptions

Pin Number

I/O structure
UFBGA176+25

Pin type
Pin name

Notes
UFBGA144

UFBGA169
TFBGA100

Additional
LQFP100

LQFP144

LQFP176
(function after Alternate functions
functions
reset)

TRACECLK, SAI1_CK1,
USART10_RX, SPI4_SCK,
SAI1_MCLK_A,
FT
A3 1 1 A3 A2 C3 1 PE2 I/O - SAI4_MCLK_A, -
_h
OCTOSPIM_P1_IO2,
SAI4_CK1, ETH_MII_TXD3,
FMC_A23, EVENTOUT

TRACED0, TIM15_BKIN,
FT SAI1_SD_B, SAI4_SD_B,
B3 2 2 A2 B2 B2 2 PE3 I/O - -
_h USART10_TX, FMC_A19,
EVENTOUT

TRACED1, SAI1_D2,
DFSDM1_DATIN3,
TIM15_CH1N, SPI4_NSS,
FT
C3 3 3 B2 A1 B1 3 PE4 I/O - SAI1_FS_A, SAI4_FS_A, -
_h
SAI4_D2, FMC_A20,
DCMI_D4/PSSI_D4, LCD_B0,
EVENTOUT
TRACED2, SAI1_CK2,
DFSDM1_CKIN3, TIM15_CH1,
SPI4_MISO, SAI1_SCK_A,
FT
D3 4 4 B3 C3 D3 4 PE5 I/O - SAI4_SCK_A, SAI4_CK2, -
_h
FMC_A21,
DCMI_D6/PSSI_D6, LCD_G0,
EVENTOUT

TRACED3, TIM1_BKIN2,
SAI1_D1, TIM15_CH2,
SPI4_MOSI, SAI1_SD_A,
SAI4_SD_A, SAI4_D1,
FT
E3 5 5 B4 C2 E3 5 PE6 I/O - SAI4_MCLK_B, -
_h
TIM1_BKIN2_COMP12,
FMC_A22,
DCMI_D7/PSSI_D7, LCD_G1,
EVENTOUT
- - - - - - 6 VSS S - - - -

- - - - - - 7 VDD S - - - -

B2 6 6 C2 E3 E2 8 VBAT S - - - -
RTC_TAMP1/
A2 7 7 A1 D3 C1 9 PC13 I/O FT - EVENTOUT
RTC_TS, WKUP4

A1 8 8 B1 C1 D2 10 PC14-OSC32_IN I/O FT - EVENTOUT OSC32_IN

64/270 DS13315 Rev 3

STM32H730xB Pinouts, pin descriptions and alternate functions

Table 7. STM32H730xB pin and ball descriptions (continued)

Pin Number

I/O structure
UFBGA176+25

Pin type
Pin name

Notes
UFBGA144

UFBGA169
TFBGA100

Additional
LQFP100

LQFP144

LQFP176
(function after Alternate functions
functions
reset)

PC15-
B1 9 9 C1 B1 D1 11 I/O FT - EVENTOUT OSC32_OUT
OSC32_OUT

- - - - - - 12 VSS S - - - -

- - - - - - 13 VDD S - - - -

- - - - E2 F2 14 VSSSMPS S - - - -
- - - - E1 F1 15 VLXSMPS S - - - -

- - - - F1 G1 16 VDDSMPS S - - - -

- - - - F2 G2 17 VFBSMPS S - - - -
I2C2_SDA(boot), I2C5_SDA,
FT OCTOSPIM_P2_IO0,
- - 10 C3 F3 F4 18 PF0 I/O - -
_fh FMC_A0, TIM23_CH1,
EVENTOUT

I2C2_SCL(boot), I2C5_SCL,
FT OCTOSPIM_P2_IO1,
- - 11 C4 E4 F3 19 PF1 I/O - -
_fh FMC_A1, TIM23_CH2,
EVENTOUT

I2C2_SMBA, I2C5_SMBA,
FT OCTOSPIM_P2_IO2,
- - 12 D4 F4 G3 20 PF2 I/O - -
_h FMC_A2, TIM23_CH3,
EVENTOUT

OCTOSPIM_P2_IO3,
FT
- - 13 E2 E5 H4 21 PF3 I/O - FMC_A3, TIM23_CH4, ADC3_INP5
_ha
EVENTOUT

FT OCTOSPIM_P2_CLK, ADC3_INN5,
- - 14 E3 G3 H2 22 PF4 I/O -
_ha FMC_A4, EVENTOUT ADC3_INP9

FT OCTOSPIM_P2_NCLK,
- - 15 E4 F5 H3 23 PF5 I/O - ADC3_INP4
_ha FMC_A5, EVENTOUT

- 10 16 - - - 24 VSS S - - - -

- 11 17 - - - 25 VDD S - - - -

TIM16_CH1, FDCAN3_RX,
SPI5_NSS, SAI1_SD_B,
FT ADC3_INN4,
- - 18 F3 G4 H1 26 PF6 I/O - UART7_RX, SAI4_SD_B,
_ha ADC3_INP8
OCTOSPIM_P1_IO3,
TIM23_CH1, EVENTOUT

DS13315 Rev 3 65/270

102
Pinouts, pin descriptions and alternate functions STM32H730xB

Table 7. STM32H730xB pin and ball descriptions (continued)

Pin Number

I/O structure
UFBGA176+25

Pin type
Pin name

Notes
UFBGA144

UFBGA169
TFBGA100

Additional
LQFP100

LQFP144

LQFP176
(function after Alternate functions
functions
reset)

TIM17_CH1, FDCAN3_TX,
SPI5_SCK, SAI1_MCLK_B,
FT
- - 19 F2 F6 J3 27 PF7 I/O - UART7_TX, SAI4_MCLK_B, ADC3_INP3
_ha
OCTOSPIM_P1_IO2,
TIM23_CH2, EVENTOUT
TIM16_CH1N, SPI5_MISO,
SAI1_SCK_B,
FT UART7_RTS/UART7_DE, ADC3_INN3,
- - 20 G3 H4 J2 28 PF8 I/O -
_ha SAI4_SCK_B, TIM13_CH1, ADC3_INP7
OCTOSPIM_P1_IO0,
TIM23_CH3, EVENTOUT
TIM17_CH1N, SPI5_MOSI,
SAI1_FS_B, UART7_CTS,
FT
- - 21 G2 G5 J4 29 PF9 I/O - SAI4_FS_B, TIM14_CH1, ADC3_INP2
_ha
OCTOSPIM_P1_IO1,
TIM23_CH4, EVENTOUT

TIM16_BKIN, SAI1_D3,
PSSI_D15,
FT OCTOSPIM_P1_CLK, ADC3_INN2,
- - 22 G1 H3 K3 30 PF10 I/O -
_ha SAI4_D3, ADC3_INP6
DCMI_D11/PSSI_D11,
LCD_DE, EVENTOUT

C1 12 23 D1 H1 J1 31 PH0-OSC_IN I/O FT - EVENTOUT OSC_IN

D1 13 24 E1 H2 K1 32 PH1-OSC_OUT I/O FT - EVENTOUT OSC_OUT

RS
E1 14 25 F1 G6 L1 33 NRST I/O - - -
T

FMC_D12/FMC_AD12,
DFSDM1_CKIN0,
DFSDM1_DATIN4,
FT
F1 15 26 H1 J1 L2 34 PC0 I/O - SAI4_FS_B, FMC_A25, ADC123_INP10
_ha
OTG_HS_ULPI_STP,
LCD_G2, FMC_SDNWE,
LCD_R5, EVENTOUT
TRACED0, SAI4_D1,
SAI1_D1, DFSDM1_DATIN0,
DFSDM1_CKIN4,
ADC123_INN10,
SPI2_MOSI/I2S2_SDO,
FT ADC123_INP11,
F2 16 27 H2 J2 L3 35 PC1 I/O - SAI1_SD_A, SAI4_SD_A,
_ha RTC_TAMP3,
SDMMC2_CK,
WKUP6
OCTOSPIM_P1_IO4,
ETH_MDC, MDIOS_MDC,
LCD_G5, EVENTOUT

66/270 DS13315 Rev 3

STM32H730xB Pinouts, pin descriptions and alternate functions

Table 7. STM32H730xB pin and ball descriptions (continued)

Pin Number

I/O structure
UFBGA176+25

Pin type
Pin name

Notes
UFBGA144

UFBGA169
TFBGA100

Additional
LQFP100

LQFP144

LQFP176
(function after Alternate functions
functions
reset)

PWR_DEEPSLEEP,
DFSDM1_CKIN1,
OCTOSPIM_P1_IO5,
SPI2_MISO/I2S2_SDI,
H5 M1 FT ADC123_INN11,
- - - H3 (1) (1) - PC2 I/O - DFSDM1_CKOUT,
_a ADC123_INP12
OCTOSPIM_P1_IO2,
OTG_HS_ULPI_DIR,
ETH_MII_TXD2,
FMC_SDNE0, EVENTOUT

E2 17 28 K2 N1 36 AN TT ADC3_INN1,
(2) (2) (2) - (1) (1) (2) PC2_C - -
A _a ADC3_INP0

PWR_SLEEP,
DFSDM1_DATIN1,
OCTOSPIM_P1_IO6,
J4 M2 FT SPI2_MOSI/I2S2_SDO, ADC12_INN12,
- - - H4 (1) (1) - PC3 I/O -
_a OCTOSPIM_P1_IO0, ADC12_INP13
OTG_HS_ULPI_NXT,
ETH_MII_TX_CLK,
FMC_SDCKE0, EVENTOUT

F3 18 29 K1 N2 37 AN TT
(2) (2) (2) - (1) (1) (2) PC3_C - - ADC3_INP1
A _a

- - 30 - - - - VDD S - - - -

G1 19 31 J1 J3 N3 38 VSSA S - - - -

- - - K1 - L4 - VREF- S - - - -

- 20 32 L1 L2 M3 39 VREF+ S - - - -

H1 21 33 M1 L1 M4 40 VDDA S - - - -

TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
TIM15_BKIN,
J5 P1 FT SPI6_NSS/I2S6_WS, ADC1_INP16,
G2 22 34 J2 (1) (1) 41 PA0 I/O -
_ha USART2_CTS/USART2_NSS, WKUP1
UART4_TX, SDMMC2_CMD,
SAI4_SD_B, ETH_MII_CRS,
FMC_A19, EVENTOUT

K3 R3 AN TT ADC12_INN1,
- - - - (1) (1) - PA0_C - -
A _a ADC12_INP0

DS13315 Rev 3 67/270

102
Pinouts, pin descriptions and alternate functions STM32H730xB

Table 7. STM32H730xB pin and ball descriptions (continued)

Pin Number

I/O structure
UFBGA176+25

Pin type
Pin name

Notes
UFBGA144

UFBGA169
TFBGA100

Additional
LQFP100

LQFP144

LQFP176
(function after Alternate functions
functions
reset)

TIM2_CH2, TIM5_CH2,
LPTIM3_OUT, TIM15_CH1N,
USART2_RTS/USART2_DE,
UART4_RX,
K4 P2 FT OCTOSPIM_P1_IO3, ADC1_INN16,
H2 23 35 K2 (1) (1) 42 PA1 I/O -
_ha SAI4_MCLK_B, ADC1_INP17
ETH_MII_RX_CLK/ETH_RMII
_REF_CLK,
OCTOSPIM_P1_DQS,
LCD_R2, EVENTOUT

L3 P3 AN TT
- - - - (1) (1) - PA1_C - - ADC12_INP1
A _a

TIM2_CH3, TIM5_CH3,
LPTIM4_OUT, TIM15_CH1,
OCTOSPIM_P1_IO0,
FT ADC12_INP14,
J2 24 36 L2 N1 R2 43 PA2 I/O - USART2_TX(boot),
_ha WKUP2
SAI4_SCK_B, ETH_MDIO,
MDIOS_MDIO, LCD_R1,
EVENTOUT

LPTIM1_IN2,
OCTOSPIM_P1_IO4,
FT
- - - - N2 N4 - PH2 I/O - SAI4_SCK_B, ETH_MII_CRS, ADC3_INP13
_ha
FMC_SDCKE0, LCD_R0,
EVENTOUT

- - - - - - 44 VDD S - - - -

- - - - - - 45 VSS S - - - -

OCTOSPIM_P1_IO5,
FT SAI4_MCLK_B, ADC3_INN13,
- - - - M3 R4 - PH3 I/O -
_ha ETH_MII_COL, FMC_SDNE0, ADC3_INP14
LCD_R1, EVENTOUT
I2C2_SCL, LCD_G5,
FT OTG_HS_ULPI_NXT, ADC3_INN14,
- - - - - P4 - PH4 I/O -
_fa PSSI_D14, LCD_G4, ADC3_INP15
EVENTOUT

FT
I2C2_SDA, SPI5_NSS, ADC3_INN15,
- - - - - R5 - PH5 I/O _fh -
FMC_SDNWE, EVENTOUT ADC3_INP16
a

68/270 DS13315 Rev 3

STM32H730xB Pinouts, pin descriptions and alternate functions

Table 7. STM32H730xB pin and ball descriptions (continued)

Pin Number

I/O structure
UFBGA176+25

Pin type
Pin name

Notes
UFBGA144

UFBGA169
TFBGA100

Additional
LQFP100

LQFP144

LQFP176
(function after Alternate functions
functions
reset)

TIM2_CH4, TIM5_CH4,
LPTIM5_OUT, TIM15_CH2,
I2S6_MCK,
OCTOSPIM_P1_IO2,
FT
K2 25 37 M2 N3 N5 46 PA3 I/O - USART2_RX(boot), LCD_B2, ADC12_INP15
_ha
OTG_HS_ULPI_D0,
ETH_MII_COL,
OCTOSPIM_P1_CLK,
LCD_B5, EVENTOUT

- 26 38 - - - 47 VSS S - - - -

- 27 39 - - - 48 VDD S - - - -
D1PWREN, TIM5_ETR,
SPI1_NSS(boot)/I2S1_WS,
SPI3_NSS/I2S3_WS,
TT USART2_CK, ADC12_INP18,
G3 28 40 J3 H6 P5 49 PA4 I/O -
_ha SPI6_NSS/I2S6_WS, DAC1_OUT1
FMC_D8/FMC_AD8,
DCMI_HSYNC/PSSI_DE,
LCD_VSYNC, EVENTOUT

D2PWREN,
TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
SPI1_SCK(boot)/I2S1_CK, ADC12_INN18,
TT
H3 29 41 K3 L4 P6 50 PA5 I/O - SPI6_SCK/I2S6_CK, ADC12_INP19,
_ha
OTG_HS_ULPI_CK, DAC1_OUT2
FMC_D9/FMC_AD9,
PSSI_D14, LCD_R4,
EVENTOUT

TIM1_BKIN, TIM3_CH1,
TIM8_BKIN,
SPI1_MISO(boot)/I2S1_SDI,
OCTOSPIM_P1_IO3,
SPI6_MISO/I2S6_SDI,
FT
J3 30 42 L3 K5 R7 51 PA6 I/O - TIM13_CH1, ADC12_INP3
_ha
TIM8_BKIN_COMP12,
MDIOS_MDC,
TIM1_BKIN_COMP12,
DCMI_PIXCLK/PSSI_PDCK,
LCD_G2, EVENTOUT

DS13315 Rev 3 69/270

102
Pinouts, pin descriptions and alternate functions STM32H730xB

Table 7. STM32H730xB pin and ball descriptions (continued)

Pin Number

I/O structure
UFBGA176+25

Pin type
Pin name

Notes
UFBGA144

UFBGA169
TFBGA100

Additional
LQFP100

LQFP144

LQFP176
(function after Alternate functions
functions
reset)

TIM1_CH1N, TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI(boot)/I2S1_SDO,
SPI6_MOSI/I2S6_SDO, ADC12_INN3,
TT
K3 31 43 M3 J6 N6 52 PA7 I/O - TIM14_CH1, ADC12_INP7,
_ha
OCTOSPIM_P1_IO2, OPAMP1_VINM
ETH_MII_RX_DV/ETH_RMII_
CRS_DV, FMC_SDNWE,
LCD_VSYNC, EVENTOUT

PWR_DEEPSLEEP,
FMC_A22, DFSDM1_CKIN2,
I2S1_MCK, SPDIFRX1_IN3, ADC12_INP4,
TT
G4 32 44 J4 K6 R6 53 PC4 I/O - SDMMC2_CKIN, OPAMP1_VOUT,
_ha
ETH_MII_RXD0/ETH_RMII_R COMP1_INM
XD0, FMC_SDNE0, LCD_R7,
EVENTOUT

PWR_SLEEP, SAI4_D3,
SAI1_D3, DFSDM1_DATIN2,
PSSI_D15, SPDIFRX1_IN4,
ADC12_INN4,
TT OCTOSPIM_P1_DQS,
H4 33 45 K4 N5 M7 54 PC5 I/O - ADC12_INP8,
_ha ETH_MII_RXD1/ETH_RMII_R
OPAMP1_VINM
XD1, FMC_SDCKE0,
COMP1_OUT, LCD_DE,
EVENTOUT
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N,
OCTOSPIM_P1_IO1, ADC12_INN5,
TT DFSDM1_CKOUT, ADC12_INP9,
J4 34 46 L4 M5 R8 55 PB0 I/O -
_ha UART4_CTS, LCD_R3, OPAMP1_VINP,
OTG_HS_ULPI_D1, COMP1_INP
ETH_MII_RXD2, LCD_G1,
EVENTOUT

TIM1_CH3N, TIM3_CH4,
TIM8_CH3N,
OCTOSPIM_P1_IO0,
FT ADC12_INP5,
K4 35 47 M4 L5 M8 56 PB1 I/O - DFSDM1_DATIN1, LCD_R6,
_ha COMP1_INM
OTG_HS_ULPI_D2,
ETH_MII_RXD3, LCD_G0,
EVENTOUT

70/270 DS13315 Rev 3

STM32H730xB Pinouts, pin descriptions and alternate functions

Table 7. STM32H730xB pin and ball descriptions (continued)

Pin Number

I/O structure
UFBGA176+25

Pin type
Pin name

Notes
UFBGA144

UFBGA169
TFBGA100

Additional
LQFP100

LQFP144

LQFP176
(function after Alternate functions
functions
reset)

RTC_OUT, SAI4_D1,
SAI1_D1, DFSDM1_CKIN1,
SAI1_SD_A,
SPI3_MOSI/I2S3_SDO,
FT
G5 36 48 J5 L6 P7 57 PB2 I/O - SAI4_SD_A, COMP1_INP
_ha
OCTOSPIM_P1_CLK,
OCTOSPIM_P1_DQS,
ETH_TX_ER, TIM23_ETR,
EVENTOUT

SPI5_MOSI,
OCTOSPIM_P1_NCLK,
FT
- - 49 M5 M6 N7 58 PF11 I/O - SAI4_SD_B, FMC_NRAS, ADC1_INP2
_ha
DCMI_D12/PSSI_D12,
TIM24_CH1, EVENTOUT
OCTOSPIM_P2_DQS,
FT ADC1_INN2,
- - 50 L5 N6 P11 59 PF12 I/O - FMC_A6, TIM24_CH2,
_ha ADC1_INP6
EVENTOUT

- - 51 - - - - VSS S - - - -

- - 52 - - - - VDD S - - - -

DFSDM1_DATIN6,
FT
- - 53 K5 G7 N11 60 PF13 I/O - I2C4_SMBA, FMC_A7, ADC2_INP2
_ha
TIM24_CH3, EVENTOUT

FT DFSDM1_CKIN6, I2C4_SCL,
ADC2_INN2,
- - 54 M6 H7 R10 61 PF14 I/O _fh - FMC_A8, TIM24_CH4,
ADC2_INP6
a EVENTOUT

FT I2C4_SDA, FMC_A9,
- - 55 L6 J7 N10 62 PF15 I/O - -
_fh EVENTOUT
OCTOSPIM_P2_IO4,
FT
- - 56 K6 K7 P8 63 PG0 I/O - UART9_RX, FMC_A10, -
_h
EVENTOUT

- - - - - - 64 VSS S - - - -

- - - - - - 65 VDD S - - - -

OCTOSPIM_P2_IO5,
TT
- - 57 J6 L7 N9 66 PG1 I/O - UART9_TX, FMC_A11, OPAMP2_VINM
_h
EVENTOUT

TIM1_ETR, DFSDM1_DATIN2,
UART7_RX,
TT OPAMP2_VOUT,
H5 37 58 M7 G8 P9 67 PE7 I/O - OCTOSPIM_P1_IO4,
_ha COMP2_INM
FMC_D4/FMC_AD4,
EVENTOUT

DS13315 Rev 3 71/270

102
Pinouts, pin descriptions and alternate functions STM32H730xB

Table 7. STM32H730xB pin and ball descriptions (continued)

Pin Number

I/O structure
UFBGA176+25

Pin type
Pin name

Notes
UFBGA144

UFBGA169
TFBGA100

Additional
LQFP100

LQFP144

LQFP176
(function after Alternate functions
functions
reset)

TIM1_CH1N,
DFSDM1_CKIN2, UART7_TX,
TT
J5 38 59 L7 H8 N8 68 PE8 I/O - OCTOSPIM_P1_IO5, OPAMP2_VINM
_ha
FMC_D5/FMC_AD5,
COMP2_OUT, EVENTOUT
TIM1_CH1, DFSDM1_CKOUT,
UART7_RTS/UART7_DE,
TT OPAMP2_VINP,
K5 39 60 K7 J8 R11 69 PE9 I/O - OCTOSPIM_P1_IO6,
_ha COMP2_INP
FMC_D6/FMC_AD6,
EVENTOUT

- - 61 - - - 70 VSS S - - - -

- - 62 - - - 71 VDD S - - - -

TIM1_CH2N,
DFSDM1_DATIN4,
FT UART7_CTS,
G6 40 63 J7 M8 R9 72 PE10 I/O - COMP2_INM
_ha OCTOSPIM_P1_IO7,
FMC_D7/FMC_AD7,
EVENTOUT

TIM1_CH2, DFSDM1_CKIN4,
SPI4_NSS(boot), SAI4_SD_B,
FT
H6 41 64 H8 N8 R12 73 PE11 I/O - OCTOSPIM_P1_NCS, COMP2_INP
_ha
FMC_D8/FMC_AD8, LCD_G3,
EVENTOUT

TIM1_CH3N,
DFSDM1_DATIN5,
SPI4_SCK(boot),
FT
J6 42 65 J8 L8 P12 74 PE12 I/O - SAI4_SCK_B, -
_h
FMC_D9/FMC_AD9,
COMP1_OUT, LCD_B4,
EVENTOUT
TIM1_CH3, DFSDM1_CKIN5,
SPI4_MISO(boot),
FT SAI4_FS_B,
K6 43 66 K8 K8 P13 75 PE13 I/O - -
_h FMC_D10/FMC_AD10,
COMP2_OUT, LCD_DE,
EVENTOUT
TIM1_CH4, SPI4_MOSI(boot),
FT SAI4_MCLK_B,
G7 44 67 L8 J9 M12 76 PE14 I/O - -
_h FMC_D11/FMC_AD11,
LCD_CLK, EVENTOUT

72/270 DS13315 Rev 3

STM32H730xB Pinouts, pin descriptions and alternate functions

Table 7. STM32H730xB pin and ball descriptions (continued)

Pin Number

I/O structure
UFBGA176+25

Pin type
Pin name

Notes
UFBGA144

UFBGA169
TFBGA100

Additional
LQFP100

LQFP144

LQFP176
(function after Alternate functions
functions
reset)

TIM1_BKIN, USART10_CK,
FT FMC_D12/FMC_AD12,
H7 45 68 M8 N9 P14 77 PE15 I/O - -
_h TIM1_BKIN_COMP12,
LCD_R7, EVENTOUT

TIM2_CH3, LPTIM2_IN1,
I2C2_SCL,
SPI2_SCK/I2S2_CK,
DFSDM1_DATIN7,
FT
J7 46 69 M9 L9 N12 78 PB10 I/O - USART3_TX(boot), -
_fh
OCTOSPIM_P1_NCS,
OTG_HS_ULPI_D3,
ETH_MII_RX_ER, LCD_G4,
EVENTOUT

TIM2_CH4, LPTIM2_ETR,
I2C2_SDA, DFSDM1_CKIN7,
FT USART3_RX(boot),
K7 47 70 M10 M9 P10 79 PB11 I/O - -
_f OTG_HS_ULPI_D4,
ETH_MII_TX_EN/ETH_RMII_T
X_EN, LCD_G5, EVENTOUT

F8 48 71 H7 N10 R13 80 VCAP S - - - -

- 49 - - - - 81 VSS S - - - -

- - - - M10 R14 82 VDDLDO S - - - -

- 50 72 - - - - VDD S - - - -

TIM12_CH1, I2C2_SMBA,
SPI5_SCK, ETH_MII_RXD2,
FT
- - - - - P15 - PH6 I/O - FMC_SDNE1, -
_h
DCMI_D8/PSSI_D8,
EVENTOUT

I2C3_SCL, SPI5_MISO,
ETH_MII_RXD3,
FT
- - - - - M11 - PH7 I/O - FMC_SDCKE1, -
_fh
DCMI_D9/PSSI_D9,
EVENTOUT
TIM5_ETR, I2C3_SDA,
FT FMC_D16,
- - - - - N13 - PH8 I/O - -
_fh DCMI_HSYNC/PSSI_DE,
LCD_R2, EVENTOUT

TIM12_CH2, I2C3_SMBA,
FT FMC_D17,
- - - - - M14 - PH9 I/O - -
_h DCMI_D0/PSSI_D0, LCD_R3,
EVENTOUT

DS13315 Rev 3 73/270

102
Pinouts, pin descriptions and alternate functions STM32H730xB

Table 7. STM32H730xB pin and ball descriptions (continued)

Pin Number

I/O structure
UFBGA176+25

Pin type
Pin name

Notes
UFBGA144

UFBGA169
TFBGA100

Additional
LQFP100

LQFP144

LQFP176
(function after Alternate functions
functions
reset)

TIM5_CH1, I2C4_SMBA,
FT FMC_D18,
- - - - K9 N14 - PH10 I/O - -
_h DCMI_D1/PSSI_D1, LCD_R4,
EVENTOUT

TIM5_CH2, I2C4_SCL,
FT FMC_D19,
- - - - L10 M13 - PH11 I/O - -
_fh DCMI_D2/PSSI_D2, LCD_R5,
EVENTOUT

- - - - - - 83 VSS S - - - -

- - - - - - 84 VDD S - - - -

TIM5_CH3, I2C4_SDA,
FT FMC_D20,
- - - - K10 N15 - PH12 I/O - -
_fh DCMI_D3/PSSI_D3, LCD_R6,
EVENTOUT
TIM1_BKIN,
OCTOSPIM_P1_NCLK,
I2C2_SMBA,
SPI2_NSS/I2S2_WS,
DFSDM1_DATIN1,
FT
K8 51 73 M11 N12 M15 85 PB12 I/O - USART3_CK, FDCAN2_RX, -
_h
OTG_HS_ULPI_D5,
ETH_MII_TXD0/ETH_RMII_TX
D0, OCTOSPIM_P1_IO0,
TIM1_BKIN_COMP12,
UART5_RX, EVENTOUT

TIM1_CH1N, LPTIM2_OUT,
OCTOSPIM_P1_IO2,
SPI2_SCK/I2S2_CK,
DFSDM1_CKIN1,
USART3_CTS/USART3_NSS,
FT
J8 52 74 M12 L11 L15 86 PB13 I/O - FDCAN2_TX, -
_h
OTG_HS_ULPI_D6,
ETH_MII_TXD1/ETH_RMII_TX
D1, SDMMC1_D0,
DCMI_D2/PSSI_D2,
UART5_TX, EVENTOUT

74/270 DS13315 Rev 3

STM32H730xB Pinouts, pin descriptions and alternate functions

Table 7. STM32H730xB pin and ball descriptions (continued)

Pin Number

I/O structure
UFBGA176+25

Pin type
Pin name

Notes
UFBGA144

UFBGA169
TFBGA100

Additional
LQFP100

LQFP144

LQFP176
(function after Alternate functions
functions
reset)

TIM1_CH2N, TIM12_CH1,
TIM8_CH2N, USART1_TX,
SPI2_MISO/I2S2_SDI,
DFSDM1_DATIN2,
FT
H10 53 75 L11 N13 K15 87 PB14 I/O - USART3_RTS/USART3_DE, -
_h
UART4_RTS/UART4_DE,
SDMMC2_D0,
FMC_D10/FMC_AD10,
LCD_CLK, EVENTOUT

RTC_REFIN, TIM1_CH3N,
TIM12_CH2, TIM8_CH3N,
USART1_RX,
FT SPI2_MOSI/I2S2_SDO,
G10 54 76 L12 M13 K14 88 PB15 I/O - -
_h DFSDM1_CKIN2,
UART4_CTS, SDMMC2_D1,
FMC_D11/FMC_AD11,
LCD_G7, EVENTOUT
DFSDM1_CKIN3,
USART3_TX(boot),
FT
K9 55 77 L9 M12 L14 89 PD8 I/O - SPDIFRX1_IN2, -
_h
FMC_D13/FMC_AD13,
EVENTOUT

DFSDM1_DATIN3,
FT USART3_RX(boot),
J9 56 78 K9 K11 K13 90 PD9 I/O - -
_h FMC_D14/FMC_AD14,
EVENTOUT

DFSDM1_CKOUT,
FT USART3_CK,
H9 57 79 J9 K12 L13 91 PD10 I/O - -
_h FMC_D15/FMC_AD15,
LCD_B3, EVENTOUT

- - - - - - 92 VDD S - - - -

- - - - - - 93 VSS S - - - -

LPTIM2_IN2, I2C4_SMBA,
USART3_CTS/USART3_NSS,
FT OCTOSPIM_P1_IO0,
G9 58 80 H9 J10 J13 94 PD11 I/O - -
_h SAI4_SD_A,
FMC_A16/FMC_CLE,
EVENTOUT

DS13315 Rev 3 75/270

102
Pinouts, pin descriptions and alternate functions STM32H730xB

Table 7. STM32H730xB pin and ball descriptions (continued)

Pin Number

I/O structure
UFBGA176+25

Pin type
Pin name

Notes
UFBGA144

UFBGA169
TFBGA100

Additional
LQFP100

LQFP144

LQFP176
(function after Alternate functions
functions
reset)

LPTIM1_IN1, TIM4_CH1,
LPTIM2_IN1, I2C4_SCL,
FDCAN3_RX,
USART3_RTS/USART3_DE,
FT
K10 59 81 L10 K13 J15 95 PD12 I/O - OCTOSPIM_P1_IO1, -
_fh
SAI4_FS_A,
FMC_A17/FMC_ALE,
DCMI_D12/PSSI_D12,
EVENTOUT

LPTIM1_OUT, TIM4_CH2,
I2C4_SDA, FDCAN3_TX,
OCTOSPIM_P1_IO3,
FT SAI4_SCK_A,
J10 60 82 K10 J11 H15 96 PD13 I/O - -
_fh UART9_RTS/UART9_DE,
FMC_A18,
DCMI_D13/PSSI_D13,
EVENTOUT

- - 83 - - - - VSS S - - - -

- - 84 - - - - VDD S - - - -

TIM4_CH3, UART8_CTS,
FT UART9_RX,
H8 61 85 K11 J13 H14 97 PD14 I/O - -
_h FMC_D0/FMC_AD0,
EVENTOUT

TIM4_CH4,
UART8_RTS/UART8_DE,
FT
G8 62 86 K12 J12 J12 98 PD15 I/O - UART9_TX, -
_h
FMC_D1/FMC_AD1,
EVENTOUT

- - - - - - 99 VDD S - - - -

- - - - - - 100 VSS S - - - -

TIM1_CH3N, TIM8_CH1,
- - - - - - 101 PJ8 I/O FT - UART8_TX, LCD_G1, -
EVENTOUT

TIM1_CH3, TIM8_CH1N,
- - - - - - 102 PJ9 I/O FT - UART8_RX, LCD_G2, -
EVENTOUT

TIM1_CH2N, TIM8_CH2,
- - - - - - 103 PJ10 I/O FT - SPI5_MOSI, LCD_G3, -
EVENTOUT

76/270 DS13315 Rev 3

STM32H730xB Pinouts, pin descriptions and alternate functions

Table 7. STM32H730xB pin and ball descriptions (continued)

Pin Number

I/O structure
UFBGA176+25

Pin type
Pin name

Notes
UFBGA144

UFBGA169
TFBGA100

Additional
LQFP100

LQFP144

LQFP176
(function after Alternate functions
functions
reset)

TIM1_CH2, TIM8_CH2N,
- - - - - - 104 PJ11 I/O FT - SPI5_MISO, LCD_G4, -
EVENTOUT

- - - - - - 105 VDD S - - - -

- - - - - - 106 VSS S - - - -
TIM1_CH1N, TIM8_CH3,
- - - - - - 107 PK0 I/O FT - SPI5_SCK, LCD_G5, -
EVENTOUT

TIM1_CH1, TIM8_CH3N,
- - - - - - 108 PK1 I/O FT - SPI5_NSS, LCD_G6, -
EVENTOUT
TIM1_BKIN, TIM8_BKIN,
TIM8_BKIN_COMP12,
- - - - - - 109 PK2 I/O FT - -
TIM1_BKIN_COMP12,
LCD_G7, EVENTOUT

TIM8_BKIN,
FT TIM8_BKIN_COMP12,
- - 87 J12 H9 G15 110 PG2 I/O - -
_h FMC_A12, TIM24_ETR,
EVENTOUT

TIM8_BKIN2,
FT TIM8_BKIN2_COMP12,
- - 88 J11 H10 H13 111 PG3 I/O - -
_h FMC_A13, TIM23_ETR,
EVENTOUT

- - - - - - 112 VSS S - - - -

- - - - - - 113 VDD S - - - -

TIM1_BKIN2,
FT TIM1_BKIN2_COMP12,
- - 89 J10 F8 G14 114 PG4 I/O - -
_h FMC_A14/FMC_BA0,
EVENTOUT

TIM1_ETR,
FT
- - 90 H12 H11 F15 115 PG5 I/O - FMC_A15/FMC_BA1, -
_h
EVENTOUT

TIM17_BKIN,
OCTOSPIM_P1_NCS,
FT
- - 91 H11 G9 F14 116 PG6 I/O - FMC_NE3, -
_h
DCMI_D12/PSSI_D12,
LCD_R7, EVENTOUT

DS13315 Rev 3 77/270

102
Pinouts, pin descriptions and alternate functions STM32H730xB

Table 7. STM32H730xB pin and ball descriptions (continued)

Pin Number

I/O structure
UFBGA176+25

Pin type
Pin name

Notes
UFBGA144

UFBGA169
TFBGA100

Additional
LQFP100

LQFP144

LQFP176
(function after Alternate functions
functions
reset)

SAI1_MCLK_A, USART6_CK,
OCTOSPIM_P2_DQS,
FT
- - 92 H10 G10 G13 117 PG7 I/O - FMC_INT, -
_h
DCMI_D13/PSSI_D13,
LCD_CLK, EVENTOUT
TIM8_ETR,
SPI6_NSS/I2S6_WS,
USART6_RTS/USART6_DE,
FT
- - 93 G11 G11 G12 118 PG8 I/O - SPDIFRX1_IN3, -
_h
ETH_PPS_OUT,
FMC_SDCLK, LCD_G7,
EVENTOUT

- - 94 - - - 119 VSS S - - - -

- - - - G12 E15 120 VDD50USB S - - - -

F6 - 95 C11 G13 F13 121 VDD33USB S - - - -

TIM3_CH1, TIM8_CH1,
DFSDM1_CKIN3, I2S2_MCK,
USART6_TX,
FT SDMMC1_D0DIR,
F10 63 96 G12 F9 E14 122 PC6 I/O - SWPMI_IO
_h FMC_NWAIT, SDMMC2_D6,
SDMMC1_D6,
DCMI_D0/PSSI_D0,
LCD_HSYNC, EVENTOUT

DBTRGIO, TIM3_CH2,
TIM8_CH2, DFSDM1_DATIN3,
I2S3_MCK, USART6_RX,
FT SDMMC1_D123DIR,
E10 64 97 F12 F10 D15 123 PC7 I/O - -
_h FMC_NE1, SDMMC2_D7,
SWPMI_TX, SDMMC1_D7,
DCMI_D1/PSSI_D1, LCD_G6,
EVENTOUT

TRACED1, TIM3_CH3,
TIM8_CH3, USART6_CK,
UART5_RTS/UART5_DE,
FT FMC_NE2/FMC_NCE,
F9 65 98 F11 F12 D14 124 PC8 I/O - -
_h FMC_INT, SWPMI_RX,
SDMMC1_D0,
DCMI_D2/PSSI_D2,
EVENTOUT

78/270 DS13315 Rev 3

STM32H730xB Pinouts, pin descriptions and alternate functions

Table 7. STM32H730xB pin and ball descriptions (continued)

Pin Number

I/O structure
UFBGA176+25

Pin type
Pin name

Notes
UFBGA144

UFBGA169
TFBGA100

Additional
LQFP100

LQFP144

LQFP176
(function after Alternate functions
functions
reset)

MCO2, TIM3_CH4,
TIM8_CH4, I2C3_SDA(boot),
I2S_CKIN, I2C5_SDA,
UART5_CTS,
FT
E9 66 99 E11 F11 E13 125 PC9 I/O - OCTOSPIM_P1_IO0, -
_fh
LCD_G3, SWPMI_SUSPEND,
SDMMC1_D1,
DCMI_D3/PSSI_D3, LCD_B2,
EVENTOUT

- - - - - - 126 VDD S - - - -

MCO1, TIM1_CH1,
TIM8_BKIN2, I2C3_SCL(boot),
I2C5_SCL, USART1_CK,
FT
D9 67 100 E12 E12 B14 127 PA8 I/O - OTG_HS_SOF, UART7_RX, -
_fh
TIM8_BKIN2_COMP12,
LCD_B3, LCD_R6,
EVENTOUT
TIM1_CH2, LPUART1_TX,
I2C3_SMBA,
SPI2_SCK/I2S2_CK,
FT I2C5_SMBA,
C9 68 101 D12 E11 D13 128 PA9 I/O - OTG_HS_VBUS
_u USART1_TX(boot),
ETH_TX_ER,
DCMI_D0/PSSI_D0, LCD_R5,
EVENTOUT

TIM1_CH3, LPUART1_RX,
USART1_RX(boot),
FT
D10 69 102 D11 E10 C14 129 PA10 I/O - OTG_HS_ID, MDIOS_MDIO, -
_u
LCD_B4, DCMI_D1/PSSI_D1,
LCD_B1, EVENTOUT
TIM1_CH4, LPUART1_CTS,
SPI2_NSS/I2S2_WS,
FT UART4_RX, OTG_HS_DM
C10 70 103 C12 F13 C15 130 PA11 I/O -
_u USART1_CTS/USART1_NSS, (boot)
FDCAN1_RX, LCD_R4,
EVENTOUT

DS13315 Rev 3 79/270

102
Pinouts, pin descriptions and alternate functions STM32H730xB

Table 7. STM32H730xB pin and ball descriptions (continued)

Pin Number

I/O structure
UFBGA176+25

Pin type
Pin name

Notes
UFBGA144

UFBGA169
TFBGA100

Additional
LQFP100

LQFP144

LQFP176
(function after Alternate functions
functions
reset)

TIM1_ETR,
LPUART1_RTS/LPUART1_DE
, SPI2_SCK/I2S2_CK,
FT UART4_TX, OTG_HS_DP
B10 71 104 B12 E13 B15 131 PA12 I/O -
_u USART1_RTS/USART1_DE, (boot)
SAI4_FS_B, FDCAN1_TX,
TIM1_BKIN2, LCD_R5,
EVENTOUT

PA13(JTMS/
A10 72 105 A12 D11 B13 132 I/O FT - JTMS/SWDIO, EVENTOUT -
SWDIO)

E7 73 106 G9 D13 A14 133 VCAP S - - - -

- 74 107 - - - 134 VSS S - - - -

- - - - D12 A13 135 VDDLDO S - - - -

- 75 108 - - - 136 VDD S - - - -

TIM8_CH1N, UART4_TX,
FT
- - - - B13 C13 - PH13 I/O - FDCAN1_TX(boot), FMC_D21, -
_h
LCD_G2, EVENTOUT
TIM8_CH2N, UART4_RX,
FDCAN1_RX(boot),
FT
- - - - A13 B12 - PH14 I/O - FMC_D22, -
_h
DCMI_D4/PSSI_D4, LCD_G3,
EVENTOUT

TIM8_CH3N, FMC_D23,
FT
- - - - - D12 - PH15 I/O - DCMI_D11/PSSI_D11, -
_h
LCD_G4, EVENTOUT

- - - - - - 137 VSS S - - - -

PA14(JTCK/
A9 76 109 A11 B12 A12 138 I/O FT - JTCK/SWCLK, EVENTOUT -
SWCLK)

JTDI, TIM2_CH1/TIM2_ETR,
CEC, SPI1_NSS/I2S1_WS,
SPI3_NSS(boot)/I2S3_WS,
A8 77 110 A10 C11 A11 139 PA15(JTDI) I/O FT - SPI6_NSS/I2S6_WS, -
UART4_RTS/UART4_DE,
LCD_R3, UART7_TX,
LCD_B6, EVENTOUT

80/270 DS13315 Rev 3

STM32H730xB Pinouts, pin descriptions and alternate functions

Table 7. STM32H730xB pin and ball descriptions (continued)

Pin Number

I/O structure
UFBGA176+25

Pin type
Pin name

Notes
UFBGA144

UFBGA169
TFBGA100

Additional
LQFP100

LQFP144

LQFP176
(function after Alternate functions
functions
reset)

DFSDM1_CKIN5, I2C5_SDA,
SPI3_SCK(boot)/I2S3_CK,
USART3_TX, UART4_TX,
FT
B9 78 111 B11 A12 C12 140 PC10 I/O - OCTOSPIM_P1_IO1, LCD_B1, -
_fh
SWPMI_RX, SDMMC1_D2,
DCMI_D8/PSSI_D8, LCD_R2,
EVENTOUT

DFSDM1_DATIN5, I2C5_SCL,
SPI3_MISO(boot)/I2S3_SDI,
USART3_RX, UART4_RX,
FT
B8 79 112 B10 B11 C11 141 PC11 I/O - OCTOSPIM_P1_NCS, -
_fh
SDMMC1_D3,
DCMI_D4/PSSI_D4, LCD_B4,
EVENTOUT
TRACED3,
FMC_D6/FMC_AD6,
TIM15_CH1, I2C5_SMBA,
SPI6_SCK/I2S6_CK,
FT
C8 80 113 C10 A11 B11 142 PC12 I/O - SPI3_MOSI(boot)/I2S3_SDO, -
_h
USART3_CK, UART5_TX,
SDMMC1_CK,
DCMI_D9/PSSI_D9, LCD_R6,
EVENTOUT

DFSDM1_CKIN6, UART4_RX,
FDCAN1_RX(boot),
FT
D8 81 114 E10 D10 C10 143 PD0 I/O - UART9_CTS, -
_h
FMC_D2/FMC_AD2, LCD_B1,
EVENTOUT

DFSDM1_DATIN6,
UART4_TX,
FT
E8 82 115 D10 C10 A10 144 PD1 I/O - FDCAN1_TX(boot), -
_h
FMC_D3/FMC_AD3,
EVENTOUT
TRACED2,
FMC_D7/FMC_AD7,
TIM3_ETR, TIM15_BKIN,
FT
B7 83 116 E9 E9 B10 145 PD2 I/O - UART5_RX, LCD_B7, -
_h
SDMMC1_CMD,
DCMI_D11/PSSI_D11,
LCD_B2, EVENTOUT

DS13315 Rev 3 81/270

102
Pinouts, pin descriptions and alternate functions STM32H730xB

Table 7. STM32H730xB pin and ball descriptions (continued)

Pin Number

I/O structure
UFBGA176+25

Pin type
Pin name

Notes
UFBGA144

UFBGA169
TFBGA100

Additional
LQFP100

LQFP144

LQFP176
(function after Alternate functions
functions
reset)

DFSDM1_CKOUT,
SPI2_SCK/I2S2_CK,
FT USART2_CTS/USART2_NSS,
C7 84 117 D9 D9 A9 146 PD3 I/O - -
_h FMC_CLK,
DCMI_D5/PSSI_D5, LCD_G7,
EVENTOUT

USART2_RTS/USART2_DE,
FT
D7 85 118 C9 C9 C9 147 PD4 I/O - OCTOSPIM_P1_IO4, -
_h
FMC_NOE, EVENTOUT

USART2_TX,
FT
B6 86 119 B9 A9 B9 148 PD5 I/O - OCTOSPIM_P1_IO5, -
_h
FMC_NWE, EVENTOUT

- - 120 - - - - VSS S - - - -

- - 121 - - - - VDD S - - - -
SAI4_D1, SAI1_D1,
DFSDM1_CKIN4,
DFSDM1_DATIN1,
SPI3_MOSI/I2S3_SDO,
FT SAI1_SD_A, USART2_RX,
C6 87 122 A8 B9 D9 149 PD6 I/O - -
_h SAI4_SD_A,
OCTOSPIM_P1_IO6,
SDMMC2_CK, FMC_NWAIT,
DCMI_D10/PSSI_D10,
LCD_B2, EVENTOUT
DFSDM1_DATIN4,
SPI1_MOSI/I2S1_SDO,
DFSDM1_CKIN1,
FT
D6 88 123 A9 D8 B8 150 PD7 I/O - USART2_CK, SPDIFRX1_IN1, -
_h
OCTOSPIM_P1_IO7,
SDMMC2_CMD, FMC_NE1,
EVENTOUT

- - - - - - 151 VSS S - - - -

- - - - - - 152 VDD S - - - -
FDCAN3_TX,
SPI1_MISO/I2S1_SDI,
USART6_RX, SPDIFRX1_IN4,
FT OCTOSPIM_P1_IO6,
- - 124 E8 C8 A8 153 PG9 I/O - -
_h SAI4_FS_B, SDMMC2_D0,
FMC_NE2/FMC_NCE,
DCMI_VSYNC/PSSI_RDY,
EVENTOUT

82/270 DS13315 Rev 3

STM32H730xB Pinouts, pin descriptions and alternate functions

Table 7. STM32H730xB pin and ball descriptions (continued)

Pin Number

I/O structure
UFBGA176+25

Pin type
Pin name

Notes
UFBGA144

UFBGA169
TFBGA100

Additional
LQFP100

LQFP144

LQFP176
(function after Alternate functions
functions
reset)

FDCAN3_RX,
OCTOSPIM_P2_IO6,
SPI1_NSS/I2S1_WS,
FT
- - 125 D8 A8 C8 154 PG10 I/O - LCD_G3, SAI4_SD_B, -
_h
SDMMC2_D1, FMC_NE3,
DCMI_D2/PSSI_D2, LCD_B2,
EVENTOUT

LPTIM1_IN2, USART10_RX,
SPI1_SCK/I2S1_CK,
SPDIFRX1_IN1,
FT OCTOSPIM_P2_IO7,
- - 126 C8 B8 A7 155 PG11 I/O - -
_h SDMMC2_D2,
ETH_MII_TX_EN/ETH_RMII_T
X_EN, DCMI_D3/PSSI_D3,
LCD_B3, EVENTOUT

LPTIM1_IN1,
OCTOSPIM_P2_NCS,
USART10_TX,
SPI6_MISO/I2S6_SDI,
FT USART6_RTS/USART6_DE,
- - 127 B8 E8 D8 156 PG12 I/O - -
_h SPDIFRX1_IN2, LCD_B4,
SDMMC2_D3,
ETH_MII_TXD1/ETH_RMII_TX
D1, FMC_NE4, TIM23_CH1,
LCD_B1, EVENTOUT

TRACED0, LPTIM1_OUT,
USART10_CTS/USART10_NS
S, SPI6_SCK/I2S6_CK,
FT USART6_CTS/USART6_NSS,
- - 128 D7 D7 B7 157 PG13 I/O - -
_h SDMMC2_D6,
ETH_MII_TXD0/ETH_RMII_TX
D0, FMC_A24, TIM23_CH2,
LCD_R0, EVENTOUT
TRACED1, LPTIM1_ETR,
USART10_RTS/USART10_DE
, SPI6_MOSI/I2S6_SDO,
USART6_TX,
FT
- - 129 C7 C7 C7 158 PG14 I/O - OCTOSPIM_P1_IO7, -
_h
SDMMC2_D7,
ETH_MII_TXD1/ETH_RMII_TX
D1, FMC_A25, TIM23_CH3,
LCD_B0, EVENTOUT
- - 130 - - - 159 VSS S - - - -

DS13315 Rev 3 83/270

102
Pinouts, pin descriptions and alternate functions STM32H730xB

Table 7. STM32H730xB pin and ball descriptions (continued)

Pin Number

I/O structure
UFBGA176+25

Pin type
Pin name

Notes
UFBGA144

UFBGA169
TFBGA100

Additional
LQFP100

LQFP144

LQFP176
(function after Alternate functions
functions
reset)

- - 131 - - - 160 VDD S - - - -

USART6_CTS/USART6_NSS,
OCTOSPIM_P2_DQS,
FT
- - 132 B7 E7 D7 161 PG15 I/O - USART10_CK, FMC_NCAS, -
_h
DCMI_D13/PSSI_D13,
EVENTOUT

JTDO/TRACESWO,
TIM2_CH2,
SPI1_SCK/I2S1_CK,
PB3(JTDO/TRAC FT SPI3_SCK/I2S3_CK,
A7 89 133 A7 F7 A6 162 I/O - -
ESWO) _h SPI6_SCK/I2S6_CK,
SDMMC2_D2, CRS_SYNC,
UART7_RX, TIM24_ETR,
EVENTOUT
NJTRST, TIM16_BKIN,
TIM3_CH1,
SPI1_MISO/I2S1_SDI,
FT SPI3_MISO/I2S3_SDI,
A6 90 134 A6 B6 B6 163 PB4(NJTRST) I/O - -
_h SPI2_NSS/I2S2_WS,
SPI6_MISO/I2S6_SDI,
SDMMC2_D3, UART7_TX,
EVENTOUT

TIM17_BKIN, TIM3_CH2,
LCD_B5, I2C1_SMBA,
SPI1_MOSI/I2S1_SDO,
I2C4_SMBA,
SPI3_MOSI/I2S3_SDO,
FT SPI6_MOSI/I2S6_SDO,
C5 91 135 B6 C6 C6 164 PB5 I/O - -
_h FDCAN2_RX,
OTG_HS_ULPI_D7,
ETH_PPS_OUT,
FMC_SDCKE1,
DCMI_D10/PSSI_D10,
UART5_RX, EVENTOUT

TIM16_CH1N, TIM4_CH1,
I2C1_SCL(boot), CEC,
I2C4_SCL, USART1_TX,
LPUART1_TX, FDCAN2_TX,
FT
B5 92 136 C6 A5 A5 165 PB6 I/O - OCTOSPIM_P1_NCS, -
_fh
DFSDM1_DATIN5,
FMC_SDNE1,
DCMI_D5/PSSI_D5,
UART5_TX, EVENTOUT

84/270 DS13315 Rev 3

STM32H730xB Pinouts, pin descriptions and alternate functions

Table 7. STM32H730xB pin and ball descriptions (continued)

Pin Number

I/O structure
UFBGA176+25

Pin type
Pin name

Notes
UFBGA144

UFBGA169
TFBGA100

Additional
LQFP100

LQFP144

LQFP176
(function after Alternate functions
functions
reset)

TIM17_CH1N, TIM4_CH2,
I2C1_SDA, I2C4_SDA,
FT USART1_RX, LPUART1_RX,
A5 93 137 D6 D6 B5 166 PB7 I/O - PVD_IN
_fa DFSDM1_CKIN5, FMC_NL,
DCMI_VSYNC/PSSI_RDY,
EVENTOUT

D5 94 138 D5 E6 C5 167 BOOT0 I B - - VPP

TIM16_CH1, TIM4_CH3,
DFSDM1_CKIN7, I2C1_SCL,
I2C4_SCL, SDMMC1_CKIN,
UART4_RX, FDCAN1_RX,
FT
B4 95 139 C5 B5 A2 168 PB8 I/O - SDMMC2_D4, -
_fh
ETH_MII_TXD3,
SDMMC1_D4,
DCMI_D6/PSSI_D6, LCD_B6,
EVENTOUT

TIM17_CH1, TIM4_CH4,
DFSDM1_DATIN7,
I2C1_SDA(boot),
SPI2_NSS/I2S2_WS,
FT I2C4_SDA, SDMMC1_CDIR,
A4 96 140 B5 C5 B3 169 PB9 I/O - -
_fh UART4_TX, FDCAN1_TX,
SDMMC2_D5, I2C4_SMBA,
SDMMC1_D5,
DCMI_D7/PSSI_D7, LCD_B7,
EVENTOUT

LPTIM1_ETR, TIM4_ETR,
LPTIM2_ETR, UART8_RX,
FT
D4 97 141 A5 D5 B4 170 PE0 I/O - SAI4_MCLK_A, FMC_NBL0, -
_h
DCMI_D2/PSSI_D2, LCD_R0,
EVENTOUT

LPTIM1_IN2, UART8_TX,
FT FMC_NBL1,
C4 98 142 A4 D4 C4 171 PE1 I/O - -
_h DCMI_D3/PSSI_D3, LCD_R6,
EVENTOUT

- - - - A4 A4 172 VCAP S - - - -

- 99 - - - - 173 VSS S - - - -

F7 - 143 E5 C4 D4 174 PDR_ON S - - - -

- - - - B4 A3 175 VDDLDO S - - - -

- 100 144 - - - - VDD S - - - -

DS13315 Rev 3 85/270

102
Pinouts, pin descriptions and alternate functions STM32H730xB

Table 7. STM32H730xB pin and ball descriptions (continued)

Pin Number

I/O structure
UFBGA176+25

Pin type
Pin name

Notes
UFBGA144

UFBGA169
TFBGA100

Additional
LQFP100

LQFP144

LQFP176
(function after Alternate functions
functions
reset)

- - - - - - 176 VDD S - - - -

C2 - - D2 B3 A1 - VSS S - - - -

E6 - - E6 B7 A15 - VSS S - - - -

J1 - - E7 B10 C2 - VSS S - - - -

E4 - - G4 C12 D10 - VSS S - - - -

E5 - - G8 D2 D6 - VSS S - - - -

- - - G10 G2 E1 - VSS S - - - -

- - - H5 H12 F10 - VSS S - - - -

- - - H6 L12 F12 - VSS S - - - -

- - - - M2 F6 - VSS S - - - -

- - - - M4 F7 - VSS S - - - -

- - - - M7 F8 - VSS S - - - -

- - - - M11 F9 - VSS S - - - -

- - - - - G10 - VSS S - - - -
- - - - - G6 - VSS S - - - -

- - - - - G7 - VSS S - - - -

- - - - - G8 - VSS S - - - -

- - - - - G9 - VSS S - - - -

- - - - - H10 - VSS S - - - -

- - - - - H6 - VSS S - - - -

- - - - - H7 - VSS S - - - -

- - - - - H8 - VSS S - - - -

- - - - - H9 - VSS S - - - -

- - - - - J10 - VSS S - - - -

- - - - - J14 - VSS S - - - -

- - - - - J6 - VSS S - - - -

- - - - - J7 - VSS S - - - -

- - - - - J8 - VSS S - - - -

- - - - - J9 - VSS S - - - -

- - - - - K10 - VSS S - - - -

86/270 DS13315 Rev 3

STM32H730xB Pinouts, pin descriptions and alternate functions

Table 7. STM32H730xB pin and ball descriptions (continued)

Pin Number

I/O structure
UFBGA176+25

Pin type
Pin name

Notes
UFBGA144

UFBGA169
TFBGA100

Additional
LQFP100

LQFP144

LQFP176
(function after Alternate functions
functions
reset)

- - - - - K12 - VSS S - - - -

- - - - - K2 - VSS S - - - -

- - - - - K6 - VSS S - - - -

- - - - - K7 - VSS S - - - -

- - - - - K8 - VSS S - - - -

- - - - - K9 - VSS S - - - -

- - - - - M10 - VSS S - - - -

- - - - - M6 - VSS S - - - -

- - - - - R1 - VSS S - - - -

- - - - - R15 - VSS S - - - -

D2 - - D3 A3 D5 - VDD S - - - -

F5 - - F4 A6 D11 - VDD S - - - -

K1 - - F5 A7 E4 - VDD S - - - -

F4 - - F6 A10 E12 - VDD S - - - -

- - - F7 C13 G4 - VDD S - - - -

- - - F8 D1 H12 - VDD S - - - -

- - - F9 G1 K4 - VDD S - - - -

- - - F10 H13 L12 - VDD S - - - -

- - - G5 L13 M5 - VDD S - - - -

- - - G6 M1 M9 - VDD S - - - -

- - - G7 N4 - - VDD S - - - -

- - - - N7 - - VDD S - - - -

- - - - N11 - - VDD S - - - -

1. Pxy_C and Pxy pins/balls are two separate pads (analog switch open). The analog switch is configured through a SYSCFG
register. Refer to the product reference manual for a detailed description of the switch configuration bits.
2. There is a direct path between Pxy_C and Pxy pins/balls, through an analog switch. Pxy alternate functions are available
on Pxy_C when the analog switch is closed. The analog switch is configured through a SYSCFG register. Refer to the
product reference manual for a detailed description of the switch configuration bits.

DS13315 Rev 3 87/270

102
88/270

Pinouts, pin descriptions and alternate functions

Table 8. STM32H730xB pin alternate functions
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

DFSDM1/
DFSDM1/ CEC/DCMI/ CRS/FMC/
DFSDM1/ SDMMC1/ LPUART1 FDCAN1/2/ ETH/I2C4/ FMC/LCD
FMC/ LCD/ PSSI/ CEC/ LCD/OCT COMP/
FDCAN3 I2C4/5/ SPI2/I2S2 /SAI4/ FMC/LCD/ LCD/MDIOS /MDIOS/
Port LPTIM1/ LPTIM2/3/ DFSDM1/ FDCAN3/ OSPIM_P1 DCMI/
/PDM_ OCTO /SPI3/I2S SDMMC1/ OCTOSPIM /OCTOSPIM OCTOSPI LCD/
SAI4/ 4/5/ I2C1/2/3/4/5 SPI1/I2S1/ /OTG1_FS/ PSSI/
SYS SAI1/ SPIM_P1/ 3/SPI6/ SPDIFRX _P1/2/SAI4 _P1/SDMMC M_P1/ TIM24/ SYS
TIM16/17 LPUART1 /LPTIM2/ SPI2/I2S2/ OTG1_HS/ LCD/
TIM3/4/5 SAI1/SPI3/ UART7 1/SPI6/ /SDMMC2/ 2/SWPMI1/ SDMMC1 UART5
/TIM1x/ /OCTO OCTOSPIM SPI3/I2S3/ SAI4/ TIM1x/
/12/15 I2S3/ /USART1/ UART4/5/ SPDIFRX1/ TIM1x/TIM8/ /TIM1x/
TIM2x SPIM_P1/ _P1/TIM15/ SPI4/5/6 SDMMC2/ TIM23
UART4 2/3/6 8 TIM13/14 UART7/9/ TIM8
2/TIM8 USART1/10 TIM8
USART10

USART2_
TIM2_
TIM5_ TIM8_ TIM15_ SPI6_NSS CTS/ UART4_ SDMMC2_ SAI4_SD_ ETH_MII_ EVENT
PA0 - CH1/TIM - FMC_A19 - -
CH1 ETR BKIN /I2S6_WS USART2_ TX CMD B CRS OUT
2_ETR
NSS

USART2_ ETH_MII_
OCTOSPI
TIM2_CH TIM5_ LPTIM3_ TIM15_CH1 RTS/ UART4_ OCTOSPIM SAI4_ RX_CLK/ LCD_R EVENT
PA1 - - - M_P1_ -
2 CH2 OUT N USART2_ RX _P1_IO3 MCLK_B ETH_RMII_ 2 OUT
DQS
DE REF_CLK
DS13315 Rev 3

TIM2_CH TIM5_ LPTIM4_ OCTOSPI USART2_ SAI4_ MDIOS_ LCD_R EVENT

PA2 - TIM15_CH1 - - - ETH_MDIO -
3 CH3 OUT M_P1_IO0 TX SCK_B MDIO 1 OUT

OCTOSPI
TIM2_CH TIM5_ LPTIM5_ OCTOSPI USART2_ OTG_HS_ ETH_MII_ LCD_B EVENT
PA3 - TIM15_CH2 I2S6_MCK - LCD_B2 M_P1_ -
4 CH4 OUT M_P1_IO2 RX ULPI_D0 COL 5 OUT
CLK

DCMI_
SPI6_NS FMC_D8/
D1PW TIM5_ SPI1_NSS SPI3_NSS/ USART2_ HSYNC LCD_V EVENT
Port A

PA4 - - - S/I2S6_ - - - FMC_AD

REN ETR /I2S1_WS I2S3_WS CK /PSSI_ SYNC OUT
WS 8
DE

TIM2_CH SPI6_SC FMC_D9/

D2PW TIM8_ SPI1_SCK OTG_HS_ PSSI_ LCD_R EVENT
PA5 1/TIM2_ - - - - K/I2S6_ - - FMC_AD
REN CH1N /I2S1_CK ULPI_CK D14 4 OUT
ETR CK 9

DCMI_
SPI1_ SPI6_MIS TIM1_
TIM1_ TIM3_C TIM8_ OCTOSPI TIM13_CH TIM8_BKIN MDIOS_ PIXCL LCD_G EVENT
PA6 - - MISO/I2S - O/I2S6_S BKIN_
BKIN H1 BKIN M_P1_IO3 1 _COMP12 MDC K/PSSI 2 OUT
1_SDI DI COMP12
_PDCK

ETH_MII_
SPI1_ SPI6_
TIM1_CH TIM3_ TIM8_CH TIM14_CH OCTOSPI RX_DV/ETH FMC_SD LCD_V EVENT
PA7 - - MOSI/I2S - - MOSI/I2S -
1N CH2 1N 1 M_P1_IO2 _RMII_CRS NWE SYNC OUT
1_SDO 6_SDO

STM32H730xB
_DV

TIM8_
TIM1_CH TIM8_ USART1_ OTG_HS_ LCD_B LCD_R EVENT
PA8 MCO1 - I2C3_SCL - I2C5_SCL - - UART7_RX BKIN2_
1 BKIN2 CK SOF 3 6 OUT
COMP12
 Table 8. STM32H730xB pin alternate functions (continued)

STM32H730xB
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

DFSDM1/
DFSDM1/ CEC/DCMI/ CRS/FMC/
DFSDM1/ SDMMC1/ LPUART1 FDCAN1/2/ ETH/I2C4/ FMC/LCD
FMC/ LCD/ PSSI/ CEC/ LCD/OCT COMP/
FDCAN3 I2C4/5/ SPI2/I2S2 /SAI4/ FMC/LCD/ LCD/MDIOS /MDIOS/
Port LPTIM1/ LPTIM2/3/ DFSDM1/ FDCAN3/ OSPIM_P1 DCMI/
/PDM_ OCTO /SPI3/I2S SDMMC1/ OCTOSPIM /OCTOSPIM OCTOSPI LCD/
SAI4/ 4/5/ I2C1/2/3/4/5 SPI1/I2S1/ /OTG1_FS/ PSSI/
SYS SAI1/ SPIM_P1/ 3/SPI6/ SPDIFRX _P1/2/SAI4 _P1/SDMMC M_P1/ TIM24/ SYS
TIM16/17 LPUART1 /LPTIM2/ SPI2/I2S2/ OTG1_HS/ LCD/
TIM3/4/5 SAI1/SPI3/ UART7 1/SPI6/ /SDMMC2/ 2/SWPMI1/ SDMMC1 UART5
/TIM1x/ /OCTO OCTOSPIM SPI3/I2S3/ SAI4/ TIM1x/
/12/15 I2S3/ /USART1/ UART4/5/ SPDIFRX1/ TIM1x/TIM8/ /TIM1x/
TIM2x SPIM_P1/ _P1/TIM15/ SPI4/5/6 SDMMC2/ TIM23
UART4 2/3/6 8 TIM13/14 UART7/9/ TIM8
2/TIM8 USART1/10 TIM8
USART10

DCMI_
TIM1_CH LPUART1 I2C3_ SPI2_SCK I2C5_ USART1_ D0/ LCD_R EVENT
PA9 - - - - - ETH_TX_ER -
2 _TX SMBA /I2S2_CK SMBA TX PSSI_ 5 OUT
D0

DCMI_
TIM1_CH LPUART1 USART1_ OTG_HS_ MDIOS_ D1/ LCD_B EVENT
PA10 - - - - - - - LCD_B4
3 _RX RX ID MDIO PSSI_ 1 OUT
D1

USART1_
DS13315 Rev 3

TIM1_CH LPUART1 SPI2_NSS CTS/ FDCAN1_ LCD_R EVENT

PA11 - - - UART4_RX - - - - -
4 _CTS /I2S2_WS USART1_ RX 4 OUT
NSS
Port A

Pinouts, pin descriptions and alternate functions

LPUART1 USART1_
TIM1_ _RTS/ SPI2_SCK RTS/ SAI4_FS_ FDCAN1_ TIM1_ LCD_R EVENT
PA12 - - - UART4_TX - - -
ETR LPUART1 /I2S2_CK USART1_ B TX BKIN2 5 OUT
_DE DE

JTMS/
EVENT
PA13 SWDI - - - - - - - - - - - - - -
OUT
O

JTCK/
EVENT
PA14 SWCL - - - - - - - - - - - - - -
OUT
K

TIM2_CH SPI6_NS UART4_R

SPI1_NSS SPI3_NSS/ LCD_B EVENT
PA15 JTDI 1/TIM2_ - - CEC S/I2S6_W TS/UART LCD_R3 - UART7_TX - -
/I2S1_WS I2S3_WS 6 OUT
ETR S 4_DE
89/270
 Table 8. STM32H730xB pin alternate functions (continued)

90/270

Pinouts, pin descriptions and alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

DFSDM1/
DFSDM1/ CEC/DCMI/ CRS/FMC/
DFSDM1/ SDMMC1/ LPUART1 FDCAN1/2/ ETH/I2C4/ FMC/LCD
FMC/ LCD/ PSSI/ CEC/ LCD/OCT COMP/
FDCAN3 I2C4/5/ SPI2/I2S2 /SAI4/ FMC/LCD/ LCD/MDIOS /MDIOS/
Port LPTIM1/ LPTIM2/3/ DFSDM1/ FDCAN3/ OSPIM_P1 DCMI/
/PDM_ OCTO /SPI3/I2S SDMMC1/ OCTOSPIM /OCTOSPIM OCTOSPI LCD/
SAI4/ 4/5/ I2C1/2/3/4/5 SPI1/I2S1/ /OTG1_FS/ PSSI/
SYS SAI1/ SPIM_P1/ 3/SPI6/ SPDIFRX _P1/2/SAI4 _P1/SDMMC M_P1/ TIM24/ SYS
TIM16/17 LPUART1 /LPTIM2/ SPI2/I2S2/ OTG1_HS/ LCD/
TIM3/4/5 SAI1/SPI3/ UART7 1/SPI6/ /SDMMC2/ 2/SWPMI1/ SDMMC1 UART5
/TIM1x/ /OCTO OCTOSPIM SPI3/I2S3/ SAI4/ TIM1x/
/12/15 I2S3/ /USART1/ UART4/5/ SPDIFRX1/ TIM1x/TIM8/ /TIM1x/
TIM2x SPIM_P1/ _P1/TIM15/ SPI4/5/6 SDMMC2/ TIM23
UART4 2/3/6 8 TIM13/14 UART7/9/ TIM8
2/TIM8 USART1/10 TIM8
USART10

TIM1_ TIM3_ TIM8_ OCTOSPIM DFSDM1_ UART4_ OTG_HS_ ETH_MII_ LCD_G EVENT
PB0 - - - LCD_R3 - -
CH2N CH3 CH2N _P1_IO1 CKOUT CTS ULPI_D1 RXD2 1 OUT

TIM1_ TIM3_ TIM8_CH OCTOSPIM DFSDM1_ OTG_HS_ ETH_MII_ LCD_G EVENT

PB1 - - - - LCD_R6 - -
CH3N CH4 3N _P1_IO0 DATIN1 ULPI_D2 RXD3 0 OUT

SPI3_ OCTOSPI
RTC_ DFSDM1_ SAI1_SD_ SAI4_SD_ OCTOSPIM TIM23_ EVENT
PB2 SAI4_D1 SAI1_D1 - - MOSI/I2S M_P1_ ETH_TX_ER - -
OUT CKIN1 A A _P1_CLK ETR OUT
3_SDO DQS

JTDO/ SPI6_
TIM2_CH SPI1_SCK SPI3_SCK/ SDMMC2_ CRS_ TIM24_ EVENT
DS13315 Rev 3

PB3 TRAC - - - - SCK/I2S6 UART7_RX - -

2 /I2S1_CK I2S3_CK D2 SYNC ETR OUT
ESWO _CK

SPI1_ SPI3_ SPI2_ SPI6_

NJT TIM16_ TIM3_ SDMMC2_ EVENT
PB4 - - MISO/I2S MISO/I2S3 NSS/I2S2 MISO/I2S - UART7_TX - - -
RST BKIN CH1 D3 OUT
1_SDI _SDI _WS 6_SDI

DCMI_
SPI1_ SPI3_ SPI6_
TIM17_ TIM3_ I2C1_ I2C4_SMB FDCAN2_ OTG_HS_ ETH_PPS_ FMC_SD D10/ UART5 EVENT
PB5 - LCD_B5 MOSI/I2S MOSI/I2S MOSI/I2S
Port B

BKIN CH2 SMBA A RX ULPI_D7 OUT CKE1 PSSI_ _RX OUT

1_SDO 3_SDO 6_SDO
D10

DCMI_
OCTOSPI
TIM16_ TIM4_ USART1_ LPUART1 FDCAN2_ DFSDM1_ FMC_SD D5/ UART5 EVENT
PB6 - - I2C1_SCL CEC I2C4_SCL M_P1_
CH1N CH1 TX _TX TX DATIN5 NE1 PSSI_ _TX OUT
NCS
D5

DCMI_
TIM17_ TIM4_ USART1_ LPUART1 DFSDM1_ VSYNC EVENT
PB7 - - I2C1_SDA - I2C4_SDA - - FMC_NL -
CH1N CH2 RX _RX CKIN5 /PSSI_ OUT
RDY

DCMI_
TIM16_ TIM4_ DFSDM1_ SDMMC1 UART4_ FDCAN1_ SDMMC2_ ETH_MII_ SDMMC1 D6/ LCD_B EVENT
PB8 - I2C1_SCL - I2C4_SCL
CH1 CH3 CKIN7 _CKIN RX RX D4 TXD3 _D4 PSSI_ 6 OUT

STM32H730xB
D6

DCMI_
TIM17_ TIM4_ DFSDM1_ SPI2_NSS SDMMC1 UART4_ FDCAN1_ SDMMC2_ SDMMC1 D7/ LCD_B EVENT
PB9 - I2C1_SDA I2C4_SDA I2C4_SMBA
CH1 CH4 DATIN7 /I2S2_WS _CDIR TX TX D5 _D5 PSSI_ 7 OUT
D7
 Table 8. STM32H730xB pin alternate functions (continued)

STM32H730xB
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

DFSDM1/
DFSDM1/ CEC/DCMI/ CRS/FMC/
DFSDM1/ SDMMC1/ LPUART1 FDCAN1/2/ ETH/I2C4/ FMC/LCD
FMC/ LCD/ PSSI/ CEC/ LCD/OCT COMP/
FDCAN3 I2C4/5/ SPI2/I2S2 /SAI4/ FMC/LCD/ LCD/MDIOS /MDIOS/
Port LPTIM1/ LPTIM2/3/ DFSDM1/ FDCAN3/ OSPIM_P1 DCMI/
/PDM_ OCTO /SPI3/I2S SDMMC1/ OCTOSPIM /OCTOSPIM OCTOSPI LCD/
SAI4/ 4/5/ I2C1/2/3/4/5 SPI1/I2S1/ /OTG1_FS/ PSSI/
SYS SAI1/ SPIM_P1/ 3/SPI6/ SPDIFRX _P1/2/SAI4 _P1/SDMMC M_P1/ TIM24/ SYS
TIM16/17 LPUART1 /LPTIM2/ SPI2/I2S2/ OTG1_HS/ LCD/
TIM3/4/5 SAI1/SPI3/ UART7 1/SPI6/ /SDMMC2/ 2/SWPMI1/ SDMMC1 UART5
/TIM1x/ /OCTO OCTOSPIM SPI3/I2S3/ SAI4/ TIM1x/
/12/15 I2S3/ /USART1/ UART4/5/ SPDIFRX1/ TIM1x/TIM8/ /TIM1x/
TIM2x SPIM_P1/ _P1/TIM15/ SPI4/5/6 SDMMC2/ TIM23
UART4 2/3/6 8 TIM13/14 UART7/9/ TIM8
2/TIM8 USART1/10 TIM8
USART10

TIM2_ LPTIM2_ SPI2_SCK DFSDM1_ USART3_ OCTOSPIM OTG_HS_ ETH_MII_ LCD_G EVENT
PB10 - - I2C2_SCL - - -
CH3 IN1 /I2S2_CK DATIN7 TX _P1_NCS ULPI_D3 RX_ER 4 OUT

ETH_MII_TX
TIM2_ LPTIM2_ DFSDM1_ USART3_ OTG_HS_ _EN/ETH_ LCD_G EVENT
PB11 - - I2C2_SDA - - - - -
CH4 ETR CKIN7 RX ULPI_D4 RMII_TX_ 5 OUT
EN

TIM1_
OCTOSPI ETH_MII_TX OCTOSPI
TIM1_ I2C2_ SPI2_NSS DFSDM1_ USART3_ FDCAN2_ OTG_HS_ BKIN_ UART5 EVENT
PB12 - - M_P1_ - D0/ETH_ M_P1_IO
P BKIN SMBA /I2S2_WS DATIN1 CK RX ULPI_D5 COMP _RX OUT
NCLK RMII_TXD0 0
DS13315 Rev 3

12
r
o
USART3_
t ETH_MII_TX DCMI_
TIM1_ LPTIM2_ OCTOSPIM SPI2_SCK DFSDM1_ CTS/ FDCAN2_ OTG_HS_ SDMMC1 UART5 EVENT

Pinouts, pin descriptions and alternate functions

B PB13 - - - D1/ETH_ D2/P
CH1N OUT _P1_IO2 /I2S2_CK CKIN1 USART3_ TX ULPI_D6 _D0 _TX OUT
RMII_TXD1 SSI_D2
NSS

USART3_ UART4_
SPI2_ FMC_D1
TIM1_ TIM12_ TIM8_ USART1_ DFSDM1_ RTS/ RTS SDMMC2_ LCD_ EVENT
PB14 - MISO/ - - 0/FMC_ -
CH2N CH1 CH2N TX DATIN2 USART3_ /UART4_ D0 CLK OUT
I2S2_SDI AD10
DE DE

SPI2_MO FMC_D11
RTC_ TIM1_ TIM12_ TIM8_ USART1_ DFSDM1_ UART4_ SDMMC2_ LCD_G EVENT
PB15 SI/I2S2_ - - - /FMC_AD -
REFIN CH3N CH2 CH3N RX CKIN2 CTS D1 7 OUT
SDO 11
91/270
 Table 8. STM32H730xB pin alternate functions (continued)

92/270

Pinouts, pin descriptions and alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

DFSDM1/
DFSDM1/ CEC/DCMI/ CRS/FMC/
DFSDM1/ SDMMC1/ LPUART1 FDCAN1/2/ ETH/I2C4/ FMC/LCD
FMC/ LCD/ PSSI/ CEC/ LCD/OCT COMP/
FDCAN3 I2C4/5/ SPI2/I2S2 /SAI4/ FMC/LCD/ LCD/MDIOS /MDIOS/
Port LPTIM1/ LPTIM2/3/ DFSDM1/ FDCAN3/ OSPIM_P1 DCMI/
/PDM_ OCTO /SPI3/I2S SDMMC1/ OCTOSPIM /OCTOSPIM OCTOSPI LCD/
SAI4/ 4/5/ I2C1/2/3/4/5 SPI1/I2S1/ /OTG1_FS/ PSSI/
SYS SAI1/ SPIM_P1/ 3/SPI6/ SPDIFRX _P1/2/SAI4 _P1/SDMMC M_P1/ TIM24/ SYS
TIM16/17 LPUART1 /LPTIM2/ SPI2/I2S2/ OTG1_HS/ LCD/
TIM3/4/5 SAI1/SPI3/ UART7 1/SPI6/ /SDMMC2/ 2/SWPMI1/ SDMMC1 UART5
/TIM1x/ /OCTO OCTOSPIM SPI3/I2S3/ SAI4/ TIM1x/
/12/15 I2S3/ /USART1/ UART4/5/ SPDIFRX1/ TIM1x/TIM8/ /TIM1x/
TIM2x SPIM_P1/ _P1/TIM15/ SPI4/5/6 SDMMC2/ TIM23
UART4 2/3/6 8 TIM13/14 UART7/9/ TIM8
2/TIM8 USART1/10 TIM8
USART10

FMC_D1
DFSDM1_ DFSDM1_ SAI4_FS_ OTG_HS_ FMC_ LCD_R EVENT
PC0 - 2/FMC_ - - - - FMC_A25 LCD_G2 -
CKIN0 DATIN4 B ULPI_STP SDNWE 5 OUT
AD12

SPI2_MO
TRA DFSDM1_ DFSDM1_C SAI1_SD_ SAI4_SD_ SDMMC2_ OCTOSPI MDIOS_ LCD_G EVENT
PC1 SAI4_D1 - SI/I2S2_S - ETH_MDC -
CED0 DATIN0 KIN4 A A CK M_P1_IO4 MDC 5 OUT
DO

PWR_ SPI2_MIS
DFSDM1_ OCTOSPIM DFSDM1_ OCTOSPIM OTG_HS_ ETH_MII_ FMC_SD EVENT
PC2 DEEP - - O/I2S2_S - - - -
CKIN1 _P1_IO5 CKOUT _P1_IO2 ULPI_DIR TXD2 NE0 OUT
SLEEP DI
DS13315 Rev 3

SPI2_MO
PWR_ DFSDM1_ OCTOSPIM OCTOSPIM OTG_HS_ ETH_MII_ FMC_SD EVENT
PC3 - - SI/I2S2_S - - - - -
SLEEP DATIN1 _P1_IO6 _P1_IO0 ULPI_NXT TX_CLK CKE0 OUT
DO

PWR_ ETH_MII_
FMC_A2 DFSDM1_ SPDIFRX1 SDMMC2_ FMC_SD LCD_R EVENT
PC4 DEEP - - I2S1_MCK - - - RXD0/ETH_ -
2 CKIN2 _IN3 CKIN NE0 7 OUT
SLEEP RMII_RXD0
Prot C

OCTOSPI ETH_MII_
PWR_ DFSDM1_ SPDIFRX1 FMC_SD COMP LCD_ EVENT
PC5 SAI4_D3 SAI1_D3 PSSI_D15 - - - - M_P1_ RXD1/ETH_
SLEEP DATIN2 _IN4 CKE0 1_OUT DE OUT
DQS RMII_RXD1

DCMI_
TIM3_ TIM8_CH DFSDM1_ USART6_ SDMMC1 FMC_ SDMMC2_ SDMMC1 D0/ LCD_ EVENT
PC6 - - I2S2_MCK - -
CH1 1 CKIN3 TX _D0DIR NWAIT D6 _D6 PSSI_ HSYNC OUT
D0

DCMI_
DBTR TIM3_ TIM8_CH DFSDM1_ USART6_ SDMMC1 SDMMC2_ SDMMC1 LCD_G EVENT
PC7 - - I2S3_MCK FMC_NE1 SWPMI_TX D1/PS
GIO CH2 2 DATIN3 RX _D123DIR D7 _D7 6 OUT
SI_D1

UART5_
DCMI_
TRA TIM3_ TIM8_CH USART6_ RTS/ FMC_NE2/ SDMMC1 EVENT
PC8 - - - - FMC_INT SWPMI_RX D2/PS -
CED1 CH3 3 CK UART5_ FMC_NCE _D0 OUT

STM32H730xB
SI_D2
DE

DCMI_
TIM3_C TIM8_CH UART5_ OCTOSPIM SWPMI_SU SDMMC1 LCD_B EVENT
PC9 MCO2 - I2C3_SDA I2S_CKIN I2C5_SDA - LCD_G3 D3/PS
H4 4 CTS _P1_IO0 SPEND _D1 2 OUT
SI_D3
 Table 8. STM32H730xB pin alternate functions (continued)

STM32H730xB
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

DFSDM1/
DFSDM1/ CEC/DCMI/ CRS/FMC/
DFSDM1/ SDMMC1/ LPUART1 FDCAN1/2/ ETH/I2C4/ FMC/LCD
FMC/ LCD/ PSSI/ CEC/ LCD/OCT COMP/
FDCAN3 I2C4/5/ SPI2/I2S2 /SAI4/ FMC/LCD/ LCD/MDIOS /MDIOS/
Port LPTIM1/ LPTIM2/3/ DFSDM1/ FDCAN3/ OSPIM_P1 DCMI/
/PDM_ OCTO /SPI3/I2S SDMMC1/ OCTOSPIM /OCTOSPIM OCTOSPI LCD/
SAI4/ 4/5/ I2C1/2/3/4/5 SPI1/I2S1/ /OTG1_FS/ PSSI/
SYS SAI1/ SPIM_P1/ 3/SPI6/ SPDIFRX _P1/2/SAI4 _P1/SDMMC M_P1/ TIM24/ SYS
TIM16/17 LPUART1 /LPTIM2/ SPI2/I2S2/ OTG1_HS/ LCD/
TIM3/4/5 SAI1/SPI3/ UART7 1/SPI6/ /SDMMC2/ 2/SWPMI1/ SDMMC1 UART5
/TIM1x/ /OCTO OCTOSPIM SPI3/I2S3/ SAI4/ TIM1x/
/12/15 I2S3/ /USART1/ UART4/5/ SPDIFRX1/ TIM1x/TIM8/ /TIM1x/
TIM2x SPIM_P1/ _P1/TIM15/ SPI4/5/6 SDMMC2/ TIM23
UART4 2/3/6 8 TIM13/14 UART7/9/ TIM8
2/TIM8 USART1/10 TIM8
USART10

DCMI_
DFSDM1_ SPI3_SCK/ USART3_ UART4_ OCTOSPIM SDMMC1 D8/ LCD_R EVENT
PC10 - - - I2C5_SDA - LCD_B1 SWPMI_RX
CKIN5 I2S3_CK TX TX _P1_IO1 _D2 PSSI_ 2 OUT
D8

DCMI_
SPI3_
DFSDM1_ USART3_ UART4_ OCTOSPIM SDMMC1 D4/ LCD_B EVENT
PC11 - - - I2C5_SCL - MISO/I2S3 - -
DATIN5 RX RX _P1_NCS _D3 PSSI_ 4 OUT
_SDI
D4

DCMI_
Prot C

FMC_D6/ SPI3_
DS13315 Rev 3

TRAC TIM15_ I2C5_SMB SPI6_SCK USART3_ UART5_ SDMMC1 D9/ LCD_R EVENT
PC12 FMC_AD - MOSI/I2S3 - - -
ED3 CH1 A /I2S6_CK CK TX _CK PSSI_ 6 OUT
6 _SDO
D9

Pinouts, pin descriptions and alternate functions

EVENT
PC13 - - - - - - - - - - - - - - -
OUT

EVENT
PC14 - - - - - - - - - - - - - - -
OUT

EVENT
PC15 - - - - - - - - - - - - - - -
OUT
93/270
 Table 8. STM32H730xB pin alternate functions (continued)

94/270

Pinouts, pin descriptions and alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

DFSDM1/
DFSDM1/ CEC/DCMI/ CRS/FMC/
DFSDM1/ SDMMC1/ LPUART1 FDCAN1/2/ ETH/I2C4/ FMC/LCD
FMC/ LCD/ PSSI/ CEC/ LCD/OCT COMP/
FDCAN3 I2C4/5/ SPI2/I2S2 /SAI4/ FMC/LCD/ LCD/MDIOS /MDIOS/
Port LPTIM1/ LPTIM2/3/ DFSDM1/ FDCAN3/ OSPIM_P1 DCMI/
/PDM_ OCTO /SPI3/I2S SDMMC1/ OCTOSPIM /OCTOSPIM OCTOSPI LCD/
SAI4/ 4/5/ I2C1/2/3/4/5 SPI1/I2S1/ /OTG1_FS/ PSSI/
SYS SAI1/ SPIM_P1/ 3/SPI6/ SPDIFRX _P1/2/SAI4 _P1/SDMMC M_P1/ TIM24/ SYS
TIM16/17 LPUART1 /LPTIM2/ SPI2/I2S2/ OTG1_HS/ LCD/
TIM3/4/5 SAI1/SPI3/ UART7 1/SPI6/ /SDMMC2/ 2/SWPMI1/ SDMMC1 UART5
/TIM1x/ /OCTO OCTOSPIM SPI3/I2S3/ SAI4/ TIM1x/
/12/15 I2S3/ /USART1/ UART4/5/ SPDIFRX1/ TIM1x/TIM8/ /TIM1x/
TIM2x SPIM_P1/ _P1/TIM15/ SPI4/5/6 SDMMC2/ TIM23
UART4 2/3/6 8 TIM13/14 UART7/9/ TIM8
2/TIM8 USART1/10 TIM8
USART10

FMC_D2/
DFSDM1_ UART4_ FDCAN1_ LCD_B EVENT
PD0 - - - - - - - - UART9_CTS FMC_AD -
CKIN6 RX RX 1 OUT
2

FMC_D3/
DFSDM1_ UART4_ FDCAN1_ EVENT
PD1 - - - - - - - - - FMC_AD - -
DATIN6 TX TX OUT
3

DCMI_
FMC_D7/
TRAC TIM3_ TIM15_ UART5_ SDMMC1 D11/ LCD_B EVENT
PD2 FMC_AD - - - - LCD_B7 - -
ED2 ETR BKIN RX _CMD PSSI_ 2 OUT
DS13315 Rev 3

7
D11

USART2_ DCMI_
DFSDM1_ SPI2_SCK CTS/ FMC_ D5/ LCD_G EVENT
PD3 - - - - - - - - -
CKOUT /I2S2_CK USART2_ CLK PSSI_ 7 OUT
NSS D5

USART2_
RTS/ OCTOSPI FMC_ EVENT
PD4 - - - - - - - - - - - -
Port D

USART2_ M_P1_IO4 NOE OUT

DE

USART2_ OCTOSPI FMC_NW EVENT

PD5 - - - - - - - - - - - -
TX M_P1_IO5 E OUT

DCMI_
SPI3_
DFSDM1_ DFSDM1_ SAI1_SD_ USART2_ SAI4_SD_ OCTOSPI SDMMC2_ FMC_ D10/ LCD_B EVENT
PD6 - SAI4_D1 SAI1_D1 MOSI/I2S -
CKIN4 DATIN1 A RX A M_P1_IO6 CK NWAIT PSSI_ 2 OUT
3_SDO
D10

SPI1_
DFSDM1_ DFSDM1_ USART2_ SPDIFRX1 OCTOSPI SDMMC2_ FMC_NE EVENT
PD7 - - - - MOSI/I2S - - -
DATIN4 CKIN1 CK _IN1 M_P1_IO7 CMD 1 OUT
1_SDO

FMC_D1

STM32H730xB
DFSDM1_ USART3_ SPDIFRX1 EVENT
PD8 - - - - - - - - - 3/FMC_A - -
CKIN3 TX _IN2 OUT
D13

FMC_D1
DFSDM1_ USART3_ EVENT
PD9 - - - - - - - - - - 4/FMC_ - -
DATIN3 RX OUT
AD14
 Table 8. STM32H730xB pin alternate functions (continued)

STM32H730xB
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

DFSDM1/
DFSDM1/ CEC/DCMI/ CRS/FMC/
DFSDM1/ SDMMC1/ LPUART1 FDCAN1/2/ ETH/I2C4/ FMC/LCD
FMC/ LCD/ PSSI/ CEC/ LCD/OCT COMP/
FDCAN3 I2C4/5/ SPI2/I2S2 /SAI4/ FMC/LCD/ LCD/MDIOS /MDIOS/
Port LPTIM1/ LPTIM2/3/ DFSDM1/ FDCAN3/ OSPIM_P1 DCMI/
/PDM_ OCTO /SPI3/I2S SDMMC1/ OCTOSPIM /OCTOSPIM OCTOSPI LCD/
SAI4/ 4/5/ I2C1/2/3/4/5 SPI1/I2S1/ /OTG1_FS/ PSSI/
SYS SAI1/ SPIM_P1/ 3/SPI6/ SPDIFRX _P1/2/SAI4 _P1/SDMMC M_P1/ TIM24/ SYS
TIM16/17 LPUART1 /LPTIM2/ SPI2/I2S2/ OTG1_HS/ LCD/
TIM3/4/5 SAI1/SPI3/ UART7 1/SPI6/ /SDMMC2/ 2/SWPMI1/ SDMMC1 UART5
/TIM1x/ /OCTO OCTOSPIM SPI3/I2S3/ SAI4/ TIM1x/
/12/15 I2S3/ /USART1/ UART4/5/ SPDIFRX1/ TIM1x/TIM8/ /TIM1x/
TIM2x SPIM_P1/ _P1/TIM15/ SPI4/5/6 SDMMC2/ TIM23
UART4 2/3/6 8 TIM13/14 UART7/9/ TIM8
2/TIM8 USART1/10 TIM8
USART10

FMC_D1
DFSDM1_ USART3_ LCD_B EVENT
PD10 - - - - - - - - - - 5/FMC_A -
CKOUT CK 3 OUT
D15

USART3_ FMC_A16
LPTIM2_I I2C4_SMB OCTOSPIM SAI4_SD_ EVENT
PD11 - - - - - CTS/USA - - /FMC_CL - -
N2 A _P1_IO0 A OUT
RT3_NSS E

USART3_ FMC_A17 DCMI_

LPTIM1_ TIM4_C LPTIM2_I FDCAN3_ OCTOSPIM SAI4_FS_ EVENT
PD12 - I2C4_SCL - RTS/USA - - /FMC_AL D12/PS -
IN1 H1 N1 RX _P1_IO1 A OUT
RT3_DE E SI_D12
Prot D
DS13315 Rev 3

DCMI_
LPTIM1_ TIM4_C FDCAN3_ OCTOSPIM SAI4_SCK UART9_RTS EVENT
PD13 - - I2C4_SDA - - - FMC_A18 D13/PS -
OUT H2 TX _P1_IO3 _A /UART9_DE OUT
SI_D13

Pinouts, pin descriptions and alternate functions

FMC_D0/
TIM4_C UART8_C EVENT
PD14 - - - - - - - - - UART9_RX FMC_AD - -
H3 TS OUT
0

UART8_R FMC_D1/
TIM4_C EVENT
PD15 - - - - - - - TS/UART - - UART9_TX FMC_AD - -
H4 OUT
8_DE 1
95/270
 Table 8. STM32H730xB pin alternate functions (continued)

96/270

Pinouts, pin descriptions and alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

DFSDM1/
DFSDM1/ CEC/DCMI/ CRS/FMC/
DFSDM1/ SDMMC1/ LPUART1 FDCAN1/2/ ETH/I2C4/ FMC/LCD
FMC/ LCD/ PSSI/ CEC/ LCD/OCT COMP/
FDCAN3 I2C4/5/ SPI2/I2S2 /SAI4/ FMC/LCD/ LCD/MDIOS /MDIOS/
Port LPTIM1/ LPTIM2/3/ DFSDM1/ FDCAN3/ OSPIM_P1 DCMI/
/PDM_ OCTO /SPI3/I2S SDMMC1/ OCTOSPIM /OCTOSPIM OCTOSPI LCD/
SAI4/ 4/5/ I2C1/2/3/4/5 SPI1/I2S1/ /OTG1_FS/ PSSI/
SYS SAI1/ SPIM_P1/ 3/SPI6/ SPDIFRX _P1/2/SAI4 _P1/SDMMC M_P1/ TIM24/ SYS
TIM16/17 LPUART1 /LPTIM2/ SPI2/I2S2/ OTG1_HS/ LCD/
TIM3/4/5 SAI1/SPI3/ UART7 1/SPI6/ /SDMMC2/ 2/SWPMI1/ SDMMC1 UART5
/TIM1x/ /OCTO OCTOSPIM SPI3/I2S3/ SAI4/ TIM1x/
/12/15 I2S3/ /USART1/ UART4/5/ SPDIFRX1/ TIM1x/TIM8/ /TIM1x/
TIM2x SPIM_P1/ _P1/TIM15/ SPI4/5/6 SDMMC2/ TIM23
UART4 2/3/6 8 TIM13/14 UART7/9/ TIM8
2/TIM8 USART1/10 TIM8
USART10

DCMI_
LPTIM1_ TIM4_E LPTIM2_ET UART8_R SAI4_MCL FMC_NB LCD_R EVENT
PE0 - - - - - - - D2/PS
ETR TR R X K_A L0 0 OUT
SI_D2

DCMI_
LPTIM1_I UART8_T FMC_NB LCD_R EVENT
PE1 - - - - - - - - - - D3/PS
N2 X L1 6 OUT
SI_D3

TRAC SAI1_C USART10_ SAI1_MCL SAI4_MC OCTOSPIM ETH_MII_TX EVENT

PE2 - - SPI4_SCK - SAI4_CK1 FMC_A23 - -
ECLK K1 RX K_A LK_A _P1_IO2 D3 OUT
DS13315 Rev 3

TRAC TIM15_BKI SAI1_SD_ SAI4_SD_ USART10_T EVENT

PE3 - - - - - - - FMC_A19 - -
ED0 N B B X OUT

DCMI_
TRAC DFSDM1_ TIM15_CH1 SAI4_FS_ LCD_B EVENT
PE4 - SAI1_D2 SPI4_NSS SAI1_FS_A - - SAI4_D2 - FMC_A20 D4/PS
ED1 DATIN3 N A 0 OUT
SI_D4

DCMI_
TRAC SAI1_C DFSDM1_ SPI4_MIS SAI1_SCK SAI4_SC LCD_G EVENT
PE5 - TIM15_CH1 - - SAI4_CK2 - FMC_A21 D6/PS
Port E

ED2 K2 CKIN3 O _A K_A 0 OUT

SI_D6

DCMI_
TRAC TIM1_BKI SPI4_MO SAI1_SD_ SAI4_SD_ SAI4_MCL TIM1_BKIN2 LCD_G EVENT
PE6 SAI1_D1 - TIM15_CH2 - SAI4_D1 FMC_A22 D7/PS
ED3 N2 SI A A K_B _COMP12 1 OUT
SI_D7

FMC_D4/
TIM1_ET DFSDM1_ UART7_R OCTOSPI EVENT
PE7 - - - - - - - - FMC_AD - -
R DATIN2 X M_P1_IO4 OUT
4

FMC_D5/
TIM1_CH DFSDM1_ UART7_T OCTOSPI COMP EVENT
PE8 - - - - - - - - FMC_AD -
1N CKIN2 X M_P1_IO5 2_OUT OUT
5

UART7_R FMC_D6/
TIM1_CH DFSDM1_ OCTOSPI EVENT
PE9 - - - - - TS/UART - - - FMC_AD - -
1 CKOUT M_P1_IO6 OUT

STM32H730xB
7_DE 6

FMC_D7/
TIM1_CH DFSDM1_ UART7_C OCTOSPI EVENT
PE10 - - - - - - - - FMC_AD - -
2N DATIN4 TS M_P1_IO7 OUT
7
 Table 8. STM32H730xB pin alternate functions (continued)

STM32H730xB
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

DFSDM1/
DFSDM1/ CEC/DCMI/ CRS/FMC/
DFSDM1/ SDMMC1/ LPUART1 FDCAN1/2/ ETH/I2C4/ FMC/LCD
FMC/ LCD/ PSSI/ CEC/ LCD/OCT COMP/
FDCAN3 I2C4/5/ SPI2/I2S2 /SAI4/ FMC/LCD/ LCD/MDIOS /MDIOS/
Port LPTIM1/ LPTIM2/3/ DFSDM1/ FDCAN3/ OSPIM_P1 DCMI/
/PDM_ OCTO /SPI3/I2S SDMMC1/ OCTOSPIM /OCTOSPIM OCTOSPI LCD/
SAI4/ 4/5/ I2C1/2/3/4/5 SPI1/I2S1/ /OTG1_FS/ PSSI/
SYS SAI1/ SPIM_P1/ 3/SPI6/ SPDIFRX _P1/2/SAI4 _P1/SDMMC M_P1/ TIM24/ SYS
TIM16/17 LPUART1 /LPTIM2/ SPI2/I2S2/ OTG1_HS/ LCD/
TIM3/4/5 SAI1/SPI3/ UART7 1/SPI6/ /SDMMC2/ 2/SWPMI1/ SDMMC1 UART5
/TIM1x/ /OCTO OCTOSPIM SPI3/I2S3/ SAI4/ TIM1x/
/12/15 I2S3/ /USART1/ UART4/5/ SPDIFRX1/ TIM1x/TIM8/ /TIM1x/
TIM2x SPIM_P1/ _P1/TIM15/ SPI4/5/6 SDMMC2/ TIM23
UART4 2/3/6 8 TIM13/14 UART7/9/ TIM8
2/TIM8 USART1/10 TIM8
USART10

FMC_D8/
TIM1_CH DFSDM1_ SAI4_SD_ OCTOSPIM LCD_G EVENT
PE11 - - - SPI4_NSS - - - - FMC_AD -
2 CKIN4 B _P1_NCS 3 OUT
8

FMC_D9/
TIM1_CH DFSDM1_ SAI4_SCK COMP LCD_B EVENT
PE12 - - - SPI4_SCK - - - - - FMC_AD
3N DATIN5 _B 1_OUT 4 OUT
9

FMC_D1
Prot E

TIM1_CH DFSDM1_ SPI4_MIS SAI4_FS_ COMP LCD_D EVENT

PE13 - - - - - - - - 0/FMC_A
3 CKIN5 O B 2_OUT E OUT
D10
DS13315 Rev 3

FMC_D11
TIM1_CH SPI4_MO SAI4_MCL LCD_C EVENT
PE14 - - - - - - - - - /FMC_AD -
4 SI K_B LK OUT
11

Pinouts, pin descriptions and alternate functions

FMC_D1 TIM1_B
TIM1_BKI USART10_C LCD_R EVENT
PE15 - - - - - - - - - - 2/FMC_A KIN_C
N K 7 OUT
D12 OMP12
97/270
 Table 8. STM32H730xB pin alternate functions (continued)

98/270

Pinouts, pin descriptions and alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

DFSDM1/
DFSDM1/ CEC/DCMI/ CRS/FMC/
DFSDM1/ SDMMC1/ LPUART1 FDCAN1/2/ ETH/I2C4/ FMC/LCD
FMC/ LCD/ PSSI/ CEC/ LCD/OCT COMP/
FDCAN3 I2C4/5/ SPI2/I2S2 /SAI4/ FMC/LCD/ LCD/MDIOS /MDIOS/
Port LPTIM1/ LPTIM2/3/ DFSDM1/ FDCAN3/ OSPIM_P1 DCMI/
/PDM_ OCTO /SPI3/I2S SDMMC1/ OCTOSPIM /OCTOSPIM OCTOSPI LCD/
SAI4/ 4/5/ I2C1/2/3/4/5 SPI1/I2S1/ /OTG1_FS/ PSSI/
SYS SAI1/ SPIM_P1/ 3/SPI6/ SPDIFRX _P1/2/SAI4 _P1/SDMMC M_P1/ TIM24/ SYS
TIM16/17 LPUART1 /LPTIM2/ SPI2/I2S2/ OTG1_HS/ LCD/
TIM3/4/5 SAI1/SPI3/ UART7 1/SPI6/ /SDMMC2/ 2/SWPMI1/ SDMMC1 UART5
/TIM1x/ /OCTO OCTOSPIM SPI3/I2S3/ SAI4/ TIM1x/
/12/15 I2S3/ /USART1/ UART4/5/ SPDIFRX1/ TIM1x/TIM8/ /TIM1x/
TIM2x SPIM_P1/ _P1/TIM15/ SPI4/5/6 SDMMC2/ TIM23
UART4 2/3/6 8 TIM13/14 UART7/9/ TIM8
2/TIM8 USART1/10 TIM8
USART10

OCTOSPIM TIM23_ EVENT

PF0 - - - - I2C2_SDA - I2C5_SDA - - - - FMC_A0 -
_P2_IO0 CH1 OUT

OCTOSPIM TIM23_ EVENT

PF1 - - - - I2C2_SCL - I2C5_SCL - - - - FMC_A1 -
_P2_IO1 CH2 OUT
DS13315 Rev 3

I2C2_SMB I2C5_SMB OCTOSPIM TIM23_ EVENT

PF2 - - - - - - - - - FMC_A2 -
A A _P2_IO2 CH3 OUT

OCTOSPIM TIM23_ EVENT

PF3 - - - - - - - - - - - FMC_A3 -
_P2_IO3 CH4 OUT
Port F

OCTOSPIM EVENT
PF4 - - - - - - - - - - - FMC_A4 - -
_P2_CLK OUT

OCTOSPIM EVENT
PF5 - - - - - - - - - - - FMC_A5 - -
_P2_NCLK OUT

TIM16_C FDCAN3 SAI1_SD_ UART7_R SAI4_SD_ OCTOSPI TIM23_ EVENT

PF6 - - - SPI5_NSS - - - -
H1 _RX B X B M_P1_IO3 CH1 OUT

TIM17_C FDCAN3 SAI1_MCL UART7_T SAI4_MC OCTOSPI TIM23_ EVENT

PF7 - - - SPI5_SCK - - - -

STM32H730xB
H1 _TX K_B X LK_B M_P1_IO2 CH2 OUT

UART7_R
TIM16_C SPI5_MIS SAI1_SCK SAI4_SC TIM13_CH OCTOSPI TIM23_ EVENT
PF8 - - - - TS/UART - - -
H1N O _B K_B 1 M_P1_IO0 CH3 OUT
7_DE
 Table 8. STM32H730xB pin alternate functions (continued)

STM32H730xB
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

DFSDM1/
DFSDM1/ CEC/DCMI/ CRS/FMC/
DFSDM1/ SDMMC1/ LPUART1 FDCAN1/2/ ETH/I2C4/ FMC/LCD
FMC/ LCD/ PSSI/ CEC/ LCD/OCT COMP/
FDCAN3 I2C4/5/ SPI2/I2S2 /SAI4/ FMC/LCD/ LCD/MDIOS /MDIOS/
Port LPTIM1/ LPTIM2/3/ DFSDM1/ FDCAN3/ OSPIM_P1 DCMI/
/PDM_ OCTO /SPI3/I2S SDMMC1/ OCTOSPIM /OCTOSPIM OCTOSPI LCD/
SAI4/ 4/5/ I2C1/2/3/4/5 SPI1/I2S1/ /OTG1_FS/ PSSI/
SYS SAI1/ SPIM_P1/ 3/SPI6/ SPDIFRX _P1/2/SAI4 _P1/SDMMC M_P1/ TIM24/ SYS
TIM16/17 LPUART1 /LPTIM2/ SPI2/I2S2/ OTG1_HS/ LCD/
TIM3/4/5 SAI1/SPI3/ UART7 1/SPI6/ /SDMMC2/ 2/SWPMI1/ SDMMC1 UART5
/TIM1x/ /OCTO OCTOSPIM SPI3/I2S3/ SAI4/ TIM1x/
/12/15 I2S3/ /USART1/ UART4/5/ SPDIFRX1/ TIM1x/TIM8/ /TIM1x/
TIM2x SPIM_P1/ _P1/TIM15/ SPI4/5/6 SDMMC2/ TIM23
UART4 2/3/6 8 TIM13/14 UART7/9/ TIM8
2/TIM8 USART1/10 TIM8
USART10

TIM17_C SPI5_MO UART7_C SAI4_FS_ TIM14_CH OCTOSPI TIM23_ EVENT

PF9 - - - - SAI1_FS_B - - -
H1N SI TS B 1 M_P1_IO1 CH4 OUT

DCMI_
TIM16_B OCTOSPIM LCD_D EVENT
PF10 - SAI1_D3 - PSSI_D15 - - - - SAI4_D3 - - D11/PS
KIN _P1_CLK E OUT
SI_D11

DCMI_
SPI5_MO OCTOSPIM SAI4_SD_ FMC_NR TIM24_ EVENT
DS13315 Rev 3

PF11 - - - - - - - - - D12/PS
SI _P1_NCLK B AS CH1 OUT
SI_D12
Prot F

Pinouts, pin descriptions and alternate functions

OCTOSPIM TIM24_ EVENT
PF12 - - - - - - - - - - - FMC_A6 -
_P2_DQS CH2 OUT

DFSDM1_ I2C4_SMB TIM24_ EVENT

PF13 - - - - - - - - - - FMC_A7 -
DATIN6 A CH3 OUT

DFSDM1_ TIM24_ EVENT

PF14 - - - I2C4_SCL - - - - - - - FMC_A8 -
CKIN6 CH4 OUT

EVENT
PF15 - - - I2C4_SDA - - - - - - - FMC_A9 - -
OUT

OCTOSPIM EVENT
PG0 - - - - - - - - - - UART9_RX FMC_A10 - -
_P2_IO4 OUT

OCTOSPIM EVENT
PG1 - - - - - - - - - - UART9_TX FMC_A11 - -
_P2_IO5 OUT
Port G-

TIM8_BKI TIM8_BKIN_ TIM24_ EVENT

PG2 - - - - - - - - - - FMC_A12 -
N COMP12 ETR OUT

TIM8_BKI TIM8_BKIN2 TIM23_ EVENT

PG3 - - - - - - - - - - FMC_A13 -
N2 _COMP12 ETR OUT
99/270
 Table 8. STM32H730xB pin alternate functions (continued)

100/270

Pinouts, pin descriptions and alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

DFSDM1/
DFSDM1/ CEC/DCMI/ CRS/FMC/
DFSDM1/ SDMMC1/ LPUART1 FDCAN1/2/ ETH/I2C4/ FMC/LCD
FMC/ LCD/ PSSI/ CEC/ LCD/OCT COMP/
FDCAN3 I2C4/5/ SPI2/I2S2 /SAI4/ FMC/LCD/ LCD/MDIOS /MDIOS/
Port LPTIM1/ LPTIM2/3/ DFSDM1/ FDCAN3/ OSPIM_P1 DCMI/
/PDM_ OCTO /SPI3/I2S SDMMC1/ OCTOSPIM /OCTOSPIM OCTOSPI LCD/
SAI4/ 4/5/ I2C1/2/3/4/5 SPI1/I2S1/ /OTG1_FS/ PSSI/
SYS SAI1/ SPIM_P1/ 3/SPI6/ SPDIFRX _P1/2/SAI4 _P1/SDMMC M_P1/ TIM24/ SYS
TIM16/17 LPUART1 /LPTIM2/ SPI2/I2S2/ OTG1_HS/ LCD/
TIM3/4/5 SAI1/SPI3/ UART7 1/SPI6/ /SDMMC2/ 2/SWPMI1/ SDMMC1 UART5
/TIM1x/ /OCTO OCTOSPIM SPI3/I2S3/ SAI4/ TIM1x/
/12/15 I2S3/ /USART1/ UART4/5/ SPDIFRX1/ TIM1x/TIM8/ /TIM1x/
TIM2x SPIM_P1/ _P1/TIM15/ SPI4/5/6 SDMMC2/ TIM23
UART4 2/3/6 8 TIM13/14 UART7/9/ TIM8
2/TIM8 USART1/10 TIM8
USART10

FMC_A14
TIM1_BKI TIM1_BKIN2 EVENT
PG4 - - - - - - - - - - /FMC_BA - -
N2 _COMP12 OUT
0

FMC_A15
TIM1_ET EVENT
PG5 - - - - - - - - - - - /FMC_BA - -
R OUT
1

OCTOSPI DCMI_
TIM17_B FMC_NE LCD_R EVENT
PG6 - - - - - - - - - M_P1_NC - D12/PS
KIN 3 7 OUT
S SI_D12
DS13315 Rev 3

DCMI_
SAI1_MCL USART6_ OCTOSPIM LCD_C EVENT
PG7 - - - - - - - - - FMC_INT D13/PS
K_A CK _P2_DQS LK OUT
SI_D13

USART6_
TIM8_ET SPI6_NSS SPDIFRX ETH_PPS_ FMC_SD LCD_G EVENT
PG8 - - - - - RTS/USA - - -
R /I2S6_WS 1_IN3 OUT CLK 7 OUT
RT6_DE
Prot G

DCMI_
SPI1_MIS FMC_NE
FDCAN3 USART6_ SPDIFRX OCTOSPIM SAI4_FS_ SDMMC2_D VSYNC EVENT
PG9 - - - - O/I2S1_S - 2/FMC_N -
_TX RX 1_IN4 _P1_IO6 B 0 /PSSI_ OUT
DI CE
RDY

OCTOSPI DCMI_
FDCAN3 SPI1_NSS SAI4_SD_ SDMMC2_D FMC_NE LCD_B EVENT
PG10 - - M_P2_IO - - - - LCD_G3 D2/PS
_RX /I2S1_WS B 1 3 2 OUT
6 SI_D2

ETH_MII_TX DCMI_
LPTIM1_I USART10_ SPI1_SCK SPDIFRX OCTOSPIM SDMMC2_ LCD_B EVENT
PG11 - - - - - _EN/ETH_R - D3/PS
N2 RX /I2S1_CK 1_IN1 _P2_IO7 D2 3 OUT
MII_TX_EN SI_D3

OCTOSPI SPI6_MIS USART6_ ETH_MII_TX

LPTIM1_I USART10_ SPDIFRX SDMMC2_ FMC_NE TIM23_ LCD_B EVENT
PG12 - - M_P2_NC O/I2S6_S - RTS/USA LCD_B4 D1/ETH_RM
N1 TX 1_IN2 D3 4 CH1 1 OUT
S DI RT6_DE II_TXD1

STM32H730xB
USART10_ USART6_ ETH_MII_TX
TRAC LPTIM1_ SPI6_SCK SDMMC2_ TIM23_ LCD_R EVENT
PG13 - - CTS/USAR - CTS/USA - - D0/ETH_RM FMC_A24
ED0 OUT /I2S6_CK D6 CH2 0 OUT
T10_NSS RT6_NSS II_TXD0
 Table 8. STM32H730xB pin alternate functions (continued)

STM32H730xB
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

DFSDM1/
DFSDM1/ CEC/DCMI/ CRS/FMC/
DFSDM1/ SDMMC1/ LPUART1 FDCAN1/2/ ETH/I2C4/ FMC/LCD
FMC/ LCD/ PSSI/ CEC/ LCD/OCT COMP/
FDCAN3 I2C4/5/ SPI2/I2S2 /SAI4/ FMC/LCD/ LCD/MDIOS /MDIOS/
Port LPTIM1/ LPTIM2/3/ DFSDM1/ FDCAN3/ OSPIM_P1 DCMI/
/PDM_ OCTO /SPI3/I2S SDMMC1/ OCTOSPIM /OCTOSPIM OCTOSPI LCD/
SAI4/ 4/5/ I2C1/2/3/4/5 SPI1/I2S1/ /OTG1_FS/ PSSI/
SYS SAI1/ SPIM_P1/ 3/SPI6/ SPDIFRX _P1/2/SAI4 _P1/SDMMC M_P1/ TIM24/ SYS
TIM16/17 LPUART1 /LPTIM2/ SPI2/I2S2/ OTG1_HS/ LCD/
TIM3/4/5 SAI1/SPI3/ UART7 1/SPI6/ /SDMMC2/ 2/SWPMI1/ SDMMC1 UART5
/TIM1x/ /OCTO OCTOSPIM SPI3/I2S3/ SAI4/ TIM1x/
/12/15 I2S3/ /USART1/ UART4/5/ SPDIFRX1/ TIM1x/TIM8/ /TIM1x/
TIM2x SPIM_P1/ _P1/TIM15/ SPI4/5/6 SDMMC2/ TIM23
UART4 2/3/6 8 TIM13/14 UART7/9/ TIM8
2/TIM8 USART1/10 TIM8
USART10

USART10_ SPI6_MO ETH_MII_TX

TRAC LPTIM1_ USART6_ OCTOSPIM SDMMC2_ TIM23_ LCD_B EVENT
PG14 - - RTS/USAR SI/I2S6_S - - D1/ETH_RM FMC_A25
ED1 ETR TX _P1_IO7 D7 CH3 0 OUT
T10_DE DO II_TXD1
Prot G

USART6_ DCMI_
OCTOSPIM USART10_C FMC_NC EVENT
PG15 - - - - - - - CTS/USA - - D13/PS -
_P2_DQS K AS OUT
RT6_NSS SI_D13

EVENT
PH0 - - - - - - - - - - - - - - -
OUT
DS13315 Rev 3

EVENT
PH1 - - - - - - - - - - - - - - -
OUT

LPTIM1_I OCTOSPIM SAI4_SCK ETH_MII_C FMC_SD LCD_R EVENT

PH2 - - - - - - - - -

Pinouts, pin descriptions and alternate functions

N2 _P1_IO4 _B RS CKE0 0 OUT

OCTOSPIM SAI4_MCL ETH_MII_C FMC_SD LCD_R EVENT

PH3 - - - - - - - - - -
_P1_IO5 K_B OL NE0 1 OUT

OTG_HS_ PSSI_ LCD_G EVENT

PH4 - - - - I2C2_SCL - - - - LCD_G5 - -
ULPI_NXT D14 4 OUT

FMC_SD EVENT
PH5 - - - - I2C2_SDA SPI5_NSS - - - - - - - -
Port H

NWE OUT

DCMI_
TIM12_ I2C2_SMB ETH_MII_R FMC_SD EVENT
PH6 - - - SPI5_SCK - - - - - D8/PS -
CH1 A XD2 NE1 OUT
SI_D8

DCMI_
SPI5_MIS ETH_MII_R FMC_SD EVENT
PH7 - - - - I2C3_SCL - - - - - D9/PS -
O XD3 CKE1 OUT
SI_D9

DCMI_
TIM5_E FMC_D1 HSYNC LCD_R EVENT
PH8 - - - I2C3_SDA - - - - - - -
TR 6 /PSSI_ 2 OUT
DE

DCMI_
TIM12_ I2C3_SMB FMC_D1 LCD_R EVENT
PH9 - - - - - - - - - - D0/PS
101/270

CH2 A 7 3 OUT
SI_D0
 Table 8. STM32H730xB pin alternate functions (continued)

102/270

Pinouts, pin descriptions and alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

DFSDM1/
DFSDM1/ CEC/DCMI/ CRS/FMC/
DFSDM1/ SDMMC1/ LPUART1 FDCAN1/2/ ETH/I2C4/ FMC/LCD
FMC/ LCD/ PSSI/ CEC/ LCD/OCT COMP/
FDCAN3 I2C4/5/ SPI2/I2S2 /SAI4/ FMC/LCD/ LCD/MDIOS /MDIOS/
Port LPTIM1/ LPTIM2/3/ DFSDM1/ FDCAN3/ OSPIM_P1 DCMI/
/PDM_ OCTO /SPI3/I2S SDMMC1/ OCTOSPIM /OCTOSPIM OCTOSPI LCD/
SAI4/ 4/5/ I2C1/2/3/4/5 SPI1/I2S1/ /OTG1_FS/ PSSI/
SYS SAI1/ SPIM_P1/ 3/SPI6/ SPDIFRX _P1/2/SAI4 _P1/SDMMC M_P1/ TIM24/ SYS
TIM16/17 LPUART1 /LPTIM2/ SPI2/I2S2/ OTG1_HS/ LCD/
TIM3/4/5 SAI1/SPI3/ UART7 1/SPI6/ /SDMMC2/ 2/SWPMI1/ SDMMC1 UART5
/TIM1x/ /OCTO OCTOSPIM SPI3/I2S3/ SAI4/ TIM1x/
/12/15 I2S3/ /USART1/ UART4/5/ SPDIFRX1/ TIM1x/TIM8/ /TIM1x/
TIM2x SPIM_P1/ _P1/TIM15/ SPI4/5/6 SDMMC2/ TIM23
UART4 2/3/6 8 TIM13/14 UART7/9/ TIM8
2/TIM8 USART1/10 TIM8
USART10

DCMI_
TIM5_C I2C4_SMB FMC_D1 LCD_R EVENT
PH10 - - - - - - - - - - D1/PS
H1 A 8 4 OUT
SI_D1

DCMI_
TIM5_C FMC_D1 LCD_R EVENT
PH11 - - - I2C4_SCL - - - - - - - D2/PS
H2 9 5 OUT
SI_D2

DCMI_
TIM5_C FMC_D2 LCD_R EVENT
PH12 - - - I2C4_SDA - - - - - - - D3/PS
H3 0 6 OUT
Prot H

SI_D3
DS13315 Rev 3

TIM8_CH UART4_T FDCAN1_T FMC_D2 LCD_G EVENT

PH13 - - - - - - - - - -
1N X X 1 2 OUT

DCMI_
TIM8_CH UART4_R FDCAN1_R FMC_D2 LCD_G EVENT
PH14 - - - - - - - - - D4/PS
2N X X 2 3 OUT
SI_D4

DCMI_
TIM8_CH FMC_D2 LCD_G EVENT
PH15 - - - - - - - - - - - D11/PS
3N 3 4 OUT
SI_D11

TIM1_CH TIM8_CH UART8_T LCD_G EVENT

PJ8 - - - - - - - - - - -
3N 1 X 1 OUT

TIM1_CH TIM8_CH UART8_R LCD_G EVENT

PJ9 - - - - - - - - - - -
3 1N X 2 OUT
Port J

TIM1_CH TIM8_CH SPI5_MO LCD_G EVENT

PJ10 - - - - - - - - - - -
2N 2 SI 3 OUT

TIM1_CH TIM8_CH SPI5_MIS LCD_G EVENT

PJ11 - - - - - - - - - - -
2 2N O 4 OUT

STM32H730xB
STM32H730xB Electrical characteristics

6 Electrical characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of junction temperature, supply voltage and frequencies by tests in production on
100% of the devices with an junction temperature at TJ = 25 °C and TJ = TJmax (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean±3σ).

6.1.2 Typical values

Unless otherwise specified, typical data are based on TJ = 25 °C, VDD = 3.3 V (for the
1.7 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 11.

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 12.

Figure 11. Pin loading conditions Figure 12. Pin input voltage

MCU pin MCU pin

C = 50 pF VIN

MS19011V2 MS19010V2

DS13315 Rev 3 103/270

240
Electrical characteristics STM32H730xB

6.1.6 Power supply scheme

Figure 13. Power supply scheme

VDDSMPS
VLXSMPS Step
VFBSMPS Down
Converter
VSSSMPS

VCAP
LDO Core domain (VCORE)
VDDLDO voltage
regulator

Power

Power
switch

switch
VSS
D3 domain
(System
Level shifter

logic, D1 domain
IO EXTI, D2 domain (CPU, peripherals,
IOs (peripherals, RAM)
logic Peripherals,
RAM) RAM) Flash

VSS

VDD domain
LSI, HSI,
VDD CSI, HSI48, Power
VBAT HSE, PLLs switch
Backup domain
charging
VSW Backup VBKP
VBAT regulator
Power switch

LSE, RTC,
Wakeup logic, Backup
BKUP IO backup RAM
IOs logic registers, Reset

VSS
VSS
VDD50USB USB regulator VSS

VDD33USB
USB
FS IOs

VDDA Analog domain

REF_BUF ADC, DAC

VREF+ OPAMP,
VREF+
Comparator
VREF- VREF-

VSSA

MSv63814V5

1. Refer to application note AN5419 “Getting started with STM32H723/733, STM32H725/735 and
STM32H730 Value Line hardware development“ for the possible power scheme and connected capacitors.

104/270 DS13315 Rev 3

STM32H730xB Electrical characteristics

6.1.7 Current consumption measurement

Figure 14. Current consumption measurement scheme

LDO ON SMPS ON

IDD_VBAT IDD_VBAT
VBAT VBAT

IDD IDD
VDD VDD

VDDLDO VDDSMPS

VDDA VDDA

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 9: Voltage characteristics,
Table 10: Current characteristics, and Table 11: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and the functional operation
of the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are
available on demand.

Table 9. Voltage characteristics

Symbols Ratings Min Max Unit

External main supply voltage (including VDD,

VDDX - VSS(1) −0.3 4.0 V
VDDLDO, VDDSMPS, VDDA, VDD33USB, VBAT)
Min(VDD, VDDA,
Input voltage on FT_xxx pins VSS−0.3 VDD33USB, VBAT) V
+4.0(3)(4)
VIN(2) Input voltage on TT_xx pins VSS−0.3 4.0 V
Input voltage on BOOT0 pin VSS 9.0 V
Input voltage on any other pins VSS-0.3 4.0 V
Variations between different VDDX power
|∆VDDX| - 50 mV
pins of the same domain
Variations between all the different ground
|VSSx-VSS| - 50 mV
pins
1. All main power (VDD, VDDA, VDD33USB, VDDSMPS, VBAT) and ground (VSS, VSSA) pins must always be
connected to the external power supply, in the permitted range.
2. VIN maximum must always be respected.
3. This formula has to be applied on power supplies related to the IO structure described by the pin definition
table.

DS13315 Rev 3 105/270

240
Electrical characteristics STM32H730xB

4. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled.

Table 10. Current characteristics

Symbols Ratings Max Unit

ΣIVDD (1)
Total current into sum of all VDD power lines (source) 620
ΣIVSS Total current out of sum of all VSS ground lines (sink)(1) 620
IVDD Maximum current into each VDD power pin (source)(1) 100
(1)
IVSS Maximum current out of each VSS ground pin (sink) 100
Output current sunk by any I/O and control pin, except Px_C 20
IIO
Output current sunk by Px_C pins 1
mA
Total output current sunk by sum of all I/Os and control pins(2) 140
ΣI(PIN)
Total output current sourced by sum of all I/Os and control pins(2) 140
Injected current on FT_xxx, TT_xx, RST and B pins except PA4,
−5/+0
IINJ(PIN) (3)(4) PA5
Injected current on PA4, PA5 −0/0
ΣIINJ(PIN) Total injected current (sum of all I/Os and control pins)(5) ±25
1. All main power (VDD, VDDA, VDD33USB) and ground (VSS, VSSA) pins must always be connected to the
external power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
QFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer also to Table 9: Voltage characteristics for the maximum allowed input voltage
values.
5. When several inputs are submitted to a current injection, the maximum ∑IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).

Table 11. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range − 65 to +150 °C

Maximum junction
TJ Industrial temperature range 6 125
temperature

106/270 DS13315 Rev 3

STM32H730xB Electrical characteristics

6.3 Operating conditions

6.3.1 General operating conditions

Table 12. General operating conditions

Operating
Symbol Parameter Min Typ Max Unit
conditions

VDD Standard operating voltage - 1.62(1) -

3.6
Supply voltage for the internal
VDDLDO VDDLDO ≤ VDD 1.62(1) - 3.6
regulator
Supply voltage for the internal
VDDSMPS VDDSMPS = VDD 1.62(1) - 3.6
SMPS Step-down converter
USB regulator ON 4 5 5.5
VDD50USB -
USB regulator OFF - VDD33USB -

Standard operating voltage, USB USB used 3.0 - 3.6

VDD33USB
domain USB not used 0 - 3.6
ADC or COMP used 1.62 -
DAC used 1.8 -
OPAMP used 2.0 - V
VDDA Analog operating voltage 3.6
VREFBUF used 1.8 -
ADC, DAC, OPAMP,
COMP, VREFBUF not 0 -
used

VBAT Supply voltage for Backup domain - 1.2(2) - 3.6

TT_xx I/O −0.3 - VDD+0.3

BOOT0 0 - 9
Min(VDD,
VIN I/O Input voltage
VDDA,
All I/O except BOOT0
−0.3 - VDD33USB)
and TT_xx
+3.6V <
5.5V(3)
VOS3 0.95 1.0 1.05

Internal regulator ON (LDO or VOS2 1.05 1.10 1.15

SMPS)(4) VOS1 1.15 1.21 1.26
VOS0 1.30 1.36 1.40
VCORE V
VOS3 0.98 1.03 1.08
Regulator OFF: external VCORE VOS2 1.08 1.13 1.18
voltage must be supplied from
external regulator on VCAP pins VOS1 1.18 1.23 1.28
VOS0 1.33 1.38 1.40

DS13315 Rev 3 107/270

240
Electrical characteristics STM32H730xB

Table 12. General operating conditions (continued)

Operating
Symbol Parameter Min Typ Max Unit
conditions

VOS3 - - 170
VOS2 - - 300
VOS1 - - 400
fCPU Arm® Cortex®-M7 clock frequency
VOS0 - - 520
VOS0 and
- - 550
CPU_FREQ_BOOST
VOS3 - - 85
VOS2 - - 150
fACLK AXI clock frequency
VOS1 - - 200
MHz
VOS0 - - 275
VOS3 - - 85
VOS2 - - 150
fHCLK AHB clock frequency
VOS1 - - 200
VOS0 - - 275
VOS3 - - 42.5(5)
VOS2 - - 75
fPCLK APB clock frequency
VOS1 - - 100
VOS0 - - 137.5
Ambient temperature for Maximum power
−40 125
temperature range 3 dissipation
Maximum power
TA(6) −40 85 °C
Ambient temperature for dissipation
temperature range 6 Low-power
−40 105
dissipation(7)
1. When RESET is released, the functionality is guaranteed down to VPDRmax or down to the specified VDDmin when the PDR
is OFF. The PDR can only be switched OFF though the PDR_ON pin that not available in all packages.
2. VBAT minimum value can be reduced to 0 V if VDD is present.
3. This formula has to be applied on power supplies related to the I/O structure described by the pin definition table.
4. At startup, the external VCORE voltage must remain higher or equal to 1.10 V before disabling the internal regulator (LDO).
5. This value corresponds to the maximum APB clock frequency when at least one peripheral is enabled.
6. The device junction temperature must be kept below maximum TJ indicated in Table 13: Supply voltage and maximum
temperature configuration and the maximum temperature.
7. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.8:
Thermal characteristics).

108/270 DS13315 Rev 3

STM32H730xB Electrical characteristics

Table 13. Supply voltage and maximum temperature configuration

Power scale VCORE source Max. TJ (°C)(1) Min. VDD(V) Min. VDDLDO (V)

SMPS 2.2 -
LDO 1.7 1.7
VOS0 105
(2)
SMPS supplies LDO 3 1.7
External (Bypass) 1.62 1.62
140 2.2 -
SMPS
1.62 -
VOS1 LDO 1.62 1.62
125
SMPS supplies LDO 2.3 -
External (Bypass) 1.62 -
SMPS 140 1.62 -
LDO 1.62 1.62
VOS2
SMPS supplies LDO 125 2.3 -
External (Bypass) 1.62 -
SMPS 140 1.62 -
LDO 1.62 1.62
VOS3
SMPS supplies LDO 125 2.3 -
external (Bypass)E 1.62 -
SMPS 140 1.62 -
125 2 2
LDO
105 1.62 1.62
SVOS4/SVOS5
(2)
125 3 2
SMPS supplies LDO
105 2.3 -
External (Bypass) 125 1.62 -
1. 140 °C can be reached only for part numbers in temperature range 3. For part numbers in temperature
range 6, this value must be decreased to 125 °C.
2. The SMPS must be configured to output 2,5 V.

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6.3.2 VCAP external capacitor

Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to
the VCAP pin. CEXT is specified in Table 14. Two external capacitors can be connected to
VCAP pins.

Figure 15. External capacitor CEXT

ESR

R Leak
MS19044V2

1. Legend: ESR is the equivalent series resistance.

Table 14. VCAP operating conditions(1)

Symbol Parameter Conditions

CEXT Capacitance of external capacitor 2.2 µF(2)(3)

ESR ESR of external capacitor < 100 mΩ
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
2. This value corresponds to CEXT typical value. A variation of +/-20% is tolerated.
3. If a third VCAP pin is available on the package, it must be connected to the other VCAP pins but no
additional capacitor is required.

6.3.3 SMPS step-down converter

The devices embed a high power efficiency SMPS step-down converter. SMPS
characteristics for external usage are given in Table 16. The SMPS step-down converter
requires external components that are fully described in AN5419 “Getting started with
STM32H723/733, STM32H725/735 and STM32H730 Value Line hardware development”,
The components used for datasheet characterization are specified in Figure 16 and
Table 15.

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Figure 16. External components for SMPS step-down converter

VDD VDDSMPS VDD VDDSMPS

Cin L VLXSMPS Cin L VLXSMPS

SMPS SMPS
VFBSMPS Cfilt VFBSMPS Cfilt
(ON) VVDD_ (ON)
DD_
External
External
Cout1 VSSSMPS 2xCou1 VSSSMPS

VCAP VCAP

VDDLDO VVCORE
CORE VDDLDO VVCORE
CORE

Voltage Voltage
Cout2 regulator Cout2 regulator
VSS (OFF) VSS (ON)

External SMPS supply, LDO supplied

Direct SMPS supply
by SMPS
MSv61398V4

Table 15. Characteristics of SMPS step-down converter external components

Symbol Parameter Conditions

Capacitance of external capacitor on VDDSMPS 4.7 µF

Cin
ESR of external capacitor 100 mΩ
Cfilt Capacitance of external capacitor on VLXSMPS pin 220 pF
Capacitance of external capacitor on VFBSMPS pin 10 µF
COUT
ESR of external capacitor 20 mΩ
L Inductance of external Inductor on VLXSMPS pin 2.2 µH
- Serial DC resistor 150 mΩ
DC current at which the inductance drops 30% from
ISAT 1.7 A
its value without current.
Average current for a 40 °C rise: rated current for
IRMS which the temperature of the inductor is raised 40°C 1.4 A
by DC current

Table 16. SMPS step-down converter characteristics for external usage

Parameters Conditions Min Typ Max Unit

VOUT = 1.8 V 2.3 - 3.6

VDDSMPS(1) V
VOUT = 2.5 V 3 - 3.6
2.25 2.5 2.75
VOUT(2) Iout=600 mA V
1.62 1.8 1.98
internal and external usage - - 600
IOUT mA
(3)
External usage only - - 600
RDSON - - 100 120 mΩ

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Table 16. SMPS step-down converter characteristics for external usage (continued)
Parameters Conditions Min Typ Max Unit

IDDSMPS_Q Quiescent current - 220 - µA

VOUT = 1.8 V - 270 405
TSMPS_START µs
VOUT = 2.5 V - 360 540
1. The switching frequency is 2.4 MHz±10%
2. Including line transient and load transient.
3. These characteristics are given for SDEXTHP bit is set in the PWR_CR3 register.

Table 17. Inrush current and inrush electric charge characteristics for LDO and
SMPS(1)(2)
Symbol Parameter Conditions - Min Typ Max Unit

Inrush current on voltage on VDDLDO(3) - - 55 96(4)

regulator power-on
(POR or wakeup from SMPS supplies
on VDDSMPS(5) - 100 420(6)
Standby) the VDDCORE

SMPS supplies
internal LDO, - 130 400(6)
VOUT = 1. 8 V(7)
SMPS supplies
internal LDO, - - 300(6)
Inrush current on voltage VOUT = 2.5 V(7)
regulator power-on on VDDSMPS(5)
(POR) SMPS supplies
IRUSH mA
external circuit, - 100 320(6)
VOUT = 1.8 V(7)
SMPS supplies
external circuit, - - 240(6)
VOUT = 2.5 V(7)
SMPS supplies
internal LDO, - 170 530(6)
Inrush current on voltage VOUT = 1.8 V
regulator power-on on VDDSMPS(5)
(wakeup from Standby) SMPS supplies
internal LDO, - 240 550(6)
VOUT = 2.5 V

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Table 17. Inrush current and inrush electric charge characteristics for LDO and
SMPS(1)(2) (continued)
Symbol Parameter Conditions - Min Typ Max Unit

Inrush current on voltage on VDDLDO(3) - - 4.4 5.3 (4)

regulator power-on
(POR or wakeup from SMPS supplies
on VDDSMPS(5) - 7.3 18(6)
Standby) the VDDCORE

SMPS supplies
internal LDO, - 17(6)
VOUT = 1. 8 V(7)
8.8
SMPS supplies
internal LDO, - 13(6)
Inrush current on voltage VOUT = 2.5 V(7)
regulator power-on on VDDSMPS(5)
(POR) SMPS supplies
QRUSH μC
external circuit, - 13.7(6)
VOUT = 1.8 V(7)
7.3
SMPS supplies
external circuit, - 10.5(6)
VOUT = 2.5 V(7)
SMPS supplies
internal LDO, - 15.0 28(6)
Inrush current on voltage VOUT = 1.8 V
regulator power-on on VDDSMPS(5)
(wakeup from Standby) SMPS supplies
internal LDO, - 28.0 39(6)
VOUT = 2.5 V
1. The typical values are given for VDDLDO = VDDSMPS = 3.3 V and for typical decoupling capacitor values of
CEXT and COUT.
2. The product consumption (on VDDCORE) is not taken into account in the inrush current and inrush electric
charges.
3. The inrush current and inrush electric charge on VDDLDO are not present in Bypass mode or when the
SMPS supplies the VDDCORE.
4. The maximum value is given for the maximum decoupling capacitor CEXT.
5. The inrush current and inrush electric charges on VDDSMPS are not present if the external component (L
or COUT) is not present that is if the SMPS is not used.
6. The maximum value is given for the maximum decoupling capacitor COUT and the minimum VDDSMPS
voltage.
7. The inrush current due to transition from 1.2 V to the final VOUT Value (1.8 V or 2.5 V) is not taken into
account.

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6.3.4 Operating conditions at power-up / power-down

Subject to general operating conditions for TA.

Table 18. Operating conditions at power-up/power-down

Symbol Parameter Min Max Unit

VDD rise time rate 0 ∞

tVDD
VDD fall time rate 10 ∞
VDDA rise time rate 0 ∞
tVDDA
VDDA fall time rate 10 ∞
µs/V
VDDUSB rise time rate 0 ∞
tVDDUSB
VDDUSB fall time rate 10 ∞
VCORE rise time rate(2) 0 285
tVCORE(1)
VCORE fall time rate 10 ∞
1. tVCORE should be achieved when VCORE is provided by an external supply voltage (bypass with
VDDLDO = VCORE).
2. VCORE rising slope must respect the above constraints. There are no constraints on the delay between VDD
rising and VCORE rising,

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6.3.5 Embedded reset and power control block characteristics

The parameters given in Table 19 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 12: General operating
conditions.

Table 19. Reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

Reset temporization
tRSTTEMPO(1) - - 377 550 µs
after BOR0 released

Power-on/power-down reset Rising edge(1) 1.62 1.67 1.71

VPOR/PDR
threshold Falling edge 1.58 1.62 1.68
Rising edge 2.04 2.10 2.15
VBOR1 Brown-out reset threshold 1
Falling edge 1.95 2.00 2.06
Rising edge 2.34 2.41 2.47
VBOR2 Brown-out reset threshold 2
Falling edge 2.25 2.31 2.37
Rising edge 2.63 2.70 2.78
VBOR3 Brown-out reset threshold 3
Falling edge 2.54 2.61 2.68

Programmable Voltage Rising edge 1.90 1.96 2.01

VPVD0
Detector threshold 0 Falling edge 1.81 1.86 1.91

Programmable Voltage Rising edge 2.05 2.10 2.16

VPVD1 V
Detector threshold 1 Falling edge 1.96 2.01 2.06

Programmable Voltage Rising edge 2.19 2.26 2.32

VPVD2
Detector threshold 2 Falling edge 2.10 2.15 2.21

Programmable Voltage Rising edge 2.35 2.41 2.47

VPVD3
Detector threshold 3 Falling edge 2.25 2.31 2.37

Programmable Voltage Rising edge 2.49 2.56 2.62

VPVD4
Detector threshold 4 Falling edge 2.39 2.45 2.51

Programmable Voltage Rising edge 2.64 2.71 2.78

VPVD5
Detector threshold 5 Falling edge 2.55 2.61 2.68

Programmable Voltage Rising edge 2.78 2.86 2.94

VPVD6
Detector threshold 6 Falling edge in Run mode 2.69 2.76 2.83
Hysteresis voltage for
VPOR/PDR Hysteresis in Run mode - 43.00 -
Power-on/power-down reset mV
Vhyst_BOR_PVD Hysteresis voltage for BOR Hysteresis in Run mode - 100 -
BOR and PVD consumption
IDD_BOR_PVD(1) - - - 0.630
from VDD
µA
POR and PVD consumption
IDD_POR_PVD - 0.8 - 1.200
from VDD

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Table 19. Reset and power control block characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

Analog voltage detector for Rising edge 1.66 1.71 1.76

VAVM_0
VDDA threshold 0 Falling edge 1.56 1.61 1.66

Analog voltage detector for Rising edge 2.06 2.12 2.19

VAVM_1
VDDA threshold 1 Falling edge 1.96 2.02 2.08
V
Analog voltage detector for Rising edge 2.42 2.50 2.58
VAVM_2
VDDA threshold 2 Falling edge 2.35 2.42 2.49

Analog voltage detector for Rising edge 2.74 2.83 2.91

VAVM_3
VDDA threshold 3 Falling edge 2.64 2.72 2.80
Hysteresis of VDDA voltage
Vhyst_VDDA - - 100 - mV
detector
PVM consumption from
IDD_PVM - - - 0.25 µA
VDD(1)
Voltage detector
IDD_VDDA Resistor bridge - - 2.5 µA
consumption on VDDA(1)
1. Guaranteed by design.

6.3.6 Embedded reference voltage characteristics

The parameters given in Table 20 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 12: General operating
conditions.

Table 20. Embedded reference voltage

Symbol Parameter Conditions Min Typ Max Unit
VREFINT Internal reference voltages -40°C < TJ < TJmax 1.180 1.216 1.255 V
ADC sampling time when
tS_vrefint(1)(2)
(3) reading the internal reference - 4.3 - -
voltage
VBAT sampling time when
µs
tS_vbat(2) reading the internal VBAT - 9 - -
reference voltage
Start time of reference voltage
tstart_vrefint(2) - - - 4.4
buffer when ADC is enable
Reference Buffer
Irefbuf(2) VDD = 3.3 V 9 13.5 23 µA
consumption for ADC
Internal reference voltage
ΔVREFINT(2) spread over the temperature -40°C < TJ < TJmax - 5 15 mV
range
Average temperature Average temperature
Tcoeff(2) - 20 70 ppm/°C
coefficient coefficient
VDDcoeff(2) Average Voltage coefficient 3.0 V < VDD < 3.6 V - 10 1370 ppm/V

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Table 20. Embedded reference voltage (continued)

Symbol Parameter Conditions Min Typ Max Unit
VREFINT_DIV1 1/4 reference voltage - - 25 -
%
VREFINT_DIV2 1/2 reference voltage - - 50 -
VREFINT
VREFINT_DIV3 3/4 reference voltage - - 75 -
1. The shortest sampling time for the application can be determined by multiple iterations.
2. Guaranteed by design.
3. Guaranteed by design. and tested in production at 3.3 V.

Table 21. Internal reference voltage calibration values

Symbol Parameter Memory address

VREFIN_CAL Raw data acquired at temperature of 30 °C, VDDA = 3.3 V 1FF1 E860 - 1FF1 E861

6.3.7 Embedded USB regulator characteristics

The parameters given in Table 22 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 12: General operating
conditions.

Table 22. USB regulator characteristics

Symbol Parameter Conditions Min Typ Max Unit

VDD50USB Supply voltage - 4 5 5.5 V

IDD50USB Current consumption - - 14 - µA
VREGOUTV33V Regulated output voltage - 3 - 3.6 V
Output current load sinked by
IOUT - - - 20 mA
USB block
TWKUP Wakeup time - - 120 170 us

6.3.8 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 14: Current consumption
measurement scheme.
All the run-mode current consumption measurements given in this section are performed
with a CoreMark code.

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Typical and maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in analog input mode.
• All peripherals are disabled except when explicitly mentioned.
• The Flash memory access time is adjusted with the minimum wait states number,
depending on the fACLK frequency (refer to the table “Number of wait states according to
CPU clock (frcc_c_ck) frequency and VCORE range” available in the reference manual).
• When the peripherals are enabled, the AHB clock frequency is the CPU frequency
divided by 2 and the APB clock frequency is AHB clock frequency divided by 2.
• For typical values, the power supply is 3 V unless otherwise specified.
The parameters given in the below tables are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 12: General operating
conditions.

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Table 23. Typical and maximum current consumption in Run mode,

code with data processing running from ITCM(1)
Max
Typ Max LDO regulator ON(2) SMPS
Typ
Symbol Parameter Conditions
frcc_c_ck LDO
SMPS ON(3) Unit
(MHz) regulator
ON
ON TJ = TJ = TJ = TJ = TJ =
25 °C 85 °C 105 °C 125 °C 140 °C

VOS0 550 145 81 170 260 330 - -

(4)
520 135 76 160 260 320 - -
520 135 76 160 260 320 - -
480 125 72.5 150 250 310 - -
VOS0
450 115 67.5 150 240 300 - -
400 105 60 130 230 290 - -
400 90.5 47 110 170 220 280 160
VOS1
300 69.5 36.5 84 150 200 260 150
All
peripherals 300 63 31.5 74 130 170 220 110
disabled
280 58 29 69 120 160 210 110
VOS2
216 45.5 22.5 56 110 150 200 110
200 42 21 53 110 140 200 110
Supply 170 32.5 15 40 80 110 160 74
IDD current in mA
Run mode 168 32 15 40 79 110 160 74
VOS3 144 28 13.5 36 75 110 150 74
60 13.5 6.7 21 61 90 140 67
25 6.9 3.6 14 54 83 130 67

VOS0 550 215 125 250 360 430 - -

(4)
520 205 120 240 350 420 - -
520 205 120 240 350 420 - -
VOS0
400 160 92.5 190 300 370 - -
All
peripherals 400 135 72 160 230 290 360 200
enabled VOS1
300 105 54.5 130 200 250 330 180
300 95 46.5 110 170 210 280 140
VOS2
280 88 43 100 160 210 270 140
VOS3 170 49 22.5 58 110 140 190 93
1. Data are in DTCM for best computation performance, the cache has no influence on consumption in this case.
2. Guaranteed by characterization results, unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS
maximum consumption.
3. The parameter values given in the above table for the SMPS regulator are extrapolated from the LDO consumption and typical SMPS
efficiency factors.
4. CPU_FREQ_BOOST is enabled.

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Table 24. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache ON(1)
Max
Typ Max LDO regulator ON(2) SMPS
Typ
Symbol Parameter Conditions
frcc_c_ck LDO
SMPS ON(3) Unit
(MHz) regulator
ON
ON TJ = TJ = TJ = TJ = TJ =
25 °C 85 °C 105 °C 125 °C 140 °C

VOS0 550 145 83.5 170 270 330 - -

(4)
520 140 78.5 170 260 320 - -

520 140 78.5 170 260 320 - -

VOS0
400 110 62 140 230 290 - -

400 92 48.5 110 180 220 290 160

VOS1
300 71 37.5 86 150 200 260 150

300 64 32 75 130 170 220 110

All 280 59 29.5 70 120 160 210 110
peripherals
disabled VOS2 216 46.5 23 - - - - -

200 42.5 21.5 53 110 140 200 110

180 36 17 43 83 120 160 85

170 33.5 15.5 41 81 110 160 74

Supply
IDD current in 168 33 15.5 - - - - - mA
Run mode
VOS3 144 29 13.5 - - - - -

60 14 6.85 - - - - -

25 6.85 3.7 - - - - -

VOS0 550 220 130 250 360 430 - -

(4)
520 210 120 240 350 420 - -

520 210 120 240 350 420 - -

VOS0
400 160 94.5 190 300 370 - -
All
peripherals 400 140 73 160 240 290 360 200
enabled VOS1
300 105 55.5 130 200 250 330 180

300 96 47 110 170 210 280 140

VOS2
280 89 43.5 110 160 210 270 140

VOS3 170 50 23 59 110 140 190 93

1. Data are in DTCM for best computation performance, the cache has no influence on consumption in this case.
2. Guaranteed by characterization results, unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for
the SMPS maximum consumption.
3. The parameter values given in the above table for the SMPS regulator are extrapolated from the LDO consumption and
typical SMPS efficiency factors.
4. CPU_FREQ_BOOST is enabled.

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Table 25. Typical and maximum current consumption in Run mode,

code with data processing running from Flash memory, cache OFF(1)
Typ
Typ
frcc_c_ck LDO
Symbol Parameter Conditions SMPS Unit
(MHz) regulator
ON
ON

550 99 59.5
VOS0(2)
520 95 56
520 95 56
VOS0
400 76.5 47
All peripherals
400 66.5 38
disabled VOS1
300 51.5 30
300 47.5 26
VOS2
280 43.5 24

Supply current VOS3 170 24.5 13

IDD mA
in Run mode 550 170 100
VOS0(2)
520 165 95.5
520 165 95.5
VOS0
400 130 77.5
All peripherals
400 115 62
enabled VOS1
300 87 47.5
300 79 41.5
VOS2
280 73.5 38
VOS3 170 41 20.5
1. Data are in DTCM for best computation performance, the cache has no influence on consumption in this
case.
2. CPU_FREQ_BOOST is enabled.

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Table 26. Typical consumption in Run mode and corresponding performance

versus code position
Conditions Typ
Typ SMPS
frcc_c_c k LDO LDO IDD/
Symbol Parameter Coremark SMPS Unit IDD/ Unit
(MHz) regulator Coremark
Peripheral Code ON Coremark
ON

ITCM 550 2777 145 81 52.2 29.2

FLASH 550 2777 145 83.5 52.2 30.1

All
peripherals AXI
550 2777 145 83.5 52.2 30.1
disabled, SRAM
cache ON
SRAM 1 550 2777 150 86 54.0 31.0
Supply µA/
IDD current in SRAM 4 550 2777 145 83.5 mA 52.2 30.1 Core-
Run mode mark
FLASH 550 923 99 59.5 107.3 64.5
All AXI
peripherals SRAM 550 1271 105 60.5 82.6 47.6
disabled
cache OFF SRAM 1 550 790 96.5 54.5 122.2 69.0

SRAM 4 550 723 89.5 50.5 123.8 69.8

Table 27. Typical current consumption in Autonomous mode

Typ
frcc_c_c k Typ
Symbol Parameter Conditions LDO Unit
(MHz) SMPS ON
regulator ON

Run, D1Stop,
VOS3 64 3.6 2.2
D2Stop
Supply current in
IDD Run, mA
Autonous mode
D1Standby, VOS3 64 2.6 1.6
D2Standby

Table 28. Typical and maximum current consumption in Sleep mode

Max
Typ Max LDO regulator ON(1)(2) SMPS
Typ
frcc_c_ck LDO ON(3)
Symbol Parameter Conditions SMPS Unit
(MHz) regulator
ON
ON TJ = TJ = TJ = TJ = TJ =
25 °C 85 °C 105 °C 125 °C 140 °C

VOS0 550 36 20.5 - - - - -

(4)
520 33.5 19.5 60 170 240 - -

520 33.5 19.5 60 170 240 - -

VOS0
400 27 16 52 160 230 - -
Supply All
IDD(Sleep) current in peripherals 400 22.5 12.5 39 110 170 240 140 mA
Sleep mode disabled VOS1
300 18.5 10.5 34 110 160 240 140

300 16.5 8.75 28 85 130 190 110

VOS2
170 9.7 5.2 21 78 120 190 110

VOS3 170 8.5 4.35 17 61 96 150 74

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1. Guaranteed by characterization results.

2. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption.
3. The parameter values given in the above table for the SMPS regulator are extrapolated from the LDO consumption and
typical SMPS efficiency factors.
4. CPU_FREQ_BOOST is enabled.

Table 29. Typical and maximum current consumption in System Stop mode
Max
Typ Max LDO regulator ON(1)(2) SMPS
Typ
LDO ON(3)
Symbol Parameter Conditions SMPS Unit
regulator
ON(3)
ON TJ = TJ = TJ = TJ = TJ =
25 °C 85 °C 105 °C 125 °C 140 °C

SVOS5 0.52 0.2 3.7 26.0 44.0 72.0 50.0

Flash memory in
SVOS4 0.81 0.34 6.1 39.0 64.0 110.0 70.0
low-power mode
D1, D2 and
D3 domains SVOS3 1.15 0.51 8.6 51.0 83.0 130.0 100.0
in DStop SVOS5 0.535 0.2 3.7 26.0 44.0 72.0 50.0
mode Flash memory in
normal mode, SVOS4 0.96 0.4 6.2 39.0 64.0 110.0 75.0
IWDG OFF
SVOS3 1.45 0.65 8.8 51.0 83.0 130.0 100.0
SVOS5 0.48 0.19 3.3 23.0 39.0 63.0 43.0
Flash memory in
D1 and D3 low-power mode, SVOS4 0.73 0.31 5.4 34.0 56.0 88.0 58.0
domains in IWDG OFF
DStop mode, SVOS3 1 0.46 7.7 45.0 72.0 120.0 71.0
D2 domain in SVOS5 0.46 0.18 3.3 23.0 39.0 63.0 43.0
IDD(Stop) DStandby Flash memory in mA
mode normal mode, SVOS4 0.9 0.38 5.6 34.0 56.0 89.0 58.0
IWDG OFF
SVOS3 1.17 0.52 7.8 45.0 72.0 120.0 71.0
D1 domain in SVOS5 0.15 0.069 0.8 5.4 9.2 16.0 9.8
DStandby
mode, D2 SVOS4 0.21 0.098 1.3 7.9 14.0 22.0 14.0
and D3
domains in SVOS3 0.275 0.15 1.8 11.0 18.0 28.0 17.0
DStop mode Flash memory in
low-power mode,
D1 and D2 IWDG OFF SVOS5 0.095 0.055 0.3 2.1 3.6 5.9 3.8
domains in
DStandby SVOS4 0.12 0.064 0.5 3.2 5.2 8.3 5.1
mode, D3
domain in SVOS3 0.15 0.084 0.8 4.2 6.8 11.0 6.3
DStop mode

1. Guaranteed by characterization results.

2. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption.
3. The parameter values given in the above table for the SMPS regulator are extrapolated from the LDO consumption and
typical SMPS efficiency factors.

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Table 30. Typical and maximum current consumption in Standby mode

Max at
Max at 3.6 V with LDO 3.6 V with
Conditions Typ(1)
regulator ON(2) SMPS
ON(3)
Symbol Parameter Unit
RTC TJ = TJ = TJ = TJ =
Backup 1.65
and 2.4 V 3V 3.3 V 25 ° 85 ° 105 ° 125 ° TJ = 140 °C
SRAM V
LSE(4) C C C C

Supply OFF OFF 2.2 2.35 2.5 2.8 - - - - -

current in ON OFF 3.5 3.7 4 4.3 - - - - -
IDD
Standby µA
(Standby) mode, OFF ON 2.2 2.4 2.85 3.25 4.5 15 30 64 96
IWDG OFF
ON ON 3.5 3.8 4.35 4.75 8.3 39 75 140 180

1. These values are given for PDR OFF. When the PDR is ON, the typical current consumption is increased (refer to Table 19:
Reset and power control block characteristics.
2. Guaranteed by characterization results.
3. The parameter values given in the above table for the SMPS regulator are extrapolated from the LDO consumption and
typical SMPS efficiency factors.
4. The LSE is in Low-drive mode.

Table 31. Typical and maximum current consumption in VBAT mode

Max at
3.6 V
Max at 3.6 V with LDO
Conditions Typ with
regulator ON(1)(2)
SMPS
Sym- Para-
ON(1)(2) Unit
bol meter
Back- RTC TJ = TJ = TJ =
TJ = TJ =
up and 1.2 V 2V 3V 3.3 V 85 ° 105 125
25 °C 140 °C
SRAM LSE(3) C °C °C

OFF OFF 0.008 0.01 0.025 0.05 0.3 3.1 7.4 18 34

Supply
IDD current ON OFF 1.5 1.7 1.9 1.9 4 28 53 91 110
µA
(VBAT) in VBAT OFF ON 0.4 0.5 0.75 0.8 - - - - -
mode
ON ON 1.8 2.1 2.8 3.2 - - - - -
1. Guaranteed by characterization results.
2. The LDO regulator is used before switching to VBAT mode.
3. The LSE is in Low-drive mode.

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Typical SMPS efficiency versus load current and temperature

Figure 17. Typical SMPS efficiency (%) vs load current (A) in Run mode at TJ = 30 °C
°C
100

90

80

70

VDDSMPS =
3.3V, VOS0
60 VDDSMPS =
1.8V, VOS1
VDDSMPS =
50 3.3V, VOS1
VDDSMPS =
1.8V, VOS2
VDDSMPS =
40 3.3V, VOS2
VDDSMPS =
1.8V, VOS3
VDDSMPS =
30 3.3V, VOS3

20

10

0
0.001 0.01 0.1 1
MSv65350V2

Figure 18. Typical SMPS efficiency (%) vs load current (A) in Run mode at TJ = TJmax

100

90

80

70

60
VDDSMPS = 1.8V,
VOS1
50 VDDSMPS =
3.3V,VOS1
VDDSMPS = 1.8V,
VOS2
40 VDDSMPS = 3.3V,
VOS2
VDDSMPS = 1.8V,
30 VOS3

20

10

0
0.001 0.01 0.1 1
MSv65350V1

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Figure 19. Typical SMPS efficiency (%) vs load current (A) in Stop and
DStop modes at TJ = 30 °C

100

90

80

70

VDDSMPS =
60
1.8V, SVOS5
VDDSMPS =
3.3V, SVOS5
50
VDDSMPS =
1.8V, SVOS4
VDDSMPS =
40 3.3V, SVOS4
VDDSMPS =
1.8V, SVOS3
30
VDDSMPS =
3.3V, SVOS3

20

10

current (A)
0
0.00001 0.0001 0.001 0.01 0.1
MSv65352V1

Figure 20. Typical SMPS efficiency (%) vs load current (A) in low-power mode at
TJ = TJmax

100

90

80

70

VDDSMPS =
60
1.8V, SVOS5
VDDSMPS =
3.3V, SVOS5
50
VDDSMPS =
1.8V, SVOS4
VDDSMPS =
40 3.3V, SVOS4
VDDSMPS =
1.8V, SVOS3
30
VDDSMPS =
3.3V, SVOS3

20

10

0
0.00001 0.0001 0.001 0.01 0.1
MSv65353V1

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I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate a current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 54: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
An additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid a current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 32: Peripheral current
consumption in Run mode), the I/Os used by an application also contribute to the current
consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to
supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external)
connected to the pin:

I SW = V DDx × f SW × C L

where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDx is the MCU supply voltage
fSW is the I/O switching frequency
CL is the total capacitance seen by the I/O pin: C = CINT+ CEXT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.

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On-chip peripheral current consumption

The MCU is placed under the following conditions:
• At startup, all I/O pins are in analog input configuration.
• All peripherals are disabled unless otherwise mentioned.
• The I/O compensation cell is enabled.
• frcc_c_ck is the CPU clock. fPCLK = frcc_c_ck/4, and fHCLK = frcc_c_ck/2.
The given value is calculated by measuring the difference of current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
– frcc_c_ck = 550 MHz (Scale 0), frcc_c_ck = 400 MHz (Scale 1), frcc_c_ck = 300 MHz
(Scale 2), frcc_c_ck = 170 MHz (Scale 3)
• The ambient operating temperature is 25 °C and VDD=3.3 V
• The LDO regulator supplies VCORE.

Table 32. Peripheral current consumption in Run mode

IDD(Typ)
Peripheral Unit
VOS0 VOS1 VOS2 VOS3

MDMA 3.70 3.10 2.90 2.60

DMA2D 2.70 2.30 2.10 1.90
Flash memory 15.20 14.00 12.00 10.90
FMC registers 0.90 0.90 0.80 0.70
FMC kernel 7.00 6.10 5.60 5.40
OCTOSPI1 registers 1.40 1.30 0.50 0.40
OCTOSPI1 kernel 3.10 1.20 0.50 0.20
AHB3 µA/MHz
SDMMC1 registers 8.70 7.60 6.90 6.10
SDMMC1 kernel 2.10 1.80 1.40 1.20
OCTOSPI2 registers 1.40 1.30 0.90 0.60
OCTOSPI2 kernel 2.50 1.50 1.40 0.50
OTFDEC1 0.80 0.70 0.10 0.10
OTFDEC2 0.80 0.70 0.10 0.10
AXI SRAM 8.50 7.50 6.90 6.00

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Table 32. Peripheral current consumption in Run mode (continued)

IDD(Typ)
Peripheral Unit
VOS0 VOS1 VOS2 VOS3

DMA1 0.70 0.60 0.50 0.40

DMA2 1.00 0.80 0.70 0.70
DMAMUX1 0.10 0.10 0.10 0.10
ADC1/2 registers 4.50 4.00 3.60 2.30
AHB1 ADC1/2 kernel 0.90 0.80 0.60 0.40 µA/MHz
USB1 registers 20.80 17.50 16.50 14.80
USB1 kernel 1.20 0.90 0.90 0.90
USB1 ULPI kernel 31.00 30.00 29.50 27.00
Ethernet 17.30 14.40 13.70 12.30
DCMI 4.80 4.00 3.80 3.40
CRYP 1.40 1.20 1.10 0.80
HASH1 1.70 1.40 1.30 1.00
HSEM 0.60 0.60 0.10 0.10
RNG1 registers 1.20 1.00 0.90 0.70
RNG1 kernel 15.00 13.60 10.00 9.00
AHB2 SDMMC2 registers 15.00 12.20 11.70 10.40 µA/MHz
SDMMC2 kernel 2.10 1.80 1.40 1.20
BDMA 6.50 5.90 4.80 4.30
SRAM1 2.40 2.00 1.80 1.60
SRAM2 2.70 2.30 2.00 1.80
CORDIC 0.80 0.60 0.50 0.50
FMAC 2.40 2.10 1.90 1.60

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Table 32. Peripheral current consumption in Run mode (continued)

IDD(Typ)
Peripheral Unit
VOS0 VOS1 VOS2 VOS3

GPIOA 0.10 0.10 0.10 0.10

GPIOB 0.90 0.80 0.10 0.10
GPIOC 0.50 0.10 0.10 0.10
GPIOD 0.90 0.80 0.10 0.10
GPIOE 0.90 0.80 0.10 0.10
GPIOF 0.30 0.10 0.10 0.10
GPIOG 0.90 0.80 0.30 0.20
GPIOH 0.10 0.10 0.10 0.10
AHB4
GPIOJ 0.90 0.80 0.30 0.20
µA/MHz
GPIOK 0.80 0.80 0.10 0.10
HSEM 0.60 0.60 0.10 0.10
BDMA 6.50 5.90 4.80 4.30
CRC 0.90 0.30 0.30 0.30
ADC3 registers 2.10 1.40 1.30 1.20
ADC3 kernel 0.40 0.30 0.30 0.20
Backup SRAM 1.80 1.00 1.00 0.80
LTDC 9.00 7.90 7.70 6.40
APB3
WWDG1 0.60 0.50 0.50 0.50

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Table 32. Peripheral current consumption in Run mode (continued)

IDD(Typ)
Peripheral Unit
VOS0 VOS1 VOS2 VOS3

TIM2 4.50 4.40 3.30 3.00

TIM3 3.80 3.20 2.90 2.70
TIM4 3.60 3.10 2.60 2.50
TIM5 4.10 3.40 3.10 2.90
TIM6 1.50 1.10 1.00 1.00
TIM7 1.40 1.10 0.90 0.90
TIM12 2.30 1.80 1.60 1.60
TIM13 1.90 1.40 1.30 1.20
TIM14 1.60 1.20 1.10 1.10
TIM23 4.60 3.90 3.60 3.40
TIM24 4.40 3.80 3.50 3.30
LPTIM1 registers 3.50 2.90 2.70 2.60
LPTIM1 kernel 2.60 2.30 2.00 1.80
SPI2 registers 2.10 1.60 0.90 0.80
SPI2 kernel 1.50 1.20 1.10 1.00
SPI3 registers 2.40 2.00 1.90 1.80
APB1 SPDIFRX registers 0.60 0.50 0.50 0.50 µA/MHz
SPDIFRX kernel 3.50 2.80 2.40 2.20
USART2 registers 6.60 5.70 5.20 4.90
USART2 kernel 4.80 4.80 4.60 3.80
USART3 registers 5.90 5.40 4.60 4.30
USART3 kernel 4.00 3.40 3.00 2.90
UART4 registers 5.60 4.80 3.50 3.10
UART4 kernel 3.80 3.20 3.00 2.40
UART5 registers 5.60 4.60 4.40 4.00
UART5 kernel 3.90 3.40 3.30 3.20
UART7 registers 5.40 4.60 4.20 3.90
UART7 kernel 3.80 3.30 3.00 3.00
UART8 registers 5.60 4.10 3.50 3.40
UART8 kernel 3.60 3.20 3.20 3.10
I2C1 registers 0.90 0.60 0.60 0.50
I2C1 kernel 2.30 2.00 1.80 1.60
I2C2 registers 1.00 0.70 0.60 0.60

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Table 32. Peripheral current consumption in Run mode (continued)

IDD(Typ)
Peripheral Unit
VOS0 VOS1 VOS2 VOS3

I2C2 kernel 2.30 1.90 1.70 1.20

I2C3 registers 0.90 0.60 0.50 0.50
I2C3 kernel 2.30 2.00 1.00 1.00
I2C5 registers 0.90 0.60 0.50 0.50
I2C5 kernel 2.20 2.10 1.90 1.80
CEC registers 0.60 0.30 0.20 0.20
CEC kernel 0.10 0.10 0.10 0.10
APB1 µA/MHz
DAC1 1.60 1.30 1.10 1.10
FDCAN1/2/3 registers 24.10 20.90 18.20 17.40
FDCAN1/2/3 kernel 9.90 9.90 9.00 8.00
CRS 4.90 3.90 3.50 3.20
SWPMI registers 1.10 0.80 0.80 0.80
SWPMI kernel 1.50 1.10 1.00 1.00
OPAMP 0.50 0.40 0.30 0.20

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Table 32. Peripheral current consumption in Run mode (continued)

IDD(Typ)
Peripheral Unit
VOS0 VOS1 VOS2 VOS3

TIM1 5.30 4.40 4.20 3.80

TIM8 5.60 5.40 5.20 3.90
USART1 registers 1.80 1.60 1.40 1.10
USART1 kernel 3.00 2.90 2.80 2.70
USART6 registers 1.90 1.70 1.50 1.20
USART6 kernel 4.50 4.00 3.60 3.10
UART9 registers 1.70 1.70 1.60 1.10
UART9 kernel 3.80 3.30 2.90 2.90
USART10 registers 1.80 1.70 1.40 1.10
USART10 kernel 3.80 3.30 2.90 2.90
SPI1 registers 1.90 1.80 1.40 1.20
SPI1 kernel 1.50 1.20 1.10 1.00
APB2 µA/MHz
SPI4 registers 1.80 1.60 1.40 1.10
SPI4 kernel 1.50 1.20 1.10 1.00
SPI5 registers 1.60 1.60 1.40 1.10
SPI5 kernel 1.50 1.20 1.10 1.00
TIM15 2.80 2.50 2.30 1.90
TIM16 2.00 1.90 1.60 1.30
TIM17 2.10 2.00 1.70 1.40
SAI1 registers 1.40 1.40 1.20 0.90
SAI1 kernel 0.80 0.70 0.70 0.70
DFSDM1 registers 5.60 5.40 5.30 4.00
DFSDM1 kernel 0.30 0.20 0.20 0.10
SYSCFG 1.20 1.10 1.10 1.10

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Table 32. Peripheral current consumption in Run mode (continued)

IDD(Typ)
Peripheral Unit
VOS0 VOS1 VOS2 VOS3

LPUART1 registers 1.80 0.90 0.80 0.60

LPUART1 kernel 2.40 2.30 2.00 1.90
SPI6 registers 2.60 2.30 2.10 1.80
SPI6 kernel 1.20 1.10 1.00 0.90
I2C4 registers 0.70 0.70 0.60 0.40
I2C4 kernel 2.00 1.70 1.70 1.40
LPTIM2 registers 1.50 0.70 0.50 0.30
LPTIM2 kernel 2.50 2.10 2.00 1.90
LPTIM3 registers 2.90 2.60 2.30 1.90
LPTIM3 kernel 2.40 2.00 1.90 1.70
APB4 LPTIM4 registers 2.60 2.30 2.10 1.80 µA/MHz
LPTIM4 kernel 2.10 1.80 1.70 1.60
LPTIM5 registers 2.60 2.30 2.00 1.70
LPTIM5 kernel 2.10 1.80 1.60 1.50
COMP1/2 0.70 0.30 0.20 0.10
VREF 0.10 0.10 0.10 0.10
RTC 0.10 0.10 0.10 0.10
WWDG1 0.60 0.50 0.50 0.50
SAI4 registers 2.40 2.20 2.10 1.70
SAI4 kernel 0.90 0.90 0.90 0.70
DTS 2.90 2.60 2.30 2.00

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6.3.9 Wakeup time from low-power modes

The wakeup times given in Table 33 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
• For Stop or Sleep modes: the wakeup event is WFE.
• WKUP (PC1) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and VDD=3.3 V.

Table 33. Low-power mode wakeup timings

Max(1)
Symbol Parameter Conditions Typ(1) (2)
Unit

CPU
tWUSLEEP(3) Wakeup from Sleep - 14.00 15.00 clock
cycles
SVOS3, HSI, Flash memory in Normal mode 4.6 6.2
SVOS3, HSI, Flash memory in low-power mode 12.4 17.4
SVOS4, HSI, Flash memory in Normal mode 15.5 21.1
SVOS4, HSI, Flash memory in low-power mode 23.3 31.8
SVOS5, HSI, Flash memory in Normal mode 39.1 52.6

Wakeup from Stop SVOS5, HSI, Flash memory in low-power mode 39.1 52.7
tWUSTOP(3)
mode SVOS3, CSI, Flash memory in Normal mode 30.0 41.6
SVOS3, CSI, Flash memory in low-power mode 40.6 55.0 µs

SVOS4, CSI, Flash memory in Normal mode 41.0 55.4

SVOS4, CSI, Flash memory in low-power mode 51.5 68.8
SVOS5, CSI, Flash memory in Normal mode 67.3 89.5
SVOS5, CSI, Flash memory in low-power mode 67.2 89.5

Wakeup from
tWUSTDBY(3) - 400.0 504.3
Standby mode

1. Guaranteed by characterization results.

2. The maximum values have been measured at -40 °C, in worst conditions.
3. The wakeup times are measured from the wakeup event to the point in which the application code reads the first

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6.3.10 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O.
The external clock signal has to respect the Table 54: I/O static characteristics. However,
the recommended clock input waveform is shown in Figure 21.

Table 34. High-speed external user clock characteristics(1)

Symbol Parameter Min Typ Max Unit

fHSE_ext User external clock source frequency 4 25 50 MHz

Digital OSC_IN input high-level
VHSEH 0.7 VDD - VDD
voltage V
VHSEL Digital OSC_IN input low-level voltage VSS - 0.3 VDD
tW(HSE) OSC_IN high or low time 7 - - ns
1. Guaranteed by design.

Figure 21. High-speed external clock source AC timing diagram

VHSEH
90 %
10 %
VHSEL
tr(HSE) tf(HSE) tW(HSE) tW(HSE) t

THSE

External fHSE_ext
IL
clock source OSC_IN
STM32

ai17528b

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Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 54: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 22.

Table 35. Low-speed external user clock characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

User external clock source

fLSE_ext - - 32.768 1000 kHz
frequency
OSC32_IN input pin high-level
VLSEH - 0.7 VDD - VDD
voltage
V
OSC32_IN input pin low-level
VLSEL - VSS - 0.3 VDD
voltage
tw(LSEH)
OSC32_IN high or low time - 250 - - ns
tw(LSEL)
1. Guaranteed by design.

Figure 22. Low-speed external clock source AC timing diagram

VLSEH
90%
10%
VLSEL
tr(LSE) tf(LSE) tW(LSE) tW(LSE) t

TLSE

External fLSE_ext
OSC32_IN IL
clock source
STM32

ai17529b

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High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 50 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 36. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).

Table 36. 4-50 MHz HSE oscillator characteristics(1)

Operating
Symbol Parameter Min Typ Max Unit
conditions(2)

F Oscillator frequency - 4 - 50 MHz

RF Feedback resistor - - 200 - kΩ
During startup(3) - - 4
VDD=3 V, Rm=30 Ω
- 0.35 -
CL=10 pF at 4 MHz
VDD=3 V, Rm=30 Ω
- 0.40 -
CL=10 pF at 8 MHz
HSE current
IDD(HSE) VDD=3 V, Rm=30 Ω mA
consumption - 0.45 -
CL=10 pF at 16 MHz
VDD=3 V, Rm=30 Ω
- 0.65 -
CL=10 pF at 32 MHz
VDD=3 V, Rm=30 Ω
- 0.95 -
CL=10 pF at 48 MHz
Maximum critical crystal
Gmcritmax Startup - - 1.5 mA/V
gm
tSU(4) Start-up time VDD is stabilized - 2 - ms
1. Guaranteed by design.
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer.

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typical), designed for high-frequency applications, and selected to
match the requirements of the crystal or resonator (see Figure 23). CL1 and CL2 are usually
the same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. The PCB and MCU pin capacitance must be included
(10 pF can be used as a rough estimate of the combined pin and board capacitance) when
sizing CL1 and CL2.
Note: For information on selecting the crystal, refer to application note AN2867 “Oscillator design
guide for ST microcontrollers” available from the ST website www.st.com.

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Figure 23. Typical application with an 8 MHz crystal

Resonator with
integrated capacitors
CL1
OSC_IN fHSE
Bias
8 MHz RF controlled
resonator
gain

REXT(1) OSC_OU T STM32

CL2
ai17530b

1. REXT value depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 37. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).

Table 37. Low-speed external user clock characteristics(1)

Symbol Parameter Operating conditions(2) Min Typ Max Unit

F Oscillator frequency - - 32.768 - kHz

LSEDRV[1:0] = 00,
- 290 -
Low drive capability
LSEDRV[1:0] = 01,
- 390 -
LSE current Medium Low drive capability
IDD nA
consumption LSEDRV[1:0] = 10,
- 550 -
Medium high drive capability
LSEDRV[1:0] = 11,
- 900 -
High drive capability
LSEDRV[1:0] = 00,
- - 0.5
Low drive capability
LSEDRV[1:0] = 01,
- - 0.75
Maximum critical crystal Medium Low drive capability
Gmcritmax µA/V
gm LSEDRV[1:0] = 10,
- - 1.7
Medium high drive capability
LSEDRV[1:0] = 11,
- - 2.7
High drive capability
tSU(3) Startup time VDD is stabilized - 2 - s
1. Guaranteed by design.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
3. tSU is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768k Hz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

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Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 24. Typical application with a 32.768 kHz crystal

Resonator with
integrated capacitors CL1
OSC32_IN fHSE

Bias
32.768 kHz
RF controlled
resonator
gain

OSC32_OUT
STM32
CL2
ai17531c

1. An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.

6.3.11 Internal clock source characteristics

The parameters given in Table 38 to Table 40 are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 12: General
operating conditions.

48 MHz high-speed internal RC oscillator (HSI48)

Table 38. HSI48 oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

VDD=3.3 V,
fHSI48 HSI48 frequency 47.5(1) 48 48.5(1) MHz
TJ=30 °C
TRIM(2) USER trimming step - - 0.175 0.250 %
USER TRIM
USER TRIMMING coverage ± 32 steps ±4.70 ±5.6 - %
COVERAGE(3)
DuCy(HSI48)(2) Duty Cycle - 45 - 55 %
Accuracy of the HSI48 oscillator over
ACCHSI48_REL(3)(4) TJ=-40 to 125 °C –4.5 - 3.5 %
temperature (factory calibrated)

HSI48 oscillator frequency drift with VDD=3 to 3.6 V - 0.025 0.05

∆VDD(HSI48)(2)(5) %
VDD(6) (the reference is 3.3 V) VDD=1.62 V to 3.6 V - 0.05 0.1
tsu(HSI48)(2) HSI48 oscillator start-up time - - 2.1 4.0 µs
IDD(HSI48)(2) HSI48 oscillator power consumption - - 350 400 µA
Next transition jitter
NT jitter(2) - - ± 0.15 - ns
Accumulated jitter on 28 cycles(7)
Paired transition jitter
PT jitter(2) - - ± 0.25 - ns
Accumulated jitter on 56 cycles(7)
1. Guaranteed by test in production.
2. Guaranteed by design.
3. Guaranteed by characterization results.
4. ∆fHSI = ACCHSI48_REL + ∆VDD.

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5. ∆fHSI = ACCHSI48_REL + ∆VDD.

6. These values are obtained by using the formula: (Freq(3.6 V) - Freq(3.0 V)) / Freq(3.0 V) or (Freq(3.6 V) - Freq(1.62 V)) /
Freq(1.62 V).
7. Jitter measurements are performed without clock source activated in parallel.

64 MHz high-speed internal RC oscillator (HSI)

Table 39. HSI oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fHSI HSI frequency VDD=3.3 V, TJ=30 °C 63.7(2) 64 64.3(2) MHz

Trimming is not a multiple
- 0.24 0.32
of 32
Trimming is 128, 256 and
−5.2 −1.8 -
384

TRIM HSI user trimming step Trimming is 64, 192, 320 %

−1.4 −0.8 -
and 448
Other trimming are a
multiple of 32 (not
−0.6 −0.25 -
including multiple of 64
and 128)
DuCy(HSI) Duty cycle - 45 - 55 %
HSI oscillator frequency drift over
ΔVDD (HSI) VDD=1.62 to 3.6 V −0.12 - 0.03 %
VDD (the reference is 3.3 V)
HSI oscillator frequency drift over TJ=-20 to 105 °C −1(3) - 1(3)
ΔTEMP(HSI) temperature (the reference is %
64 MHz) TJ=−40 to TJmax °C −2(3) - 1(3)

tsu(HSI) HSI oscillator start-up time - - 1.4 2

at 1% of target frequency - 4 8 µs
tstab(HSI) HSI oscillator stabilization time
at 5% of target frequency - - 4
IDD(HSI) HSI oscillator power consumption - - 300 400 µA
1. Guaranteed by design unless otherwise specified.
2. Guaranteed by test in production.
3. Guaranteed by characterization results.

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4 MHz low-power internal RC oscillator (CSI)

Table 40. CSI oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fCSI CSI frequency VDD=3.3 V, TJ=30 °C 3.96(2) 4 4.04(2) MHz

Trimming is not a
- 0.40 0.75
multiple of 16
Trimming is a multiple
−4.75 −2.75 0.75
of 32
TRIM CSI trimming step %
Other trimming values
not multiple of 16
−0.43 0.00 0.75
(excluding multiple of
32)
DuCy(CSI) Duty cycle - 45 - 55 %

CSI oscillator frequency drift over TJ = 0 to 85 °C −3.7(3) - 4.5(3)

∆TEMP (CSI) %
temperature TJ = −40 to 125 °C −11(3) - 7.5(3)
CSI oscillator frequency drift over
∆VDD (CSI) VDD = 1.62 to 3.6 V −0.06 - 0.06 %
VDD
tsu(CSI) CSI oscillator startup time - - 1 2 µs
CSI oscillator stabilization time
tstab(CSI) - - - 4 cycle
(to reach ± 3% of fCSI)
IDD(CSI) CSI oscillator power consumption - - 23 30 µA
1. Guaranteed by design, unless otherwise specified.
2. Guaranteed by test in production.
3. Guaranteed by characterization results.

Low-speed internal (LSI) RC oscillator

Table 41. LSI oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

VDD = 3.3 V, TJ = 25 °C 31.4(1) 32 32.6(1)

TJ = –40 to 110 °C,
29.76(2) - 33.6(2)
fLSI LSI frequency VDD = 1.62 to 3.6 V kHz
TJ = –40 to 125 °C,
29.4(2) - 33.6(2)
VDD = 1.62 to 3.6 V
tsu(LSI)(3) LSI oscillator startup time - - 80 130
LSI oscillator stabilization time µs
tstab(LSI)(3) - - 120 170
(5% of final value)
IDD(LSI)(3) LSI oscillator power consumption - - 130 280 nA
1. Guaranteed by test in production.
2. Guaranteed by characterization results.
3. Guaranteed by design.

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6.3.12 PLL characteristics

The parameters given in Table 42, Table 45 are derived from tests performed under
temperature and VDD supply voltage conditions summarized in Table 12: General operating
conditions.

Table 42. PLL1 characteristics (wide VCO frequency range)(1)

Symbol Parameter Conditions Min Typ Max Unit

PLL input clock - 2 - 16 MHz

fPLL_IN
PLL input clock duty cycle - 10 - 90 %
(2)
VOS0 1.5 - 550
VOS1 1.5 - 400(2)
fPLL_P_OUT PLL multiplier output clock P
VOS2 1.5 - 300(2) MHz
VOS3 1.5 - 170(2)
fVCO_OUT PLL VCO output - 192 - 836(3)
Normal mode 15 50 150(3)
tLOCK PLL lock time Sigma-delta mode (CKIN ≥ µs
25 65 170
8 MHz)
fVCO_OUT
- 51 -
= 192 MHz
fVCO_OUT
- 19 -
= 400 MHz
Cycle-to-cycle jitter(4)
fVCO_OUT
- 10 -
= 560 MHz
fPLL_OUT = fVCO_OUT
- 9 - ps
fVCO_OUT/100 = 800 MHz
fVCO_OUT
- 38 -
= 192 MHz
fVCO_OUT
Period jitter - 8 -
= 560 MHz
fVCO_OUT
Jitter - 7 -
= 800 MHz
fVCO_OUT
- 0.15 -
= 192 MHz
Normal mode fVCO_OUT
- 0.14 -
(CKIN = 2 MHz) = 400 MHz
fVCO_OUT
- 0.16 -
= 832 MHz
Long term jitter %
fVCO_OUT
- 0.17 -
= 192 MHz
Sigma-delta
fVCO_OUT
mode (CKIN = - 0.08 -
= 500 MHz
16 MHz)
fVCO_OUT
- 0.06 -
= 836 MHz

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Table 42. PLL1 characteristics (wide VCO frequency range)(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

fVCO_OUT = VDDA 530 557 670

560 MHz VCORE 1190 1285 6300
IDD(PLL) PLL power consumption µA
fVCO_OUT = VDDA 260 286 513
192 MHz VCORE 309 377 5700
1. Guaranteed by design unless otherwise specified.
2. This value must be limited to the maximum frequency due to the product limitation.
3. Guaranteed by characterization results.
4. Integer mode only.

Table 43. PLL1 characteristics (medium VCO frequency range)(1)

Symbol Parameter Conditions Min Typ Max Unit

PLL input clock - 1 - 2 MHz

fPLL_IN
PLL input clock duty cycle - 10 - 90 %
VOS0 1.17 - 210
VOS1 1.17 - 210
fPLL_OUT PLL multiplier output clock P, Q, R
VOS2 1.17 - 210 MHz
VOS3 1.17 - 200
fVCO_OUT PLL VCO output - 150 - 420
Normal mode - 60(2) 100(2)
tLOCK PLL lock time µs
Sigma-delta mode forbidden
fVCO_OUT =
- 145 -
150 MHz
fVCO_OUT =
- 91 -
300 MHz
Cycle-to-cycle jitter(3) - ±ps
fVCO_OUT =
- 64 -
400 MHz
fVCO_OUT =
Jitter - 63 -
420 MHz
fVCO_OUT =
- 55 -
fPLL_OUT = 150 MHz
Period jitter ±-ps
50 MHz fVCO_OUT =
- 30 -
400 MHz
fVCO_OUT =
Long term jitter Normal mode - ±0.3 - %
400 MHz

fVCO_OUT = VDD - 440 1150

420 MHz VCORE - 530 -
I(PLL) PLL power consumption on VDD µA
fVCO_OUT = VDD - 180 500
150 MHz VCORE - 200 -

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1. Guaranteed by design unless otherwise specified.

2. Guaranteed by characterization results.
3. Integer mode only.

Table 44. PLL2 and PLL3 characteristics (wide VCO frequency range)(1)
Symbol Parameter Conditions Min Typ Max Unit

PLL input clock - 2 - 16 MHz

fPLL_IN
PLL input clock duty cycle - 10 - 90 %
VOS0 1.5 - 550(2)

PLL multiplier output clock P, VOS1 1.5 - 400(2)

fPLL_OUT
Q, R VOS2 1.5 - 300(2) MHz
VOS3 1.5 - 170(2)
fVCO_OUT PLL VCO output - 192 - 960(3)
Normal mode - 50 150(3)
tLOCK PLL lock time Sigma-delta mode (fPLL_IN µs
- 58 166(3)
≥ 8 MHz)
fVCO_OUT = 192 MHz - 134 -
fVCO_OUT = 200 MHz - 134 -
Cycle-to-cycle jitter(4) ±ps
fVCO_OUT = 400 MHz - 76 -
fVCO_OUT = 800 MHz - 39 -
Normal
mode fVCO_OUT =
- ±0.2 -
(fPLL_IN = 560 MHz
2 MHz)
Normal
Jitter mode fVCO_OUT =
- ±0.8 -
(fPLL_IN = 560 MHz
16 MHz)
Long term jitter %
Sigma-delta
mode fVCO_OUT =
- ±0.2 -
(fPLL_IN = 560 MHz
2 MHz)
Sigma-delta
mode fVCO_OUT =
- ±0.8 -
(fPLL_IN = 560 MHz
16 MHz)

fVCO_OUT = VDD - 590 1500

836 MHz VCORE - 720 -
IDD(PLL)(3) PLL power consumption µA
fVCO_OUT = VDD - 180 600
192 MHz VCORE - 280 -
1. Guaranteed by design unless otherwise specified.
2. This value must be limited to the maximum frequency due to the product limitation.

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3. Guaranteed by characterization results.

4. Integer mode only.

Table 45. PLL2 and PLL3 characteristics (medium VCO frequency range)(1)
Symbol Parameter Conditions Min Typ Max Unit

PLL input clock - 1 - 2 MHz

fPLL_IN
PLL input clock duty cycle - 10 - 90 %
VOS0 1.17 - 210 MHz

PLL multiplier output clock VOS1 1.17 - 210 -

fPLL_OUT
P, Q, R VOS2 1.17 - 210 -
VOS3 1.17 - 200 -
fVCO_OUT PLL VCO output - 150 - 420 -
Normal mode - 60 100(2)
tLOCK PLL lock time µs
Sigma-delta mode forbidden
fVCO_OUT = 150 MHz - 145 -
fVCO_OUT = 200 MHz - 91 -
Cycle-to-cycle jitter(3) ±ps
fVCO_OUT = 400 MHz - 64 -
fVCO_OUT = 420 MHz - 63 -
Jitter
fPLL_OUT = fVCO_OUT =
- 55 -
Period jitter 50 MHz 150 MHz ±ps
fVCO_OUT = 400 MHz - 30 -
fVCO_OUT =
Long term jitter Normal mode - ±0.3 - %
400 MHz

fVCO_OUT = VDD - 440 1150

420 MHz VCORE - 530 -
PLL power consumption on
IDD(PLL) µA
VDD VDD - 180 500
fVCO_OUT =
150 MHz VCORE - 200 -
1. Guaranteed by design unless otherwise specified.
2. Guaranteed by characterization results.
3. Integer mode only.

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6.3.13 Memory characteristics

Flash memory
The characteristics are given at TJ = –40 to 125 °C unless otherwise specified.
The devices are shipped to customers with the Flash memory erased.

Table 46. Flash memory characteristics

Symbol Parameter Conditions Min Typ Max Unit

Write / Erase 8-bit mode - 6.5 -

Write / Erase 16-bit mode - 11.5 -
IDD Supply current mA
Write / Erase 32-bit mode - 20 -
Write / Erase 64-bit mode - 35 -

Table 47. Flash memory programming

Symbol Parameter Conditions Min(1) Typ Max(1) Unit

Program/erase parallelism x 8 - 290 580(2)

Word (266 bits) programming Program/erase parallelism x 16 - 180 360

tprog µs
time Program/erase parallelism x 32 - 130 260
Program/erase parallelism x 64 - 100 200
Program/erase parallelism x 8 - 2 4
tERASE Sector (128 Kbytes) erase time Program/erase parallelism x 16 - 1.8 3.6
Program/erase parallelism x 32 -
Program/erase parallelism x 8 - 3 26 s
Program/erase parallelism x 16 - 8 16
tME Mass erase time (1 Mbyte)
Program/erase parallelism x 32 - 6 12
Program/erase parallelism x 64 - 5 10
Program parallelism x 8
Program parallelism x 16 1.62 - 3.6
Vprog Programming voltage V
Program parallelism x 32
Program parallelism x 64 1.8 - 3.6
1. Guaranteed by characterization results.
2. The maximum programming time is measured after 10K erase operations.

Table 48. Flash memory endurance and data retention

Symbol Parameter Conditions Min(1) Unit

NEND Endurance TJ = –40 to +125 °C 10 kcycles

Data retention 1 kcycle at TA = 85 °C 30
tRET Years
10 kcycles at TA = 55 °C 20

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1. Guaranteed by characterization results.

6.3.14 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 49. They are based on the EMS levels and classes
defined in application note AN1709 “EMC design guide for STM8, STM32 and Legacy
MCUs ”.

Table 49. EMS characteristics

Level/
Symbol Parameter Conditions
Class

VDD = 3.3 V, TA = 25 °C,

Voltage limits to be applied on any I/O pin to induce
VFESD LQFP176, conforming to 3B
a functional disturbance
IEC 61000-4-2
Fast transient voltage burst limits to be applied VDD = 3.3 V, TA = 25 °C,
VFTB through 100 pF on VDD and VSS pins to induce a LQFP176, conforming to 5A
functional disturbance IEC 61000-4-4

As a consequence, it is recommended to add a serial resistor (1 kΏ) located as close as

possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm
on PCB).

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...)

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Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015 “Software
techniques for improving microcontrollers EMC performance”).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.

Table 50. EMI characteristics

Max vs.
Monitored [fHSE/fCPU]
Symbol Parameter Conditions Unit
frequency band
8/550 MHz

0.1 to 30 MHz 14
30 to 130 MHz 20
VDD = 3.6 V, TA = 25 °C, LQFP176 package, dBµV
SEMI Peak level 130 MHz to 1 GHz 27
conforming to IEC61967-2
1 GHz to 2 GHz 17
EMI Level 4 -

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6.3.15 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each
sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC
JS-001 and ANSI/ESDA/JEDEC JS-002 standards.

Table 51. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Packages Class Unit
value(1)

Packages with
1C 1000(2)
Electrostatic discharge TA = 25 °C conforming to SMPS
VESD(HBM)
voltage (human body model) ANSI/ESDA/JEDEC JS-001 Packages without
2 2000
SMPS
V
All LQFP
Electrostatic discharge C1 250
TA = +25 °C conforming to packages
VESD(CDM) voltage (charge device
ANSI/ESDA/JEDEC JS-002 All BGA and
model) C2a 500
WLCSP packages
1. Guaranteed by characterization results.
2. Excluding VFBSMPS,the maximum value is 2000 V.

Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with JESD78 IC latchup standard.

Table 52. Electrical sensitivities

Symbol Parameter Conditions Class

Conforming to JESD78,
LU Static latchup class II level A
TJ = TJMax

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6.3.16 I/O current injection characteristics

As a general rule, a current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3.3 V-capable I/O pins) should be avoided during the normal
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when an abnormal injection accidentally happens, susceptibility
tests are performed on a sample basis during the device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency
deviation).
The following tables are the compilation of the SIC1/SIC2 and functional ESD results.
Negative induced A negative induced leakage current is caused by negative injection and
positive induced leakage current by positive injection.

Table 53. I/O current injection susceptibility(1)

Functional susceptibility
Symbol Description Unit
Negative Positive
injection injection

PA12, PE8 5 0
PC4, PE12, PF15, PH0 0 NA
IINJ PA0, PA0_C, PA1, PA1_C, PC2, PC2_C, PC3, PC3_C, PA4, mA
0 0
PA5, PE7, PG1, PH4, PH5, BOOT0
All other I/Os 5 NA
1. Guaranteed by characterization results.

6.3.17 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 54: I/O static characteristics are
derived from tests performed under the conditions summarized in Table 12: General
operating conditions. All I/Os are CMOS and TTL compliant (except for BOOT0).
Note: For information on GPIO configuration, refer to application note AN4899 “STM32 GPIO
configuration for hardware settings and low-power consumption”, available from the ST
website www.st.com.

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Table 54. I/O static characteristics

Symbol Parameter Condition Min Typ Max Unit

I/O input low level voltage

- - 0.3VDD(1)
except BOOT0
I/O input low level voltage 0.4VDD−0.1
VIL 1.62 V<VDD<3.6 V - - (2) V
except BOOT0
BOOT0 I/O input low level 0.19VDD+0.1
- - (2)
voltage
I/O input high level voltage
0.7VDD(1) - -
except BOOT0
I/O input high level voltage 0.47VDD+
VIH 1.62 V<VDD<3.6 V - - V
except BOOT0 0.25(2)
BOOT0 I/O input high level 0.17VDD+
- -
voltage 0.6(2)
TT_xx, FT_xxx and NRST I/O
- 250 -
VHYS(2) input hysteresis 1.62 V< VDD <3.6 V mV
BOOT0 I/O input hysteresis - 200 -
0< VIN ≤ Max(VDDXXX)(8) - - +/-250
FT_xx Input leakage current(2) Max(VDDXXX) < VIN ≤ 5.5 V
(4)(5)(8) - - 1500

0< VIN ≤ Max(VDDXXX)(8) - - +/- 350

Ilkg(3) FT_u IO Max(VDDXXX) < VIN ≤ 5.5 V nA
(4)(5)(8) - - 5000(6)

TT_xx Input leakage current 0< VIN ≤ Max(VDDXXX) (8) - - +/-250

VPP (BOOT0 alternate 0< VIN ≤ VDD - - 15

function) VDD < VIN ≤ 9 V 35
Weak pull-up equivalent
RPU VIN=VSS 30 40 50
resistor(7)
kΩ
Weak pull-down equivalent (8)
RPD VIN=VDD 30 40 50
resistor(7)
CIO I/O pin capacitance - - 5 - pF
1. Compliant with CMOS requirements.
2. Guaranteed by design.
3. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following
formula: ITotal_Ieak_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max).
4. All FT_xx IO except FT_lu, FT_u and PC3.
5. VIN must be less than Max(VDDXXX) + 3.6 V.
6. To sustain a voltage higher than MIN(VDD, VDDA, VDD33USB) +0.3 V, the internal pull-up and pull-down resistors must be
disabled.
7. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
8. Max(VDDXXX) is the maximum value of all the I/O supplies.

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All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 25.

Figure 25. VIL/VIH for all I/Os except BOOT0

2.5

TLL requirement: VIHmin = 2 V

0.7V D
D
2 in=
en t: V IHm
uirem
S req +0.25
CMO
=0.47VDD
ulati on VIHmin
1.5 Base d on sim
Voltage

-0.1
=0.4VDD
lation VIL
max

1 s e d o n simu =0 .3 V DD
Ba
ment: VIL
max
require
CMOS
TLL requirement: VILmin = 0.8 V

0.5

0
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

MSv46121V3

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2. In particular:
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 10).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
ΣIVSS (see Table 10).

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Output voltage levels

Unless otherwise specified, the parameters given in Table 55: Output voltage characteristics
for all I/Os except PC13, PC14 and PC15 and Table 56: Output voltage characteristics for
PC13, PC14 and PC15 are derived from tests performed under ambient temperature and
VDD supply voltage conditions summarized in Table 12: General operating conditions. All
I/Os are CMOS and TTL compliant.

Table 55. Output voltage characteristics for all I/Os except PC13, PC14 and PC15(1)
Symbol Parameter Conditions(3) Min Max Unit

CMOS port(2)
VOL Output low level voltage IIO = 8 mA - 0.4
2.7 V≤ VDD ≤3.6 V
CMOS port(2)
VOH Output high level voltage IIO = −8 mA VDD−0.4 -
2.7 V≤ VDD ≤3.6 V
TTL port(2)
VOL(3) Output low level voltage IIO = 8 mA - 0.4
2.7 V≤ VDD ≤3.6 V
TTL port(2)
VOH (3) Output high level voltage IIO = −8 mA 2.4 -
2.7 V≤ VDD ≤3.6 V
V
IIO = 20 mA
VOL(3) Output low level voltage - 1.3
2.7 V≤ VDD ≤3.6 V
IIO = −20 mA
VOH(3) Output high level voltage VDD−1.3 -
2.7 V≤ VDD ≤3.6 V
IIO = 4 mA
VOL(3) Output low level voltage - 0.4
1.62 V≤ VDD ≤3.6 V
IIO = −4 mA
VOH (3) Output high level voltage VDD−-0.4 -
1.62 V≤VDD<3.6 V
IIO = 20 mA
- 0.4
Output low level voltage for an FTf 2.3 V≤ VDD≤3.6 V
VOLFM+(3)
I/O pin in FM+ mode IIO = 10 mA
- 0.4
1.62 V≤ VDD ≤3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 9:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.

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Table 56. Output voltage characteristics for PC13, PC14 and PC15(1)
Symbol Parameter Conditions(3) Min Max Unit

CMOS port(2)
VOL Output low level voltage IIO = 3 mA - 0.4
2.7 V≤ VDD ≤3.6 V
CMOS port(2)
VOH Output high level voltage IIO = −3 mA VDD−0.4 -
2.7 V≤ VDD ≤3.6 V
TTL port(2)
VOL(3) Output low level voltage IIO = 3 mA - 0.4
V
2.7 V≤ VDD ≤3.6 V
TTL port(2)
VOH (2)
Output high level voltage IIO = −3 mA 2.4 -
2.7 V≤ VDD ≤3.6 V
IIO = 1.5 mA
VOL(2) Output low level voltage - 0.4
1.62 V≤ VDD ≤3.6 V
IIO = −1.5 mA
VOH(2) Output high level voltage VDD−0.4 -
1.62 V≤ VDD ≤3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 9:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.

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Output buffer timing characteristics (HSLV option disabled)

The HSLV bit of SYSCFG_CCCSR register can be used to optimize the I/O speed when the
product voltage is below 2.7 V.

Table 57. Output timing characteristics (HSLV OFF)(1)

Speed Symbol Parameter conditions Min Max Unit

C=50 pF, 2.7 V≤ VDD≤3.6 V - 12

C=50 pF, 1.62 V≤VDD≤2.7 V - 3
C=30 pF, 2.7 V≤VDD≤3.6 V - 12
Fmax(2) Maximum frequency MHz
C=30 pF, 1.62 V≤VDD≤2.7 V - 3
C=10 pF, 2.7 V≤VDD≤3.6 V - 16
C=10 pF, 1.62 V≤VDD≤2.7 V - 4
00
C=50 pF, 2.7 V≤ VDD≤3.6 V - 16.6
C=50 pF, 1.62 V≤VDD≤2.7 V - 33.3
Output high to low level C=30 pF, 2.7 V≤VDD≤3.6 V - 13.3
tr/tf(3) fall time and output low ns
to high level rise time C=30 pF, 1.62 V≤VDD≤2.7 V - 25
C=10 pF, 2.7 V≤VDD≤3.6 V - 10
C=10 pF, 1.62 V≤VDD≤2.7 V - 20
C=50 pF, 2.7 V≤ VDD≤3.6 V - 60
C=50 pF, 1.62 V≤VDD≤2.7 V - 15
C=30 pF, 2.7 V≤VDD≤3.6 V - 80
Fmax(2) Maximum frequency MHz
C=30 pF, 1.62 V≤VDD≤2.7 V - 15
C=10 pF, 2.7 V≤VDD≤3.6 V - 110
C=10 pF, 1.62 V≤VDD≤2.7 V - 20
01
C=50 pF, 2.7 V≤ VDD≤3.6 V - 5.2
C=50 pF, 1.62 V≤VDD≤2.7 V - 10
Output high to low level C=30 pF, 2.7 V≤VDD≤3.6 V - 4.2
tr/tf(3) fall time and output low ns
to high level rise time C=30 pF, 1.62 V≤VDD≤2.7 V - 7.5
C=10 pF, 2.7 V≤VDD≤3.6 V - 2.8
C=10 pF, 1.62 V≤VDD≤2.7 V - 5.2

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Table 57. Output timing characteristics (HSLV OFF)(1) (continued)

Speed Symbol Parameter conditions Min Max Unit

C=50 pF, 2.7 V≤VDD≤3.6 V (4)

- 85
C=50 pF, 1.62 V≤VDD≤2.7 V(4) - 35
(4)
C=30 pF, 2.7 V≤VDD≤3.6 V - 110
Fmax(2) Maximum frequency MHz
(4)
C=30 pF, 1.62 V≤VDD≤2.7 V - 40
C=10 pF, 2.7 V≤VDD≤3.6 V(4) - 166
C=10 pF, 1.62 V≤VDD≤2.7 V(4) - 100
10
(4)
C=50 pF, 2.7 V≤VDD≤3.6 V - 3.8
(4)
C=50 pF, 1.62 V≤VDD≤2.7 V - 6.9
Output high to low level C=30 pF, 2.7 V≤VDD≤3.6 V(4) - 2.8
tr/tf(3) fall time and output low ns
to high level rise time C=30 pF, 1.62 V≤VDD≤2.7 V(4) - 5.2
C=10 pF, 2.7 V≤VDD≤3.6 V(4) - 1.8
C=10 pF, 1.62 V≤VDD≤2.7 Vv - 3.3
C=50 pF, 2.7 V≤VDD≤3.6 Vv - 100
C=50 pF, 1.62 V≤VDD≤2.7 V(4) - 50
C=30 pF, 2.7 V≤VDD≤3.6 Vv - 133
Fmax(2) Maximum frequency MHz
C=30 pF, 1.62 V≤VDD≤2.7 V(4) - 66
C=10 pF, 2.7 V≤VDD≤3.6 V(4) - 220
C=10 pF, 1.62 V≤VDD≤2.7 V(4) - 85
11
C=50 pF, 2.7 V≤VDD≤3.6 V(4) - 3.3
C=50 pF, 1.62 V≤VDD≤2.7 V(4) - 6.6
Output high to low level C=30 pF, 2.7 V≤VDD≤3.6 V(4) - 2.4
tr/tf(3) fall time and output low ns
to high level rise time C=30 pF, 1.62 V≤VDD≤2.7 V(4) - 4.5
C=10 pF, 2.7 V≤VDD≤3.6 V(4) - 1.5
C=10 pF, 1.62 V≤VDD≤2.7 V(4) - 2.7
1. Guaranteed by design.
2. The maximum frequency is defined with the following conditions:
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45%<Duty cycle<55%
3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
4. Compensation system enabled.

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Output buffer timing characteristics (HSLV option enabled)

Table 58. Output timing characteristics (HSLV ON)(1)

Speed Symbol Parameter conditions Min Max Unit

C=50 pF, 1.62 V≤VDD≤2.7 V - 10

(2)
Fmax Maximum frequency C=30 pF, 1.62 V≤VDD≤2.7 V - 10 MHz
C=10 pF, 1.62 V≤VDD≤2.7 V - 10
00
C=50 pF, 1.62 V≤VDD≤2.7 V - 11
Output high to low level
tr/tf(3) fall time and output low C=30 pF, 1.62 V≤VDD≤2.7 V - 9 ns
to high level rise time
C=10 pF, 1.62 V≤VDD≤2.7 V - 6.6
C=50 pF, 1.62 V≤VDD≤2.7 V - 50
(2)
Fmax Maximum frequency C=30 pF, 1.62 V≤VDD≤2.7 V - 58 MHz
C=10 pF, 1.62 V≤VDD≤2.7 V - 66
01
C=50 pF, 1.62 V≤VDD≤2.7 V - 6.6
Output high to low level
tr/tf(3) fall time and output low C=30 pF, 1.62 V≤VDD≤2.7 V - 4.8 ns
to high level rise time
C=10 pF, 1.62 V≤VDD≤2.7 V - 3
C=50 pF, 1.62 V≤VDD≤2.7 V(4) - 55
Fmax (2) Maximum frequency C=30 pF, 1.62 V≤VDD≤2.7 V(4) - 80 MHz
C=10 pF, 1.62 V≤VDD≤2.7 V(4) - 133
10
C=50 pF, 1.62 V≤VDD≤2.7 V(4) - 5.8
Output high to low level
tr/tf(3) fall time and output low C=30 pF, 1.62 V≤VDD≤2.7 V(4) - 4 ns
to high level rise time
C=10 pF, 1.62 V≤VDD≤2.7 V(4) - 2.4
C=50 pF, 1.62 V≤VDD≤2.7 V(4) - 60
Fmax (2) Maximum frequency C=30 pF, 1.62 V≤VDD≤2.7 V(4) - 90 MHz
C=10 pF, 1.62 V≤VDD≤2.7 V(4) - 175
11
C=50 pF, 1.62 V≤VDD≤2.7 V(4) - 5.3
Output high to low level
tr/tf(3) fall time and output low C=30 pF, 1.62 V≤VDD≤2.7 V(4) - 3.6 ns
to high level rise time (4)
C=10 pF, 1.62 V≤VDD≤2.7 V - 1.9
1. Guaranteed by design.
2. The maximum frequency is defined with the following conditions:
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45%<Duty cycle<55%
3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
4. Compensation system enabled.

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Analog switch between ports Pxy_C and Pxy

PA0_C, PA1_C, PC2_C and PC3_C can be connected internally to PA0, PA1, PC2 and
PC3, respectively (refer to SYSCFG_PMCR register in RM0468 reference manual). The
switch is controlled by VDDSWITCH voltage level. It is defined through BOOSTVDDSEL bit of
SYSCFG_PMCR. If the switch is closed the switch characteristics are given in the table
below.

Table 59. Pxy_C and Pxy analog switch characteristics

Parameter Conditions Min Typ Max Unit

Switch control boosted - - 315

VDDSWITCH > 2.7 V - - 315

Switch VDDSWITCH > 2.4 V - - 335

Switch control Ω
impedance VDDSWITCH > 2.0 V - - 390
not boosted
VDDSWITCH > 1.8 V - - 445
VDDSWITCH > 1.62 V - - 550

6.3.18 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 54: I/O static characteristics).
Unless otherwise specified, the parameters given in Table 60 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 12: General operating conditions.

Table 60. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

Weak pull-up equivalent

RPU(2) VIN = VSS 30 40 50 ㏀
resistor(1)
VF(NRST)(2) NRST Input filtered pulse 1.71 V < VDD < 3.6 V - - 50
1.71 V < VDD < 3.6 V 350 - - ns
VNF(NRST)(2) NRST Input not filtered pulse
1.62 V < VDD < 3.6 V 1000 - -
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
2. Guaranteed by design.

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Figure 26. Recommended NRST pin protection

VDD
External
reset circuit (1)
RPU
NRST (2) Internal Reset
Filter

0.1 μF

STM32

ai14132d

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 54. Otherwise the reset is not taken into account by the device.

6.3.19 FMC characteristics

Unless otherwise specified, the parameters given in Table 61 to Table 74 for the FMC
interface are derived from tests performed under the ambient temperature, fHCLK frequency
and VDD supply voltage conditions summarized in Table 12: General operating conditions,
with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Measurement points are done at CMOS levels: 0.5VDD
• IO Compensation cell activated.
• HSLV activated when VDD ≤ 2.7 V
• VOS level set to VOS0.
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics.

Asynchronous waveforms and timings

Figure 27 through Figure 29 represent asynchronous waveforms and Table 61 through
Table 68 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
• AddressSetupTime = 0x1
• AddressHoldTime = 0x1
• DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)
• BusTurnAroundDuration = 0x0
• Capacitive load CL = 30 pF
In all timing tables, the TKERCK is the fmc_ker_ck clock period.

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Figure 27. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

tw(NE)

FMC_NE

tv(NOE_NE) t w(NOE) t h(NE_NOE)

FMC_NOE

FMC_NWE

tv(A_NE) t h(A_NOE)

FMC_A[25:0] Address
tv(BL_NE) t h(BL_NOE)

FMC_NBL[1:0]

t h(Data_NE)

t su(Data_NOE) th(Data_NOE)

t su(Data_NE)

FMC_D[15:0] Data

t v(NADV_NE)

tw(NADV)

FMC_NADV (1)

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)

MS32753V1

1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

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Table 61. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 3Tfmc_ker_ck–1 3Tfmc_ker_ck+1

tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 0.5
tw(NOE) FMC_NOE low time 2Tfmc_ker_ck –1 2Tfmc_ker_ck+1
FMC_NOE high to FMC_NE high
th(NE_NOE) Tfmc_ker_ck -
hold time
tv(A_NE) FMC_NEx low to FMC_A valid - 0.5
Address hold time after
th(A_NOE) 2Tfmc_ker_ck -
FMC_NOE high
Data to FMC_NEx high setup ns
tsu(Data_NE) Tfmc_ker_ck+14 -
time
Data to FMC_NOEx high setup
tsu(Data_NOE) 13 -
time
Data hold time after FMC_NOE
th(Data_NOE) 0 -
high
Data hold time after FMC_NEx
th(Data_NE) 0 -
high
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 4
tw(NADV) FMC_NADV low time - Tfmc_ker_ck+1
1. Guaranteed by characterization results.

Table 62. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT

timings(1)(2)
Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 7Tfmc_ker_ck–1 7Tfmc_ker_ck+1

tw(NOE) FMC_NOE low time 5Tfmc_ker_ck–1 5Tfmc_ker_ck +1
tw(NWAIT) FMC_NWAIT low time Tfmc_ker_ck– 0.5 -
ns
FMC_NWAIT valid before FMC_NEx
tsu(NWAIT_NE) 4Tfmc_ker_ck +9 -
high
FMC_NEx hold time after
th(NE_NWAIT) 3Tfmc_ker_ck+12 -
FMC_NWAIT invalid
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 fmc_ker_ck cycle.

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Figure 28. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

tw(NE)

FMC_NEx

FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)

FMC_NWE

tv(A_NE) th(A_NWE)

FMC_A[25:0] Address
tv(BL_NE) th(BL_NWE)

FMC_NBL[1:0] NBL
tv(Data_NE) th(Data_NWE)

FMC_D[15:0] Data
t v(NADV_NE)

tw(NADV)
FMC_NADV (1)

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)
MS32754V1

1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

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Table 63. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 3Tfmc_ker_ck –1 3Tfmc_ker_ck + 1

tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck–1 Tfmc_ker_ck
tw(NWE) FMC_NWE low time Tfmc_ker_ck –0.5 Tfmc_ker_ck+0.5
FMC_NWE high to FMC_NE high
th(NE_NWE) Tfmc_ker_ck -
hold time
tv(A_NE) FMC_NEx low to FMC_A valid - 1
Address hold time after FMC_NWE
th(A_NWE) Tfmc_ker_ck –0.5 -
high ns
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
FMC_BL hold time after FMC_NWE
th(BL_NWE) Tfmc_ker_ck –0.5 -
high
tv(Data_NE) Data to FMC_NEx low to Data valid - Tfmc_ker_ck+ 2
th(Data_NWE) Data hold time after FMC_NWE high Tfmc_ker_ck -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 5
tw(NADV) FMC_NADV low time - Tfmc_ker_ck+ 1
1. Guaranteed by characterization results.

Table 64. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT

timings(1)(2)
Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 8Tfmc_ker_ck –1 8Tfmc_ker_ck+1

tw(NWE) FMC_NWE low time 6Tfmc_ker_ck –1 6Tfmc_ker_ck+1
FMC_NWAIT valid before FMC_NEx ns
tsu(NWAIT_NE) 5Tfmc_ker_ck+13 -
high
FMC_NEx hold time after
th(NE_NWAIT) 4Tfmc_ker_ck+12 -
FMC_NWAIT invalid
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 fmc_ker_ck cycle.

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Figure 29. Asynchronous multiplexed PSRAM/NOR read waveforms

tw(NE)

FMC_ NE
tv(NOE_NE) t h(NE_NOE)

FMC_NOE

t w(NOE)

FMC_NWE

tv(A_NE) th(A_NOE)

FMC_ A[25:16] Address

tv(BL_NE) th(BL_NOE)

FMC_ NBL[1:0] NBL

th(Data_NE)
tsu(Data_NE)
t v(A_NE) tsu(Data_NOE) th(Data_NOE)

FMC_ AD[15:0] Address Data

t v(NADV_NE) th(AD_NADV)
tw(NADV)

FMC_NADV

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)

MS32755V1

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Table 65. Asynchronous multiplexed PSRAM/NOR read timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 4Tfmc_ker_ck –1 4Tfmc_ker_ck +1

2Tfmc_ker_ck
tv(NOE_NE) FMC_NEx low to FMC_NOE low 2Tfmc_ker_ck
+0.5
ttw(NOE) FMC_NOE low time Tfmc_ker_ck –1 Tfmc_ker_ck+1
FMC_NOE high to FMC_NE high hold
th(NE_NOE) Tfmc_ker_ck -
time
tv(A_NE) FMC_NEx low to FMC_A valid - 0.5
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 4.0
tw(NADV) FMC_NADV low time Tfmc_ker_ck –0.5 Tfmc_ker_ck +1 ns
FMC_AD(address) valid hold time
th(AD_NADV) Tfmc_ker_ckk –4 -
after FMC_NADV high)
Address hold time after FMC_NOE
th(A_NOE) Tfmc_ker_ck –0.5 -
high
tsu(Data_NE) Data to FMC_NEx high setup time Tfmc_ker_ck +14 -
tsu(Data_NOE) Data to FMC_NOE high setup time 13 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
1. Guaranteed by characterization results.

Table 66. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 8Tfmc_ker_ck –1 8Tfmc_ker_ck +1

tw(NOE) FMC_NWE low time 5Tfmc_ker_ck –1 5Tfmc_ker_ck +1
FMC_NWAIT valid before ns
tsu(NWAIT_NE) 4Tfmc_ker_ck +9 -
FMC_NEx high
FMC_NEx hold time after
th(NE_NWAIT) 3Tfmc_ker_ck +12 -
FMC_NWAIT invalid
1. Guaranteed by characterization results.

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Table 67. Asynchronous multiplexed PSRAM/NOR write timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 4Tfmc_ker_ck –1 4Tfmc_ker_ck

tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck –1 Tfmc_ker_ck +0.5
tw(NWE) FMC_NWE low time 2Tfmc_ker_ck –0.5 2Tfmc_ker_ck +0.5
FMC_NWE high to FMC_NE high hold
th(NE_NWE) Tfmc_ker_ck –0.5 -
time
tv(A_NE) FMC_NEx low to FMC_A valid - 1
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 5.0
tw(NADV) FMC_NADV low time Tfmc_ker_ck –0.5 Tfmc_ker_ck + 1
ns
FMC_AD(adress) valid hold time after
th(AD_NADV) Tfmc_ker_ck –4.5 -
FMC_NADV high)
Address hold time after FMC_NWE
th(A_NWE) Tfmc_ker_ck – 0.5 -
high
FMC_BL hold time after FMC_NWE
th(BL_NWE) Tfmc_ker_ck – 0.5 -
high
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
tv(Data_NADV) FMC_NADV high to Data valid - Tfmc_ker_ck +2
th(Data_NWE) Data hold time after FMC_NWE high Tfmc_ker_ck -
1. Guaranteed by characterization results.

Table 68. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 9Tfmc_ker_ck –1 9Tfmc_ker_ck

tw(NWE) FMC_NWE low time 7Tfmc_ker_ck –0.5 7Tfmc_ker_ck +0.5
FMC_NWAIT valid before FMC_NEx ns
tsu(NWAIT_NE) 5Tfmc_ker_ck +9 -
high
FMC_NEx hold time after
th(NE_NWAIT) 4Tfmc_ker_ck +12 -
FMC_NWAIT invalid
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 fmc_ker_ck cycle.

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Synchronous waveforms and timings

Figure 30 through Figure 33 represent synchronous waveforms and Table 69 through
Table 72 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
• BurstAccessMode = FMC_BurstAccessMode_Enable
• MemoryType = FMC_MemoryType_CRAM
• WriteBurst = FMC_WriteBurst_Enable
• CLKDivision = 1
• DataLatency = 1 for NOR Flash, DataLatency = 0 for PSRAM, CL = 30 pF
In all the timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following
FMC_CLK maximum values:
• For 2.7 V<VDD<3.6 V: maximum FMC_CLK = 137 MHz at CL = 20 pF
• For 1.8 V<VDD<1.9 V: maximum FMC_CLK = 100 MHz at CL = 20 pF
• For 1.62 V<VDD<1.8 V: maximumFMC_CLK = 88 MHz at CL = 15 pF

Figure 30. Synchronous multiplexed NOR/PSRAM read timings

tw(CLK) tw(CLK) BUSTURN = 0

FMC_CLK

Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx
t d(CLKL-NADVL) td(CLKL-NADVH)

FMC_NADV
td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16]

td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE
td(CLKL-ADIV) th(CLKH-ADV)
t d(CLKL-ADV) tsu(ADV-CLKH) tsu(ADV-CLKH) th(CLKH-ADV)

FMC_AD[15:0] AD[15:0] D1 D2
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV)

MS32757V1

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Table 69. Synchronous multiplexed NOR/PSRAM read timings(1)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period 2Tfmc_ker_ck –0.5 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 3
td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2) Tfmc_ker_ck+1.5 -

FMC_CLK low to 1.62 V <VDD < 3.6 V 5.5

td(CLKL-NADVL) -
FMC_NADV low 2.7 V <VDD < 3.6 V 2

FMC_CLK low to 1.62 V <VDD < 3.6 V -

td(CLKL-NADVH) 1
FMC_NADV high 2.7 V <VDD < 3.6 V -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 3
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) Tfmc_ker_ck -
ns
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 2.5
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high Tfmc_ker_ck +1 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 3 -
th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 0 -
tsu(NWAIT-
FMC_NWAIT valid before FMC_CLK high 3 -
CLKH)

th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2.5 -

1. Guaranteed by characterization results.

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Figure 31. Synchronous multiplexed PSRAM write timings

tw(CLK) tw(CLK) BUSTURN = 0

FMC_CLK

Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx
td(CLKL-NADVL) td(CLKL-NADVH)

FMC_NADV
td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16]

td(CLKL-NWEL) td(CLKH-NWEH)

FMC_NWE
td(CLKL-ADIV) td(CLKL-Data)
td(CLKL-ADV) td(CLKL-Data)

FMC_AD[15:0] AD[15:0] D1 D2

FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV)

td(CLKH-NBLH)

FMC_NBL

MS32758V1

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Table 70. Synchronous multiplexed PSRAM write timings(1)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period, VDD = 2.7 to 3.6 V 2Tfmc_ker_ck –0.5 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x =0..2) - 3
FMC_CLK high to FMC_NEx high
td(CLKH-NExH) Tfmc_ker_ck +1.5 -
(x = 0…2)

FMC_CLK low to 1.62 V <VDD < 3.6 V 5.5

td(CLKL-NADVL) -
FMC_NADV low 2.7 V <VDD < 3.6 V 2.0

FMC_CLK low to 1.62 V <VDD < 3.6 V -

td(CLKL-NADVH) 1
FMC_NADV high 2.7 V <VDD < 3.6 V -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x =16…25) - 3
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x =16…25) Tfmc_ker_ck - ns
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 2.5
t(CLKH-NWEH) FMC_CLK high to FMC_NWE high Tfmc_ker_ck +1 -
td(CLKL-ADV) FMC_CLK low to to FMC_AD[15:0] valid - 2.5
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 3.5
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Tfmc_ker_ck +0.5 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 3 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2.5 -
1. Guaranteed by characterization results.

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Figure 32. Synchronous non-multiplexed NOR/PSRAM read timings

tw(CLK) tw(CLK)

FMC_CLK
td(CLKL-NExL) td(CLKH-NExH)
Data latency = 0
FMC_NEx
td(CLKL-NADVL) td(CLKL-NADVH)

FMC_NADV
td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0]

td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE
tsu(DV-CLKH) th(CLKH-DV)
tsu(DV-CLKH) th(CLKH-DV)

FMC_D[15:0] D1 D2

tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) t h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)

MS32759V1

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Table 71. Synchronous non-multiplexed NOR/PSRAM read timings(1)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period 2Tfmc_ker_ck –0.5 -

t(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 3
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) Tfmc_ker_ck+1.5 -

FMC_CLK low to 1.62 V <VDD < 3.6 V 5.5

td(CLKL-NADVL) -
FMC_NADV low 2.7 V <VDD < 3.6 V 2.0

FMC_CLK low to 1.62 V <VDD < 3.6 V -

td(CLKL-NADVH) 1
FMC_NADV high 2.7 V <VDD < 3.6 V -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 3 ns
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) Tfmc_ker_ck -
td(CLKL-NOEL) FMC_CLK ow to FMC_NOE low - 2.5
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high Tfmc_ker_ck+1 -
tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 3 -
th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 0 -
t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 3 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2.5 -
1. Guaranteed by characterization results.

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Figure 33. Synchronous non-multiplexed PSRAM write timings

tw(CLK) tw(CLK)

FMC_CLK

td(CLKL-NExL) td(CLKH-NExH)
Data latency = 0
FMC_NEx

td(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV

td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0]

td(CLKL-NWEL) td(CLKH-NWEH)
FMC_NWE

td(CLKL-Data) td(CLKL-Data)

FMC_D[15:0] D1 D2

FMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) td(CLKH-NBLH)
th(CLKH-NWAITV)
FMC_NBL

MS32760V1

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Table 72. Synchronous non-multiplexed PSRAM write timings(1)

Symbol Parameter Min Max Unit

t(CLK) FMC_CLK period 2Tfmc_ker_ck –0.5 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 3
t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) Tfmc_ker_ck+1.5 -

FMC_CLK low to 1.62 V <VDD < 3.6 V 5.5

td(CLKL-NADVL) -
FMC_NADV low 2.7 V <VDD < 3.6 V 2

FMC_CLK low to 1.62 V <VDD < 3.6 V -

td(CLKL-NADVH) 1
FMC_NADV high 2.7 V <VDD < 3.6 V -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 3
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) Tfmc_ker_ck - ns

td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 2.5

td(CLKH-NWEH) FMC_CLK high to FMC_NWE high Tfmc_ker_ck+1 -
td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 3.5
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Tfmc_ker_ck+0.5 -
tsu(NWAIT-
FMC_NWAIT valid before FMC_CLK high 3 -
CLKH)

th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2.5 -

1. Guaranteed by characterization results.

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NAND controller waveforms and timings

Figure 34 through Figure 37 represent synchronous waveforms, and Table 73 and Table 74
provide the corresponding timings. The results shown in this table are obtained with the
following FMC configuration and a capacitive load (CL) of 30 pF:
• COM.FMC_SetupTime = 0x01
• COM.FMC_WaitSetupTime = 0x03
• COM.FMC_HoldSetupTime = 0x02
• COM.FMC_HiZSetupTime = 0x01
• ATT.FMC_SetupTime = 0x01
• ATT.FMC_WaitSetupTime = 0x03
• ATT.FMC_HoldSetupTime = 0x02
• ATT.FMC_HiZSetupTime = 0x01
• Bank = FMC_Bank_NAND
• MemoryDataWidth = FMC_MemoryDataWidth_16b
• ECC = FMC_ECC_Enable
• ECCPageSize = FMC_ECCPageSize_512Bytes
• TCLRSetupTime = 0
• TARSetupTime = 0
In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period.

Figure 34. NAND controller waveforms for read access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)

FMC_NWE

td(ALE-NOE) th(NOE-ALE)

FMC_NOE (NRE)

tsu(D-NOE) th(NOE-D)
FMC_D[15:0]

MS32767V1

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Figure 35. NAND controller waveforms for write access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NWE) th(NWE-ALE)

FMC_NWE

FMC_NOE (NRE)
tv(NWE-D) th(NWE-D)

FMC_D[15:0]

MS32768V1

Figure 36. NAND controller waveforms for common memory read access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE) th(NOE-ALE)

FMC_NWE

tw(NOE)
FMC_NOE

tsu(D-NOE) th(NOE-D)

FMC_D[15:0]

MS32769V1

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Figure 37. NAND controller waveforms for common memory write access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE) tw(NWE) th(NOE-ALE)

FMC_NWE

FMC_N OE

td(D-NWE)

tv(NWE-D) th(NWE-D)

FMC_D[15:0]

MS32770V1

Table 73. Switching characteristics for NAND Flash read cycles(1)

Symbol Parameter Min Max Unit

tw(N0E) FMC_NOE low width 4Tfmc_ker_ck – 0.5 4Tfmc_ker_ck+0.5

FMC_D[15-0] valid data before
tsu(D-NOE) 11 -
FMC_NOE high
FMC_D[15-0] valid data after ns
th(NOE-D) 0 -
FMC_NOE high
td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 3Tfmc_ker_ck +0.5
th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 4Tfmc_ker_ck –1 -
1. Guaranteed by characterization results.

Table 74. Switching characteristics for NAND Flash write cycles(1)

Symbol Parameter Min Max Unit

tw(NWE) FMC_NWE low width 4Tfmc_ker_ck – 0.5 4Tfmc_ker_ck +0.5

FMC_NWE low to FMC_D[15-0]
tv(NWE-D) 0 -
valid
FMC_NWE high to FMC_D[15-0]
th(NWE-D) 2Tfmc_ker_ck +1.5 -
invalid
FMC_D[15-0] valid before ns
td(D-NWE) 5Tfmc_ker_ck – 5 -
FMC_NWE high
FMC_ALE valid before FMC_NWE
td(ALE-NWE) - 3Tfmc_ker_ck +0.5
low
FMC_NWE high to FMC_ALE
th(NWE-ALE) 2Tfmc_ker_ck – 0.5 -
invalid
1. Guaranteed by characterization results.

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SDRAM waveforms and timings

In all timing tables, the TKERCK is the fmc_ker_ck clock period, with the following
FMC_SDCLK maximum values:
• For 2.7 V<VDD<3.6 V: maximum FMC_CLK = 95 MHz at 20 pF
• For 1.8 V<VDD<1.9 V: maximum FMC_CLK = 90 MHz at 20 pF
• For 1.62 V<DD<1.8 V: maximum FMC_CLK = 85 MHz at 15 pF

Figure 38. SDRAM read access waveforms (CL = 1)

FMC_SDCLK
td(SDCLKL_AddC)
td(SDCLKL_AddR) th(SDCLKL_AddR)

FMC_A[12:0] Row n Col1 Col2 Coli Coln

th(SDCLKL_AddC)

td(SDCLKL_SNDE) th(SDCLKL_SNDE)

FMC_SDNE[1:0]
td(SDCLKL_NRAS) th(SDCLKL_NRAS)

FMC_SDNRAS

td(SDCLKL_NCAS) th(SDCLKL_NCAS)

FMC_SDNCAS

FMC_SDNWE
tsu(SDCLKH_Data) th(SDCLKH_Data)

FMC_D[31:0] Data1 Data2 Datai Datan

MS32751V2

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Table 75. SDRAM read timings(1)

Symbol Parameter Min Max Unit

2Tfmc_ker_ck – 2Tfmc_ker_ck
tw(SDCLK) FMC_SDCLK period
0.5 +0.5
tsu(SDCLKH _Data) Data input setup time 3 -
th(SDCLKH_Data) Data input hold time 1.5 -
td(SDCLKL_Add) Address valid time - 2.0
td(SDCLKL- SDNE) Chip select valid time - 1.5(2) ns
th(SDCLKL_SDNE) Chip select hold time 0 -
td(SDCLKL_SDNRAS) SDNRAS valid time - 1
th(SDCLKL_SDNRAS) SDNRAS hold time 0 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 2.0
th(SDCLKL_SDNCAS) SDNCAS hold time 0.5 -
1. Guaranteed by characterization results.
2. Using PC2_C I/O adds 4.5 ns to this timing.

Table 76. LPSDR SDRAM read timings(1)

Symbol Parameter Min Max Unit

2Tfmc_ker_ck –
tW(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck+0.5
0.5
tsu(SDCLKH_Data) Data input setup time 3 -
th(SDCLKH_Data) Data input hold time 2.5 -
td(SDCLKL_Add) Address valid time - 2
td(SDCLKL_SDNE) Chip select valid time - 1.5(2)(3) ns
th(SDCLKL_SDNE) Chip select hold time 0 -
td(SDCLKL_SDNRAS SDNRAS valid time - 1
th(SDCLKL_SDNRAS) SDNRAS hold time 0 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 2
th(SDCLKL_SDNCAS) SDNCAS hold time 0.5 -
1. Guaranteed by characterization results.
2. Using PC2 I/O adds 4 ns to this timing.
3. Using PC2_C I/O adds 16.5 ns to this timing.

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Figure 39. SDRAM write access waveforms

FMC_SDCLK
td(SDCLKL_AddC)
td(SDCLKL_AddR) th(SDCLKL_AddR)

FMC_A[12:0] Row n Col1 Col2 Coli Coln

th(SDCLKL_AddC)

td(SDCLKL_SNDE) th(SDCLKL_SNDE)

FMC_SDNE[1:0]
td(SDCLKL_NRAS) th(SDCLKL_NRAS)

FMC_SDNRAS

td(SDCLKL_NCAS) th(SDCLKL_NCAS)

FMC_SDNCAS
td(SDCLKL_NWE) th(SDCLKL_NWE)

FMC_SDNWE
td(SDCLKL_Data)

FMC_D[31:0] Data1 Data2 Datai Datan

td(SDCLKL_NBL) th(SDCLKL_Data)

FMC_NBL[3:0]
MS32752V2

Table 77. SDRAM Write timings(1)

Symbol Parameter Min Max Unit

tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck – 0.5 2Tfmc_ker_ck+0.5

td(SDCLKL _Data) Data output valid time - 2
th(SDCLKL _Data) Data output hold time 0.5 -
td(SDCLKL_Add) Address valid time - 2
td(SDCLKL_SDNWE) SDNWE valid time - 2
th(SDCLKL_SDNWE) SDNWE hold time 0 -
ns
td(SDCLKL_ SDNE) Chip select valid time - 1.5(2)
th(SDCLKL-_SDNE) Chip select hold time 0 -
td(SDCLKL_SDNRAS) SDNRAS valid time - 1
th(SDCLKL_SDNRAS) SDNRAS hold time 0 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 2
td(SDCLKL_SDNCAS) SDNCAS hold time 0.5 -
1. Guaranteed by characterization results.
2. Using PC2_C I/O adds 4.5 ns to this timing.

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Table 78. LPSDR SDRAM Write timings(1)

Symbol Parameter Min Max Unit

tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck – 0.5 2Tfmc_ker_ck+0.5

td(SDCLKL _Data) Data output valid time - 2
th(SDCLKL _Data) Data output hold time 0 -
td(SDCLKL_Add) Address valid time - 2.5
td(SDCLKL-SDNWE) SDNWE valid time - 2
th(SDCLKL-SDNWE) SDNWE hold time 0 -
ns
td(SDCLKL- SDNE) (2)(3)
Chip select valid time - 1.5
th(SDCLKL- SDNE) Chip select hold time 0 -
td(SDCLKL-SDNRAS) SDNRAS valid time - 1
th(SDCLKL-SDNRAS) SDNRAS hold time 0 -
td(SDCLKL-SDNCAS) SDNCAS valid time - 2
td(SDCLKL-SDNCAS) SDNCAS hold time 0.5 -
1. Guaranteed by characterization results.
2. Using PC2 I/O adds 4 ns to this timing.
3. Using PC2_C I/O adds 16.5 ns to this timing.

6.3.20 Octo-SPI interface characteristics

Unless otherwise specified, the parameters given in Table 79 and Table 81 for OCTOSPI
are derived from tests performed under the ambient temperature, fHCLK frequency and VDD
supply voltage conditions summarized in Table 12: General operating conditions, with the
following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Measurement points are done at CMOS levels: 0.5VDD
• IO Compensation cell activated.
• HSLV activated when VDD ≤ 2.5 V
• VOS level set to VOS0
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics.

Table 79. OCTOSPI characteristics in SDR mode(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

1.71 V < VDD < 3.6 V,

VOS0, - - 92
CLOAD = 15 pF
1.71 V < VDD < 3.6 V,
F(CLK) OCTOSPI clock frequency - - 90 MHz
VOS0, CLOAD =20 pF
2.7 V < VDD < 3.6 V,
VOS0, - - 140
CLOAD = 20 pF

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Table 79. OCTOSPI characteristics in SDR mode(1)(2) (continued)

Symbol Parameter Conditions Min Typ Max Unit

tw(CKH) OCTOSPI clock high and low PRESCALER[7:0] = n t(CK)/2 - t(CK)/2+1

tw(CKL) time, even division = 0,1,3,5 t(CK)/2–1 - t(CK)/2
(n/2)*t(CK)/ (n/2)*t(CK)/
tw(CKH) -
OCTOSPI clock high and low PRESCALER[7:0] = n (n+1) (n+1)+1
time, odd division = 2,4,6,8 (n/2+1)*t(CK)/ (n/2+1)*t(CK)
tw(CKL) - ns
(n+1)–1 /(n+1)
ts(IN)(3) Data input setup time - 3.0 - -
th(IN) (3) Data input hold time - 1.5 - -
tv(OUT) Data output valid time - - 0.5 1(4)
th(OUT) Data output hold time - 0 - -
1. All values apply to Octal and Quad-SPI mode.
2. Guaranteed by characterization results.
3. Delay block bypassed.
4. Using PC2 or PC3 I/O in the data bus adds 4 ns to this timing value.

Figure 40. OCTOSPI SDR read/write timing diagram

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)

Clock
tv(OUT) th(OUT)

Data output D0 D1 D2

ts(IN) th(IN)

Data input D0 D1 D2
MSv36878V3

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Table 80. OCTOSPI characteristics in DTR mode (no DQS)(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

1.71 V < VDD < 3.6 V,

- - 90(4)
VOS0, CLOAD = 15 pF
1.71 V < VDD < 3.6 V,
FCK(3) OCTOSPI clock frequency - - 87(4) MHz
VOS0, CLOAD = 20 pF
2.7 V < VDD < 3.6 V,
- - 110
VOS0, CLOAD = 20 pF
tw(CKH) OCTOSPI clock high and PRESCALER[7:0] = n t(CK)/2 - t(CK)/2+1
tw(CKL) low time, even division = 0,1,3,5 t(CK)/2–1 - t(CK)/2
(n/2)*t(CK)/ (n/2)*t(CK)/
tw(CKH) -
OCTOSPI clock high and PRESCALER[7:0] = n (n+1) (n+1)+1
low time, odd division = 2,4,6,8 (n/2+1)*t(CK)/( (n/2+1)*
tw(CKL) -
n+1) – 1 t(CK)/(n+1)
tsr(IN)
Data input setup time - 3.0 - -
tsf(IN)(5)
ns
thr(IN)
Data input hold time - 1.50 - -
thf(IN)(5)
DHQC = 0 - 6 7(6)
tvr(OUT)
Data output valid time DHQC = 1, tpclk/4+ tpclk/4+1.25
tvf(OUT) - (6)
Prescaler = 1,2 ... 1
DHQC = 0 4.5 - -
thr(OUT)
Data output hold time DHQC = 1,
thf(OUT) tpclk/4 - -
Prescaler = 1,2 ...
1. All values apply to Octal and Quad-SPI mode.
2. Guaranteed by characterization results.
3. DHQC must be set to reach the mentioned frequency.
4. Using PC2 or PC3 I/O in the data bus decreases the frequency to 47 MHz.
5. Delay block bypassed.
6. Using PC2 or PC3 I/O in the data bus adds 4 ns to this timing value.

Figure 41. OCTOSPI DTR mode timing diagram

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)

Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)

Data output D0 D1 D2 D3 D4 D5

tsf(IN) thf(IN) tsr(IN) thr(IN)

Data input D0 D1 D2 D3 D4 D5

MSv36879V4

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Table 81. OCTOSPI characteristics in DTR mode (with DQS)/Octal and Hyperbus(1)
Symbol Parameter Conditions Min Typ Max Unit

2,7 V < VDD < 3.6 V,

- - 100
VOS0, CLOAD = 20 pF
FCK(2)(3) OCTOSPI clock frequency MHz
1.71 V < VDD < 3.6 V,
- - 100(4)
VOS0, CLOAD = 20 pF
tw(CKH) OCTOSPI clock high and PRESCALER[7:0] = n = t(CK)/2 - t(CK)/2+1
ns
tw(CKL) low time, even division 0,1,3,5 t(CK)/2–1 - t(CK)/2
(n/2)*t(CK)/ (n/2)*t(CK)/
tw(CKH) -
OCTOSPI clock high and PRESCALER[7:0] = n = (n+1) (n+1)+1
low time, odd division 2,4,6,8 (n/2+1)*t(CK)/( (n/2+1)*t(CK)/
tw(CKL) - ns
n+1)–1 (n+1)
tv(CK) Clock valid time - - - t(CK)+1
th(CK) Clock hold time - t(CK)/2 - -
CK,CK crossing level on CK
VODr(CK) VDD = 1.8 V 922 - 1229
rising edge
mV
CK,CK crossing level on CK
VODf(CK) VDD = 1.8 V 1000 - 1277
falling edge
tw(CS) Chip select high time - 3*t(CK) - -
tv(DQ) Data input vallid time - 0 - -
tv(DS) Data strobe input valid time - 0 - -
th(DS) Data strobe input hold time - 0 - -
Data strobe output valid
tv(RWDS) - - - 3 x t(CK)
time
tsr(DQ) Rising edge 0 - -
Data input setup time
tsf(DQ) Falling edge 0 - -
thr(DQ) Rising edge 1 - -
Data input hold time
thf(DQ) Falling edge 1 - -
(5) ns
DHQC = 0 - 6 7
Data output valid time rising
tvr(OUT) DHQC = 1, tpclk/4+ tpclk/4+1.25
edge - (5)
Prescaler = 1,2... 1
DHQC = 0 - 5.5 6(5)
Data output valid time
tvf(OUT) DHQC = 1, tpclk/4+ tpclk/4+0.75
falling edge - (5)
Prescaler = 1,2... 0.5
DHQC = 0 4.5 - -
Data output hold time rising
thr(OUT) DHQC = 1,
edge tpclk/4 - -
Prescaler = 1,2...
DHQC = 0 4.5 - -
Data output hold time falling
thf(OUT) DHQC = 1,
edge tpclk/4 - -
Prescaler = 1,2...
1. Guaranteed by characterization results.

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2. Maximum frequency values are given for a RWDS to DQ skew of maximum +/-1.0 ns.
3. Activating DHQC is mandatory to reach this frequency
4. Using PC2 or PC3 I/O on data bus decreases the frequency to 47 MHz.
5. Using PC2 or PC3 I/O on the data bus adds 4 ns to this timing value.

Figure 42. OCTOSPI Hyperbus clock timing diagram

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)

tf(NCLK) t(NCLK) tw(NCLKL) tw(NCLKH) tr(NCLK)

NCLK

VOD(CLK)
CLK
MSv47732V3

Figure 43. OCTOSPI Hyperbus read timing diagram

tw(CS)

NCS

tv(CLK) t ACC= Initial access th(CLK)

CLK, NCLK

tv(RWDS) tv(DS) th(DS)

RWDS

tv(OUT) th(OUT) Latency count tv(DQ) ts(DQ) th(DQ)

47:40 39:32 31:24 23:16 15:8 7:0 Dn Dn Dn+1 Dn+1

DQ[7:0] A B A B

Command address
Memory drives DQ[7:0] and RWDS.
Host drives DQ[7:0] and the memory drives RWDS. MSv47733V3

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Figure 44. OCTOSPI Hyperbus write timing diagram

tw(CS)

NCS

Read write recovery Access latency

tv(CLK) th(CLK)

CLK, NCLK

tv(RWDS) High = 2x latency count tv(OUT) th(OUT)

Low = 1x latency count
RWDS

Latency count
tv(OUT) th(OUT) tv(OUT) th(OUT)

Dn Dn Dn+1 Dn+1
DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0
A B A B

Command address Host drives DQ[7:0] and RWDS.

Host drives DQ[7:0] and the memory drives RWDS.
MSv47734V3

6.3.21 Delay block (DLYB) characteristics

Unless otherwise specified, the parameters given in Table 82 for Delay Block are derived
from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply
voltage summarized in Table 12: General operating conditions, with the following
configuration:

Table 82. Delay Block characteristics

Symbol Parameter Conditions Min Typ Max Unit

tinit Initial delay - 900 1300 1900 ps

t∆ Unit Delay - 28 33 41 -

6.3.22 16-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 83, Table 84 and Table 85 are
derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA
supply voltage conditions summarized in Table 12: General operating conditions.

Table 83. 16-bit ADC characteristics(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

Analog supply
VDDA voltage for ADC - 1.62 - 3.6
ON

Positive VDDA ≥ 2 V 1.62 - VDDA

V
VREF+
reference voltage VDDA < 2 V VDDA

Negative
VREF- - VSSA
reference voltage

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Table 83. 16-bit ADC characteristics(1)(2) (continued)

Symbol Parameter Conditions Min Typ Max Unit

BOOST = 11 0.12 - 50

BOOST = 10 0.12 - 25
ADC clock
fADC 1.62 V ≤ VDDA ≤ 3.6 V MHz
frequency BOOST = 01 0.12 - 12.5

BOOST = 00 - - 6.25

Resolution = 16 bits,
fADC = 36 MHz SMP = 1.5 - - 3.60
VDDA >2.5 V
TJ = 90 °C
Resolution = 16 bits fADC = 37 MHz SMP = 2.5 - - 3.35

Resolution = 14 bits fADC = 50 MHz SMP = 2.5 - - 5.00

Resolution = 12 bits fADC = 50 MHz SMP = 2.5 - - 5.50

TJ = 125 °C
Sampling rate for Resolution = 10 bits fADC = 50 MHz SMP = 1.5 - - 7.10
Direct channels
Resolution = 8 bits fADC = 50 MHz SMP = 1.5 - - 8.30

Resolution = 14 bits fADC = 49 MHz SMP = 1.5 - - 4.90

Resolution = 12 bits fADC = 50 MHz SMP = 1.5 - - 5.50

TJ = 140 °C
Resolution = 10 bits fADC = 50 MHz SMP = 1.5 - - 6.70

Resolution = 8 bits fADC = 50 MHz SMP = 1.5 - - 8.30

Resolution = 16 bits,
fADC = 32 MHz SMP = 2.5 - - 2.90
VDDA >2.5 V TJ = 90 °C
Resolution = 16 bits fADC = 31 MHz SMP = 2.5 - - 2.80

Resolution = 14 bits fADC = 33 MHz SMP = 2.5 - - 3.30

fs(3) MSps
Resolution = 12 bits fADC = 39 MHz SMP = 2.5 - - 4.30
Sampling rate for TJ = 125 °C
Fast channels Resolution = 10 bits fADC = 48 MHz SMP = 2.5 - - 6.00

Resolution = 8 bits fADC = 50 MHz SMP = 2.5 - - 7.10

Resolution = 12 bits fADC = 37 MHz SMP = 2.5 - - 4.10

Resolution = 10 bits TJ = 140 °C fADC = 46 MHz SMP = 2.5 - - 5.70

Resolution = 8 bits fADC = 50 MHz SMP = 2.5 - - 7.10

Resolution = 16 bits TJ = 90 °C - -

resolution = 14 bits - -

resolution = 12 bits - -
TJ = 125 °C
resolution = 10 bits - -
Sampling rate for
1.00
Slow channels(4)
resolution = 8 bits - -

resolution = 12 bits - -

resolution = 10 bits TJ = 140 °C - -

resolution = 8 bits - -

External trigger 1/
tTRIG Resolution = 16 bits - - 10
period fADC

Conversion
VAIN(5) - 0 - VREF+ V
voltage range

Common mode VREF/2 VREF/ VREF/2

VCMIV - V
input voltage − 10% 2 + 10%

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Table 83. 16-bit ADC characteristics(1)(2) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Resolution = 16 bits, TJ = 125 °C - - - - 170

Resolution = 14 bits, TJ = 125 °C - - - - 435

External input
RAIN(6) Resolution = 12 bits, TJ =125 °C - - - - 1,150 Ω
impedance
Resolution = 10 bits, TJ = 125 °C - - - - 5,650

Resolution = 8 bits, TJ = 125 °C - - - - 26,500

Internal sample
CADC and hold - - 4 - pF
capacitor

tADCVREG ADC LDO startup

- - 5 10 us
_STUP time

conver
ADC Power-up
tSTAB LDO already started 1 - - sion
time
cycle

Offset and
tCAL linearity - 16,5010 1/fADC
calibration time

tOFF_ Offset calibration

- 1,280 1/fADC
CAL time

Trigger CKMODE = 00 1.5 2 2.5

conversion
CKMODE = 01 - - 2.5
latency regular
tLATR 1/fADC
and injected
CKMODE = 10 - - 2.5
channels without
conversion abort CKMODE = 11 - - 2.25

Trigger CKMODE = 00 2.5 3 3.5

conversion
CKMODE = 01 - - 3.5
latency regular
tLATRINJ 1/fADC
injected channels
CKMODE = 10 - - 3.5
aborting a regular
conversion CKMODE = 11 - - 3.25

tS Sampling time - 1.5 - 810.5 1/fADC

Total conversion
ts + 0.5
tCONV time (including Resolution = N bits - - 1/fADC
+ N/2
sampling time)

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Table 83. 16-bit ADC characteristics(1)(2) (continued)

Symbol Parameter Conditions Min Typ Max Unit

ADC Resolution = 16 bits, fADC = 25 MHz - - - 1,440 -

consumption on
VDDA, Resolution = 14 bits, fADC = 30 MHz - - - 1,350 -
BOOST=11,
Differential mode Resolution = 12 bits, fADC = 40 MHz - - - 990 -

ADC Resolution = 16 bits - - - 1,080 -

consumption on
VDDA, Resolution = 14 bits - - - 810 -
BOOST=10,
Differential mode, Resolution = 12 bits - - - 585 -
fADC = 25 MHz
IDDA_D
(ADC) ADC Resolution = 16 bits - - - 630 -
consumption on
VDDA, Resolution = 14 bits - - - 432 -
BOOST=01,
Differential mode, Resolution = 12 bits - - - 315 -
fADC = 12.5 MHz

ADC Resolution = 16 bits - - - 360 -

consumption on
VDDA, Resolution = 14 bits - - - 270 -
BOOST=00,
Differential mode, Resolution = 12 bits - - - 225 -
fADC = 6.25 MHz

ADC Resolution = 16 bits, fADC=25 MHz - - - 720 -

consumption on
VDDA, Resolution = 14 bits, fADC=30 MHz - - - 675 -
BOOST=11,
Single-ended Resolution = 12 bits, fADC=40 MHz - - - 495 -
mode
µA
ADC Resolution = 16 bits - - - 540 -
consumption on
VDDA, Resolution = 14 bits - - - 405 -
BOOST=10,
Singl-ended
mode, Resolution = 12 bits - - - 292.5 -
fADC = 25 MHz
IDDA_SE
(ADC) ADC Resolution = 16 bits - - - 315 -
consumption on
VDDA, Resolution = 14 bits - - - 216 -
BOOST=01,
Single-ended
mode, Resolution = 12 bits - - - 157.5 -
fADC = 12.5 MHz

ADC Resolution = 16 bits - - - 180 -

consumption on
VDDA Resolution = 14 bits - - - 135 -
BOOST=00,
Single-ended
mode Resolution = 12 bits - - - 112.5 -
fADC=6.25 MHz

fADC=50 MHz - - - 400 -

fADC=25 MHz - - - 220 -

ADC
IDD
consumption on fADC=12.5 MHz - - - 180 -
(ADC)
VDD
fADC=6.25 MHz - - - 120 -

fADC=3.125 MHz - - - 80 -

1. Guaranteed by design.
2. The voltage booster on ADC switches must be used for VDDA < 2.4 V (embedded I/O switches).
3. These values are valid for TFBGA100, UFBGA169 and UFBGA176+25 packages and one ADC. The values for other packages and multiple
ADCs may be different.
4. For slow channels, the performance should be limited to 1 Msps what ever the value of fADC.

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5. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA.
6. The tolerance is 10 LSBs for 16-bit resolution, 4 LSBs for 14-bit resolution, and 2 LSBs for 12-bit, 10-bit and 8-bit resolutions.

Table 84. Minimum sampling time vs RAIN (16-bit ADC)(1)(2)

Minimum sampling time (s)
Resolution RAIN (Ω)
Direct
Fast channels(4) Slow channels(5)
channels(3)

16 bits 47 7.37E-08 1.14E-07 1.72E-07

47 6.29E-08 9.74E-08 1.55E-07
68 6.84E-08 1.02E-07 1.58E-07
14 bits 100 7.80E-08 1.12E-07 1.62E-07
150 9.86E-08 1.32E-07 1.80E-07
220 1.32E-07 1.61E-07 2.01E-07
47 5.32E-08 8.00E-08 1.29E-07
68 5.74E-08 8.50E-08 1.32E-07
100 6.58E-08 9.31E-08 1.40E-07
150 8.37E-08 1.10E-07 1.51E-07
12 bits
220 1.11E-07 1.34E-07 1.73E-07
330 1.56E-07 1.78E-07 2.14E-07
470 2.16E-07 2.39E-07 2.68E-07
680 3.01E-07 3.29E-07 3.54E-07
47 4.34E-08 6.51E-08 1.08E-07
68 4.68E-08 6.89E-08 1.11E-07
100 5.35E-08 7.55E-08 1.16E-07
150 6.68E-08 8.77E-08 1.26E-07
220 8.80E-08 1.08E-07 1.40E-07
330 1.24E-07 1.43E-07 1.71E-07
10 bits
470 1.69E-07 1.89E-07 2.13E-07
680 2.38E-07 2.60E-07 2.80E-07
1000 3.45E-07 3.66E-07 3.84E-07
1500 5.15E-07 5.35E-07 5.48E-07
2200 7.42E-07 7.75E-07 7.78E-07
3300 1.10E-06 1.14E-06 1.14E-06

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Table 84. Minimum sampling time vs RAIN (16-bit ADC)(1)(2) (continued)

Minimum sampling time (s)
Resolution RAIN (Ω)
Direct
Fast channels(4) Slow channels(5)
channels(3)

47 3.32E-08 5.10E-08 8.61E-08

68 3.59E-08 5.35E-08 8.83E-08
100 4.10E-08 5.83E-08 9.22E-08
150 5.06E-08 6.76E-08 9.95E-08
220 6.61E-08 8.22E-08 1.11E-07
330 9.17E-08 1.08E-07 1.32E-07
470 1.24E-07 1.40E-07 1.63E-07
680 1.74E-07 1.91E-07 2.12E-07
8 bits
1000 2.53E-07 2.70E-07 2.85E-07
1500 3.73E-07 3.93E-07 4.05E-07
2200 5.39E-07 5.67E-07 5.75E-07
3300 8.02E-07 8.36E-07 8.38E-07
4700 1.13E-06 1.18E-06 1.18E-06
6800 1.62E-06 1.69E-06 1.68E-06
10000 2.36E-06 2.47E-06 2.45E-06
15000 3.50E-06 3.69E-06 3.65E-06
1. Guaranteed by design.
2. Data valid at up to 130 °C, with a 47 pF PCB capacitor, and VDDA=1.6 V.
3. Direct channels are connected to analog I/Os (PA0_C, PA1_C, PC2_C and PC3_C) to optimize ADC performance.
4. Fast channels correspond to PA6, PB1, PC4, PF11, PF13 for ADCx_INPx, and to PA7, PB0, PC5, PF12, PF14 for
ADCx_INNx.
5. Slow channels correspond to all ADC inputs except for the Direct and Fast channels.

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Table 85. 16-bit ADC accuracy(1)(2)

Symbol Parameter Conditions(3) Min Typ Max Unit

Direct Single ended - +10/–20 -

channel Differential - ±15 -
Single ended - +10/–20 -
ET Total undadjusted error Fast channel
Differential - ±15 -

Slow Single ended - ±10 -

channel Differential ±10 -
EO Offset error - - ±10 -
EG Gain error - - ±15 -
LSB
Single ended - +3/–1 -
ED Differential linearity error
Differential - +4.5/–1 -

Direct Single ended - ±11 -

channel Differential - ±7 -
Single ended - ±13 -
EL Integral linearity error Fast channel
Differential - ±7 -

Slow Single ended - ±10 -

channel Differential - ±6 -
Single ended - 12.2 -
ENOB Effective number of bits Bits
Differential - 13.2 -

Signal-to-noise and Single ended - 75.2 -

SINAD
distortion ratio Differential - 81.2 -
Single ended - 77.0 -
SNR Signal-to-noise ratio dB
Differential - 81.0 -
Single ended - 87 -
THD Total harmonic distortion
Differential - 90 -
1. Guaranteed by characterization results for BGA packages. The values for LQFP packages might differ.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC clock frequency = 25 MHz, ADC resolution = 16 bits, VDDA=VREF+=3.3 V, BOOST=11 and 16-bit mode.

Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) does not
affect the ADC accuracy.

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240
Electrical characteristics STM32H730xB

Figure 45. ADC accuracy characteristics

VREF+ VDDA
[1LSB = (or )]
Output code 2n 2n
EG
(1) Example of an actual transfer curve
2n-1 (2) Ideal transfer curve
2n-2 (3) End-point correlation line
2n-3 (2)
n = ADC resolution
ET = total unadjusted error: maximum deviation
(3) between the actual and ideal transfer curves
ET
7 (1) EO = offset error: maximum deviation between the first
actual transition and the first ideal one
6
EL EG = gain error: deviation between the last ideal
5 EO
transition and the last actual one
4 ED = differential linearity error: maximum deviation
ED between actual steps and the ideal one
3
2 EL = integral linearity error: maximum deviation between
1 any actual transition and the end point correlation line
1 LSB ideal
0 VREF+ (VDDA)
(1/2n)*VREF+
(2/2n)*VREF+
(3/2n)*VREF+
(4/2n)*VREF+
(5/2n)*VREF+
(6/2n)*VREF+
(7/2n)*VREF+

(2n-3/2n)*VREF+
(2n-2/2n)*VREF+
(2n-1/2n)*VREF+
(2n/2n)*VREF+
VSSA

MSv19880V6

1. Example of an actual transfer curve.

2. Ideal transfer curve.
3. End point correlation line.
4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.

Figure 46. Typical connection diagram when using the ADC with FT/TT pins
featuring analog switch function

VDDA(4) VREF+(4)

I/O Sample-and-hold ADC converter

analog
RAIN(1) switch RADC
Converter

Cparasitic(2) Ilkg(3) CADC

VAIN Sampling
switch with
multiplexing

VSS VSS VSSA

MSv67871V3

1. Refer to Table 83: 16-bit ADC characteristics for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 54: I/O static characteristics). A high Cparasitic value downgrades
conversion accuracy. To remedy this, fADC should be reduced.
3. Refer to Table 54: I/O static characteristics for the value of Ilkg.
4. Refer to Figure 13: Power supply scheme.

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General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 47 or Figure 48,
depending on whether VREF+ is connected to VDDA or not. The 100 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.

Figure 47. Power supply and reference decoupling (VREF+ not connected to VDDA)

STM32

VREF+(1)

1 μF // 100 nF
VDDA

1 μF // 100 nF

VSSA/VREF-(1)

MSv50648V2

1. When VREF+ and VREF- inputs are not available, they are internally connected to VDDA and VSSA,
respectively.

Figure 48. Power supply and reference decoupling (VREF+ connected to VDDA)

STM32

VREF+/VDDA(1)

1 μF // 100 nF

VREF-/VSSA(1)

MSv50649V1

1. When VREF+ and VREF- inputs are not available, they are internally connected to VDDA and VSSA,
respectively.

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Electrical characteristics STM32H730xB

6.3.23 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 86, Table 87 and Table 88 are
derived from tests performed under the ambient temperature and VDDA supply voltage
conditions summarized in Table 12: General operating conditions. In Table 86, Table 87 and
Table 88, fADC refers to fadc_ker_ck.

Table 86. 12-bit ADC characteristics(1)(2)

Sym-
Parameter Conditions Min Typ Max Unit
bol

Analog
power
VDDA - 1.62 - 3.6
supply for
ADC ON

Positive
VREF+ V
(3) reference VDDA ≥ VREF+ 1.62 - VDDA
voltage

Negative
VREF- reference - VSSA - -
voltage

ADC clock
fADC 1,62 V ≤ VDDA ≤ 3.6 V 1.5 - 75 MHz
frequency

fADC = 75
Continuous 2.4 V ≤ VDDA ≤ 3.6 V - - 5
MHz
and
Discontinuous fADC = 60
mode(5) 1.6V ≤ VDDA≤ 3.6 V - - 4
MHz
Resolution SMP
–40 °C ≤ TJ ≤ 130 °C
= 12 bits = 2.5
fADC = 50
2.4 V ≤ VDDA ≤ 3.6 V - - 3.33
MHz(6)
Single mode
fADC = 38
1.6 V ≤ VDDA ≤ 3.6 V - - 2.53
MHz(6)

Continuous
and fADC = 75
1.6V ≤ VDDA ≤ 3.6V - - 5.77
Discontinuous MHz
mode(5)
Resolution SMP
–40 °C ≤ TJ ≤ 130 °C
= 10 bits fADC = 58 = 2.5
2.4 V ≤ VDDA ≤ 3.6 V - - 4.46
MHz(6)
Single mode
Sampling fADC = 42
1.6V ≤ VDDA ≤ 3.6V - - 3.23
rate for MHz(6)
fS(4) MSPS
Direct
channels Continuous
and fADC = 75
1.6V ≤ VDDA ≤ 3.6V - - 6.82
Discontinuous MHz
mode(5)
Resolution SMP
–40 °C ≤ TJ ≤ 130 °C
= 8 bits fADC = 67 = 2.5
2.4 V ≤ VDDA ≤ 3.6 V - - 6.09
MHz(6)
Single mode
fADC = 48
1.6V ≤ VDDA ≤ 3.6V - - 4.36
MHz(6)

Continuous
and fADC = 75
1.6V ≤ VDDA ≤ 3.6V - - 8.33
Discontinuous MHz
mode(5)
Resolution SMP
–40 °C ≤ TJ ≤ 130 °C
= 6 bits fADC = 75 = 2.5
2.4 V ≤ VDDA ≤ 3.6 V - - 8.33
MHz(6)
Single mode
fADC = 55
1.6V ≤ VDDA ≤ 3.6V - - 6.11
MHz(6)

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Table 86. 12-bit ADC characteristics(1)(2) (continued)

Sym-
Parameter Conditions Min Typ Max Unit
bol

fADC = 65
Continuous 2.4 V ≤ VDDA ≤ 3.6 V - - 4.33
MHz
and
Discontinuous
fADC = 58
mode(5) 1.6V ≤ VDDA ≤ 3.6V
MHz
- - 3.87
Resolution SMP
–40 °C ≤ TJ ≤ 130 °C
= 12 bits fADC = 32 = 2.5
2.4 V ≤ VDDA ≤ 3.6 V - - 2.13
MHz(6)
Single mode
fADC =
1.6V ≤ VDDA ≤ 3.6V - - 1.73
26 MHz(6)

Continuous
and fADC = 75
1.6V ≤ VDDA ≤ 3.6V - - 5.77
Discontinuous MHz
mode(5)
Resolution SMP
–40 °C ≤ TJ ≤ 130 °C
= 10 bits fADC = 36 = 2.5
2.4 V ≤ VDDA ≤ 3.6 V - - 2.77
MHz(6)
Single mode
Sampling fADC = 30
1.6V ≤ VDDA ≤ 3.6V - - 2.31
rate for fast MHz(6)
channels
(VIN[0:5]) Continuous
and fADC = 75
1.6V ≤ VDDA ≤ 3.6V - - 6.82
Discontinuous MHz
fS(4) mode(5)
Resolution SMP
(conti- –40 °C ≤ TJ ≤ 130 °C MSPS
= 8 bits fADC =44 = 2.5
nued) 2.4 V ≤ VDDA ≤ 3.6 V - - 4.00
MHz(6)
Single mode
fADC = 35
1.6V ≤ VDDA ≤ 3.6V - - 3.18
MHz(6)

Continuous
and fADC = 75
1.6V ≤ VDDA ≤ 3.6V - - 8.33
Discontinuous MHz
mode(5)
Resolution SMP
–40 °C ≤ TJ ≤ 130 °C
= 6 bits fADC = 56 = 2.5
2.4 V ≤ VDDA ≤ 3.6 V - - 6.22
MHz(6)
Single mode
fADC = 42
1.6V ≤ VDDA ≤ 3.6V - - 4.66
MHz(6)

Resolution
- - 1.00
= 12 bits

Resolution
Sampling - - 1.28
= 10 bits
fADC = 15 SMP
rate for slow - - –40 °C ≤ TJ ≤ 130 °C
Resolution MHz(6) = 2.5
channels - - 1.63
= 8 bits

Resolution
- - 2.08
= 6 bits

External
tTRIG trigger Resolution = 12 bits - - 15 1/fADC
period

Conversion
VAIN voltage - 0 - VREF+
range
V
Common VREF
VREF VREF/2
VCMIV mode input - /2−
/2 + 10%
voltage 10%

Resolution = 12 bits, TJ = 125 °C - - 220

External Resolution = 10 bits, TJ = 125 °C - - 2100

RAIN
(7) input Ω
impedance Resolution = 8 bits, TJ = 125 °C - - 12000

Resolution = 6 bits, TJ = 125 °C - - 80000

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 Electrical characteristics STM32H730xB

Table 86. 12-bit ADC characteristics(1)(2) (continued)

Sym-
Parameter Conditions Min Typ Max Unit
bol

Internal
sample and
CADC - - 5 - pF
hold
capacitor

tADCV
ADC LDO
REG_ - - 5 10 µs
startup time
STUP

con-
ADC power-
tSTAB LDO already started 1 - - version
up time
cycle

Offset
tOFF_
calibration - 135 - -
CAL time

Trigger CKMODE = 00 1.5 2 2.5

conversion
latency for CKMODE = 01 - - 2.5
regular and
tLATR injected CKMODE = 10 - - 2.5
channels
without
aborting the CKMODE = 11 - - 2.25
conversion

Trigger CKMODE = 00 2.5 3 3.5

conversion
latency for CKMODE = 01 - - 3.5
1/fADC
regular and
tLATR injected CKMODE = 10 - - 3.5
INJ channels
when a
regular CKMODE = 11 - - 3.25
conversion
is aborted

Sampling
tS - 2.5 - 640.5
time

Total
conversion
tS +
time
tCONV N-bits resolution 0.5 + - -
(including
N
sampling
time)

ADC fS= 5 MSPS - 430 -

consumption
IDDA_ on VDDA and fS = 1 MSPS - 133 -
D(ADC) VREF,
Differential fS = 0.1 MSPS - 51 -
mode
µA
ADC fS= 5 MSPS - 350 -
consumption
IDDA_ fS = 1 MSPS - 122 -
on VDDA and
SE VREF,
(ADC) Single- fS = 0.1 MSPS - 47 -
ended mode

ADC
IDD consumption µA/
- - 2.4 -
(ADC) on VDD per MHz
fADC

1. Guaranteed by design.
2. The voltage booster on ADC switches must be used for VDDA < 2.4 V (embedded I/O switches).
3. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA.
4. Guaranteed by characterization for BGA and CSP packages. The values for LQFP packages may be different.
5. The conversion of the first element in the group is excluded.

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6. fADC value corresponds to the maximum frequency that can be reached considering a 2.5 sampling period. For other SMPy sampling periods,
the maximum frequency is fADC value * SMPy / 2.5 with a limitation to 75 MHz.
7. The tolerance is 2 LSBs for 12-bit, 10-bit and 8-bit resolutions. It is otherwise specified.

Table 87. Minimum sampling time vs RAIN (12-bit ADC)(1)(2)

Minimum sampling time (s)
Resolution RAIN (Ω)
Direct channels(3) Fast channels(4) Slow channels(5)

47 5.55E-08 7.04E-08 1.03E-07

68 5.76E-08 7.22E-08 1.05E-07
100 6.17E-08 7.65E-08 1.07E-07
150 7.02E-08 8.45E-08 1.13E-07
12 bits
220 8.59E-08 1.00E-07 1.22E-07
330 1.11E-07 1.26E-07 1.41E-07
470 1.46E-07 1.61E-07 1.69E-07
680 1.98E-07 2.17E-07 2.25E-07
47 4.90E-08 6.06E-08 8.77E-08
68 5.07E-08 6.27E-08 8.95E-08
100 5.41E-08 6.67E-08 9.22E-08
150 6.18E-08 7.50E-08 9.59E-08
220 7.51E-08 8.70E-08 1.04E-07
330 9.46E-08 1.07E-07 1.17E-07
10 bits
470 1.22E-07 1.34E-07 1.42E-07
680 1.63E-07 1.77E-07 1.86E-07
1000 2.27E-07 2.42E-07 2.43E-07
1500 3.27E-07 3.40E-07 3.35E-07
2200 4.53E-07 4.86E-07 4.73E-07
3300 6.56E-07 6.93E-07 6.72E-07

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Table 87. Minimum sampling time vs RAIN (12-bit ADC)(1)(2) (continued)

Minimum sampling time (s)
Resolution RAIN (Ω)
Direct channels(3) Fast channels(4) Slow channels(5)

47 4.35E-08 5.31E-08 7.36E-08

68 4.47E-08 5.48E-08 7.47E-08
100 4.72E-08 5.79E-08 7.63E-08
150 5.33E-08 6.35E-08 7.88E-08
220 6.26E-08 7.26E-08 8.47E-08
330 7.84E-08 8.80E-08 9.48E-08
470 9.80E-08 1.07E-07 1.14E-07
680 1.28E-07 1.39E-07 1.43E-07
8 bits
1000 1.76E-07 1.88E-07 1.90E-07
1500 2.49E-07 2.66E-07 2.64E-07
2200 3.50E-07 3.63E-07 3.63E-07
3300 5.09E-07 5.27E-07 5.24E-07
4700 7.00E-07 7.28E-07 7.09E-07
6800 9.84E-07 1.03E-06 1.00E-06
10000 1.43E-06 1.48E-06 1.44E-06
15000 2.10E-06 2.18E-06 2.11E-06
47 3.79E-08 4.58E-08 5.74E-08
68 3.88E-08 4.69E-08 5.81E-08
100 4.09E-08 4.89E-08 5.93E-08
150 4.48E-08 5.25E-08 6.14E-08
220 5.07E-08 5.81E-08 6.58E-08
330 6.04E-08 6.79E-08 7.46E-08
470 7.37E-08 8.10E-08 8.60E-08
680 9.31E-08 1.01E-07 1.04E-07
6 bits
1000 1.23E-07 1.32E-07 1.34E-07
1500 1.71E-07 1.82E-07 1.82E-07
2200 2.39E-07 2.50E-07 2.49E-07
3300 3.43E-07 3.57E-07 3.49E-07
4700 4.72E-07 4.92E-07 4.81E-07
6800 6.65E-07 6.89E-07 6.68E-07
10000 9.54E-07 9.88E-07 9.54E-07
15000 1.40E-06 1.45E-06 1.39E-06
1. Guaranteed by design.
2. Data valid up to 130 °C, with a 22 pF PCB capacitor and VDDA = 1.62 V.

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3. Direct channels are connected to analog I/Os (PA0_C, PA1_C, PC2_C and PC3_C) to optimize ADC performance.
4. Fast channels correspond to ADCx_INx[0:5].
5. Slow channels correspond to all ADC inputs except for the Direct and Fast channels.

Table 88. 12-bit ADC accuracy(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

Single
- 3.5 5
Direct channel ended
Differential - 2.5 3

Total Single
- 3.5 5
ET unadjusted Fast channel ended
error Differential - 2.5 3
Single
- 3.5 5
Slow channel ended
Differential - 2.5 3
EO Offset error - - +/-2 +/-5
TBD
EG Gain error - - (3) -

+/- +1.5/- ±LSB

Differential Single ended -
0.75 1
ED linearity
error +1.25
Differential - +/-0.5
/-1
Single
- +/-1 +/-2.5
Direct channel ended
Differential - +/-1 +/-2

Integral Single
- +/-1 +/-2.5
EL linearity Fast channel ended
error Differential - +/-1 +/-2
Single
- +/-1 +/-2.5
Slow channel ended
Differential - +/-1 +/-2
Effective Single ended - 11.2 -
ENOB number of bits
bits Differential - 11.5 -

Signal-to- Single ended - 68.9 -

noise and
SINAD
distortion Differential - 71.1 -
ratio

Signal-to- Single ended - 69.1 - dB

SNR
noise ratio Differential - 71.4 -
Total Single ended - -79.6 -
THD harmonic
distortion Differential - -81.8 -

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1. Guaranteed by characterization for BGA packages. The maximum values are preliminary data. The values for LQFP
packages may be different.
2. ADC DC accuracy values are measured after internal calibration in Continuous and Discontinuous mode.
3. TBD stands for “to be defined”.

6.3.24 DAC characteristics

Table 89. DAC characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VDDA Analog supply voltage - 1.8 3.3 3.6

VREF+ Positive reference voltage - 1.80 - VDDA
V
Negative reference
VREF- - - VSSA -
voltage
connected
5 - -
DAC output buffer to VSSA
RL Resistive Load
ON connected kΩ
25 - -
to VDDA
RO Output Impedance DAC output buffer OFF 10.3 13 16
Output impedance VDD = 2.7 V - - 1.6
DAC output buffer
RBON sample and hold mode, kΩ
ON VDD = 2.0 V - - 2.6
output buffer ON
Output impedance VDD = 2.7 V - - 17.8
DAC output buffer
RBOFF sample and hold mode, kΩ
OFF VDD = 2.0 V - - 18.7
output buffer OFF
CL DAC output buffer OFF - - 50 pF
Capacitive Load
CSH Sample and Hold mode - 0.1 1 µF
VDDA
Voltage on DAC_OUT DAC output buffer ON 0.2 -
VDAC_OUT −0.2 V
output
DAC output buffer OFF 0 - VREF+
±0.5 LSB - 2.05 3
Settling time (full scale:
for a 12-bit code transition Normal mode, DAC ±1 LSB - 1.97 2.87
between the lowest and output buffer ON,
±2 LSB - 1.67 2.84
the highest input codes CL ≤ 50 pF,
tSETTLING RL ≥ 5 ㏀ ±4 LSB - 1.66 2.78 µs
when DAC_OUT reaches
the final value of ±0.5LSB, ±8 LSB - 1.65 2.7
±1LSB, ±2LSB, ±4LSB,
±8LSB) Normal mode, DAC output buffer
- 1.7 2
OFF, ±1LSB CL=10 pF
Wakeup time from off Normal mode, DAC output buffer
- 5 7.5
state (setting the ENx bit ON, CL ≤ 50 pF, RL = 5 ㏀
tWAKEUP(2) in the DAC Control µs
register) until the final Normal mode, DAC output buffer
2 5
value of ±1LSB is reached OFF, CL ≤ 10 pF

DC VDDA supply rejection Normal mode, DAC output buffer

PSRR - −80 −28 dB
ratio ON, CL ≤ 50 pF, RL = 5 ㏀

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Table 89. DAC characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Sampling time in Sample MODE<2:0>_V12=100/101

- 0.7 2.6
and Hold mode (BUFFER ON)
CL=100 nF ms
MODE<2:0>_V12=110
(code transition between - 11.5 18.7
tSAMP (BUFFER OFF)
the lowest input code and
the highest input code MODE<2:0>_V12=111
when DAC_OUT reaches - 0.3 0.6 µs
(INTERNAL BUFFER OFF)
the ±1LSB final value)
(3)
Ileak Output leakage current - nA
Internal sample and hold
CIint - 1.8 2.2 2.6 pF
capacitor
Middle code offset trim Minimum time to verify the each
tTRIM 50 - - µs
time code

Middle code offset for 1 VREF+ = 3.6 V - 850 -

Voffset µV
trim code step VREF+ = 1.8 V - 425 -
No load,
middle code - 360 -
DAC output buffer (0x800)
ON No load,
worst code - 490 -
(0xF1C)
DAC quiescent
IDDA(DAC) No load,
consumption from VDDA
DAC output buffer middle/
- 20 -
OFF worst code
(0x800)
360*TON/
Sample and Hold mode,
- (TON+TOFF) -
CSH=100 nF (4)

No load,
middle code - 170 - µA
DAC output buffer (0x800)
ON No load,
worst code - 170 -
(0xF1C)
No load,
DAC consumption from DAC output buffer middle/
IDDV(DAC) - 160 -
VREF+ OFF worst code
(0x800)
170*TON/
Sample and Hold mode, Buffer
- (TON+TOFF) -
ON, CSH=100 nF (worst code) (4)

160*TON/
Sample and Hold mode, Buffer
- (TON+TOFF) -
OFF, CSH=100 nF (worst code) (4)

1. Guaranteed by design unless otherwise specified.

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2. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).
3. Refer to Table 54: I/O static characteristics.
4. TON is the refresh phase duration, while TOFF is the hold phase duration. Refer to the product reference manual for more
details.

Table 90. DAC accuracy(1)

Symbol Parameter Conditions Min Typ Max Unit

Differential non DAC output buffer ON −2 - 2

DNL LSB
linearity(2) DAC output buffer OFF −2 - 2
- Monotonicity 10 bits - - - -
DAC output buffer ON, CL ≤ 50 pF,
−4 - 4
RL ≥ 5 ㏀
INL Integral non linearity(3) LSB
DAC output buffer OFF,
−4 - 4
CL ≤ 50 pF, no RL
DAC output VREF+ = 3.6 V - - ±12
buffer ON,
Offset error at code CL ≤ 50 pF, VREF+ = 1.8 V - - ±25
Offset RL ≥ 5 ㏀ LSB
0x800 (3)
DAC output buffer OFF,
- - ±8
CL ≤ 50 pF, no RL
Offset error at code DAC output buffer OFF,
Offset1 - - ±5 LSB
0x001(4) CL ≤ 50 pF, no RL
DAC output VREF+ = 3.6 V - - ±5
Offset error at code buffer ON,
OffsetCal 0x800 after factory LSB
CL ≤ 50 pF, VREF+ = 1.8 V - - ±7
calibration
RL ≥ 5 ㏀
DAC output buffer ON,CL ≤ 50 pF,
- - ±1
RL ≥ 5 ㏀
Gain Gain error(5) %
DAC output buffer OFF,
- - ±1
CL ≤ 50 pF, no RL
DAC output buffer ON, CL ≤ 50 pF,
- - ±30
RL ≥ 5 ㏀
TUE Total unadjusted error
DAC output buffer OFF, CL ≤
±12 LSB
50 pF, no RL
Total unadjusted error DAC output buffer ON, CL ≤ 50 pF,
TUECal - - ±23
after calibration RL ≥ 5 ㏀
DAC output buffer ON,CL ≤ 50 pF,
- 67.8 -
RL ≥ 5 ㏀ , 1 kHz, BW = 500 KHz
SNR Signal-to-noise ratio(6) DAC output buffer OFF, dB
CL ≤ 50 pF, no RL,1 kHz, BW = - 67.8 -
500 KHz

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Table 90. DAC accuracy(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit
DAC output buffer ON, CL ≤ 50 pF,
- −78.6 -
Total harmonic RL ≥ 5 ㏀ , 1 kHz
THD dB
distortion(6) DAC output buffer OFF,
- −78.6 -
CL ≤ 50 pF, no RL, 1 kHz
DAC output buffer ON, CL ≤ 50 pF,
- 67.5 -
Signal-to-noise and RL ≥ 5 ㏀ , 1 kHz
SINAD dB
distortion ratio(6) DAC output buffer OFF,
- 67.5 -
CL ≤ 50 pF, no RL, 1 kHz
DAC output buffer ON,
- 10.9 -
Effective number of CL ≤ 50 pF, RL ≥ 5 ㏀ , 1 kHz
ENOB bits
bits DAC output buffer OFF,
- 10.9 -
CL ≤ 50 pF, no RL, 1 kHz
1. Guaranteed by characterization results.
2. Difference between two consecutive codes minus 1 LSB.
3. Difference between the value measured at Code i and the value measured at Code i on a line drawn between Code 0 and
last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF
when the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON.
6. Signal is −0.5dBFS with Fsampling=1 MHz.

Figure 49. 12-bit buffered /non-buffered DAC

Buffered/Non-buffered DAC

Buffer(1)
RL

12-bit DAC_OUTx
digital to
analog
converter
CL

ai17157V3

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.

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6.3.25 Voltage reference buffer characteristics

Table 91. VREFBUF characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit
VSCALE = 000 2.8 3.3 3.6

Normal mode, VSCALE = 001 2.4 - 3.6

VDDA = 3.3 V VSCALE = 010 2.1 - 3.6
VSCALE = 011 1.8 - 3.6
VDDA Analog supply voltage
VSCALE = 000 1.62 - 2.80
VSCALE = 001 1.62 - 2.40
Degraded mode(2)
VSCALE = 010 1.62 - 2.10
VSCALE = 011 1.62 - 1.80
VSCALE = 000 2.4980 2.5000 2.5035
VSCALE = 001 2.0460 2.0490 2.0520 V
Normal mode at 30 °C,
Iload = 100 µA VSCALE = 010 1.8010 1.8040 1.8060
VSCALE = 011 1.4995 1.5015 1.5040

Voltage Reference VDDA−

VREFBUF VSCALE = 000 - VDDA
Buffer Output, at 30 °C, 150 mV
_OUT Iload= 100 µA VDDA−
VSCALE = 001 - VDDA
150 mV
Degraded mode(2)
VDDA−
VSCALE = 010 - VDDA
150 mV
VDDA−
VSCALE = 011 - VDDA
150 mV
TRIM Trim step resolution - - - ±0.05 ±0.1 %
CL Load capacitor - - 0.5 1 1.50 µF
Equivalent Serial
esr
Resistor of CL
- - - - 2 Ω

ILOAD Static load current - - - - 4 mA

Iload = 500 µA - 200 -
Iline_reg Line regulation 2.8 V ≤ VDDA ≤ 3.6 V ppm/V
Iload = 4 mA - 100 -
ppm/
Iload_reg Load regulation 500 µA ≤ ILOAD ≤ 4 mA Normal mode - 50 -
mA
Tcoeff
ppm/
Tcoeff Temperature coefficient −40 °C < TJ < +130 °C - - VREFINT
°C
+ 100
DC - - 60 -
PSRR Power supply rejection dB
100KHz - - 40 -

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Table 91. VREFBUF characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit
CL=0.5 µF - - 300 -
tSTART Start-up time CL=1 µF - - 500 - µs
CL=1.5 µF - - 650 -
Control of maximum
DC current drive on
IINRUSH - - 8 - mA
VREFBUF_OUT during
startup phase(3)
ILOAD = 0 µA - - 15 25
VREFBUF
IDDA
consumption from ILOAD = 500 µA - - 16 30 µA
(VREFBUF) VDDA
ILOAD = 4 mA - - 32 50
1. Guaranteed by design, unless otherwise specified.
2. In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (VDDA−drop voltage).
3. To properly control VREFBUF IINRUSH current during the startup phase and the change of scaling, VDDA voltage should be in
the range of 1.8 V-3.6 V, 2.1 V-3.6 V, 2.4 V-3.6 V and 2.8 V-3.6 V for VSCALE = 011, 010, 001 and 000, respectively.

6.3.26 Analog temperature sensor characteristics

Table 92. Temperature sensor characteristics

Symbol Parameter Min Typ Max Unit

TL(1) VSENSE linearity with temperature - - ±3 °C

(2)
Avg_Slope Average slope - 2 - mV/°C
V30(3) Voltage at 30°C ± 5 °C - 0.62 - V
tstart_run Startup time in Run mode (buffer startup) - - 25.2
µs
(1)
tS_temp ADC sampling time when reading the temperature 9 - -
Isens(1) Sensor consumption - 0.18 0.31
µA
Isensbuf(1) Sensor buffer consumption - 3.8 6.5
1. Guaranteed by design.
2. Guaranteed by characterization results.
3. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1
byte.

Table 93. Temperature sensor calibration values

Symbol Parameter Memory address

Temperature sensor raw data acquired value at

TS_CAL1 0x1FF1 E820 -0x1FF1 E821
30 °C, VDDA=3.3 V
Temperature sensor raw data acquired value at
TS_CAL2 0x1FF1 E840 - 0x1FF1 E841
130 °C, VDDA=3.3 V

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6.3.27 Digital temperature sensor characteristics

Table 94. Digital temperature sensor characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fDTS(2) Output Clock frequency - 500 750 1150 kHz

Hz/°
TLC(2) Temperature linearity coefficient VOS2 1660 2100 2750
C
TJ = −40°C to
−13 - 4
TTOTAL_ERROR Temperature offset 30°C
(2) °C
measurement, all VOS TJ = 30°C to
−7 - 2
Tjmax
VOS2 0 - 0
Additional error due to supply
TVDD_CORE VOS0, VOS1, °C
variation −1 - 1
VOS3
tTRIM Calibration time - - - 2 ms
Wake-up time from off state until
tWAKE_UP - - 67 116.00 μs
DTS ready bit is set
DTS consumption on
IDDCORE_DTS - 8.5 30 70.0 μA
VDD_CORE
1. Guaranteed by design, unless otherwise specified.
2. Guaranteed by characterization results.

6.3.28 Temperature and VBAT monitoring

Table 95. VBAT monitoring characteristics

Symbol Parameter Min Typ Max Unit

R Resistor bridge for VBAT - 26 - KΩ

Q Ratio on VBAT measurement - 4 - -
(1)
Er Error on Q –10 - +10 %
tS_vbat(1) ADC sampling time when reading VBAT input 9 - - µs
VBAThigh High supply monitoring - 3.55 -
V
VBATlow Low supply monitoring - 1.36 -
1. Guaranteed by design.

Table 96. VBAT charging characteristics

Symbol Parameter Condition Min Typ Max Unit

VBRS in PWR_CR3= 0 - 5 -
RBC Battery charging resistor KΩ
VBRS in PWR_CR3= 1 1.5 -

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Table 97. Temperature monitoring characteristics

Symbol Parameter Min Typ Max Unit

TEMPhigh High temperature monitoring - 117 -

°C
TEMPlow Low temperature monitoring - –25 -

6.3.29 Voltage booster for analog switch

Table 98. Voltage booster for analog switch characteristics(1)

Symbol Parameter Condition Min Typ Max Unit

VDD Supply voltage - 1.62 2.6 3.6 V

tSU(BOOST) Booster startup time - - - 50 µs
1.62 V ≤ VDD ≤ 2.7 V - - 125
IDD(BOOST) Booster consumption µA
2.7 V < VDD < 3.6 V - - 250
1. Guaranteed by characterization results.

6.3.30 Comparator characteristics

Table 99. COMP characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VDDA Analog supply voltage - 1.62 3.3 3.6

Comparator input voltage
VIN - 0 - VDDA V
range
(2)
VBG Scaler input voltage -
VSC Scaler offset voltage - - ±5 ±10 mV

Scaler static consumption BRG_EN=0 (bridge disable) - 0.2 0.3

IDDA(SCALER) µA
from VDDA BRG_EN=1 (bridge enable) - 0.8 1
tSTART_SCALER Scaler startup time - - 140 250 µs
High-speed mode - 2 5
Comparator startup time to
tSTART reach propagation delay Medium mode - 5 20 µs
specification
Ultra-low-power mode - 15 80
High-speed mode - 50 80 ns
Propagation delay for
200 mV step with 100 mV Medium mode - 0.5 0.9
overdrive µs
Ultra-low-power mode - 2.5 7
(3)
tD
Propagation delay for step High-speed mode - 50 120 ns
> 200 mV with 100 mV
Medium mode - 0.5 1.2
overdrive only on positive µs
inputs Ultra-low-power mode - 2.5 7
Voffset Comparator offset error Full common mode range - ±5 ±20 mV

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Table 99. COMP characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

No hysteresis - 0 -
Low hysteresis 4 10 22
Vhys Comparator hysteresis mV
Medium hysteresis 8 20 37
High hysteresis 16 30 52
Static - 400 600
Ultra-low- With 50 kHz nA
power mode ±100 mV overdrive - 800 -
square signal
Static - 5 7
Comparator consumption
IDDA(COMP) Medium mode With 50 kHz
from VDDA ±100 mV overdrive - 6 -
square signal
µA
Static - 70 100
High-speed With 50 kHz
mode ±100 mV overdrive - 75 -
square signal
1. Guaranteed by design, unless otherwise specified.
2. Refer to Table 20: Embedded reference voltage.
3. Guaranteed by characterization results.

6.3.31 Operational amplifier characteristics

Table 100. Operational amplifier characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Analog supply voltage

VDDA - 2 3.3 3.6
Range
V
Common Mode Input
CMIR - 0 - VDDA
Range
25°C, no load on output - - ±1.5
VIOFFSET Input offset voltage All voltages and mV
- - ±2.5
temperature, no load
ΔVIOFFSET Input offset voltage drift - - ±3.0 - μV/°C
Offset trim step at low
TRIMOFFSETP
common input voltage - - 1.1 1.5
TRIMLPOFFSETP (0.1*VDDA)
mV
Offset trim step at high
TRIMOFFSETN
common input voltage - - 1.1 1.5
TRIMLPOFFSETN (0.9*VDDA)
ILOAD Drive current - - - 500
μA
ILOAD_PGA Drive current in PGA mode - - - 270

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Table 100. Operational amplifier characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

CLOAD Capacitive load - - - 50 pF

Common mode rejection
CMRR - - 80 - dB
ratio
CLOAD ≤ 50pf /
Power supply rejection
PSRR RLOAD ≥ 4 kΩ(2) at 1 kHz, 50 66 - dB
ratio
Vcom=VDDA/2
Gain bandwidth for high 200 mV ≤ Output dynamic
GBW 4 7.3 12.3 MHz
supply range range ≤ VDDA - 200 mV

Slew rate (from 10% and Normal mode - 3 -

SR V/µs
90% of output voltage) High-speed mode - 24 -
200 mV ≤ Output dynamic
AO Open loop gain 59 90 129 dB
range ≤ VDDA - 200 mV
φm Phase margin - - 55 - °
GM Gain margin - - 12 - dB
Iload=max or RLOAD=min, VDDA
VOHSAT High saturation voltage - -
Input at VDDA −100 mV
mV
Iload=max or RLOAD=min,
VOLSAT Low saturation voltage - - 100
Input at 0 V
CLOAD ≤ 50pf,
Normal RLOAD ≥ 4 kΩ,
- 0.8 3.2
mode follower
Wake up time from OFF configuration
tWAKEUP µs
state CLOAD ≤ 50pf,
High
RLOAD ≥ 4 kΩ,
speed - 0.9 2.8
follower
mode
configuration
PGA gain = 2 −1 - 1

Non inverting gain error PGA gain = 4 −2 - 2

value PGA gain = 8 −2.5 - 2.5
PGA gain = 16 −3 - 3
PGA gain = 2 −1 - 1
PGA gain = 4 −1 - 1
PGA gain Inverting gain error value %
PGA gain = 8 −2 - 2
PGA gain = 16 −3 - 3
PGA gain = 2 −1 - 1

External non-inverting gain PGA gain = 4 −3 - 3

error value PGA gain = 8 −3.5 - 3.5
PGA gain = 16 −4 - 4

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Table 100. Operational amplifier characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

PGA Gain=2 - 10/10 -

R2/R1 internal resistance PGA Gain=4 - 30/10 -
values in non-inverting
PGA mode(3) PGA Gain=8 - 70/10 -
PGA Gain=16 - 150/10 - kΩ/
Rnetwork
PGA Gain = -1 - 10/10 - kΩ
R2/R1 internal resistance PGA Gain = -3 - 30/10 -
values in inverting PGA
mode(3) PGA Gain = -7 - 70/10 -
PGA Gain = -15 - 150/10 -
Resistance variation (R1
Delta R - −15 - 15 %
or R2)
Gain=2 - GBW/2 -

PGA bandwidth for Gain=4 - GBW/4 -

MHz
different non inverting gain Gain=8 - GBW/8 -
Gain=16 - GBW/16 -
PGA BW
Gain = -1 - 5.00 -

PGA bandwidth for Gain = -3 - 3.00 -

MHz
different inverting gain Gain = -7 - 1.50 -
Gain = -15 - 0.80 -
at
- 140 -
1 KHz output loaded nV/√
en Voltage noise density
at with 4 kΩ Hz
- 55 -
10 KHz
Normal
- 570 1000
mode no Load,
OPAMP consumption from
IDDA(OPAMP) High- quiescent mode, µA
VDDA
speed follower - 610 1200
mode
1. Guaranteed by design, unless otherwise specified.
2. RLOAD is the resistive load connected to VSSA or to VDDA.
3. R2 is the internal resistance between the OPAMP output and th OPAMP inverting input. R1 is the internal resistance
between the OPAMP inverting input and ground. PGA gain = 1 + R2/R1.

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6.3.32 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics

Unless otherwise specified, the parameters given in Table 101 for DFSDM are derived from
tests performed under the ambient temperature, fPCLKx frequency and supply voltage
conditions summarized in Table 12: General operating conditions.
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load CL = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD
• VOS level set to VOS0
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (DìFSDM_CKINx, DFSDM_DATINx, DFSDM_CKOUT for DFSDM).

Table 101. DFSDM measured timing

Symbol Parameter Conditions Min Typ Max Unit

DFSDM
fDFSDMCLK 1.62 < VDD < 3.6 V - - fSYSCLK
clock
SPI mode
(SITP[1:0] = 0,1),
- - 20
External clock mode
fCKIN Input clock (SPICKSEL[1:0] = 0)
MHz
(1/TCKIN) frequency SPI mode
(SITP[1:0] = 0,1),
- - 20
Internal clock mode
(SPICKSEL[1:0] # 0)
Output clock
fCKOUT 1.62 < VDD < 3.6 V - - 20
frequency
Even
division,
45 50 55
CKOUTDIV
Output clock = n, 1, 3, 5..
1.62 < VDD
DuCyCKOUT frequency %
< 3.6 V Odd
duty cycle
division, (((n/2+1)/(n+1)) (((n/2+1)/(n+1)) (((n/2+1)/(n+1))
CKOUTDIV *100)−5 *100) *100)+5
= n, 2, 4, 6..

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Table 101. DFSDM measured timing (continued)

Symbol Parameter Conditions Min Typ Max Unit

SPI mode
Input clock
twh(CKIN) (SITP[1:0] = 0,1),
high and low TCKIN/2−0.5 TCKIN/2 -
twl(CKIN) External clock mode
time
(SPICKSEL[1:0] = 0)
SPI mode
Data input (SITP[1:0] = 0,1),
tsu 2 - -
setup time External clock mode
(SPICKSEL[1:0] = 0)
ns
SPI mode
Data input (SITP[1:0] = 0,1),
th 1 - -
hold time External clock mode
(SPICKSEL[1:0] = 0)
Manchester Manchester mode
data period (SITP[1:0] = 2,3), (CKOUTDIV+1) (2*CKOUTDIV)
TManchester -
(recovered Internal clock mode * TDFSDMCLK * TDFSDMCLK
clock period) (SPICKSEL[1:0] # 0)

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STM32H730xB Electrical characteristics

Figure 50. Channel transceiver timing diagrams

DFSDM_CKINy
(SPICKSEL=0)
SPI timing : SPICKSEL = 0

twl twh tr tf
tsu th
DFSDM_DATINy

SITP = 00

tsu th

SITP = 01

SPICKSEL=3
DFSDM_CKOUT

SPICKSEL=2
SPI timing : SPICKSEL = 1, 2, 3

SPICKSEL=1

twl twh tr tf
tsu th
DFSDM_DATINy

SITP = 0

tsu th

SITP = 1

SITP = 2
DFSDM_DATINy
Manchester timing

SITP = 3

recovered clock

recovered data 0 0 1 1 0
MS30766V2

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6.3.33 Camera interface (DCMI) timing specifications

Unless otherwise specified, the parameters given in Table 102 for DCMI are derived from
tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage
summarized in Table 12: General operating conditions, with the following configuration:
• DCMI_PIXCLK polarity: falling
• DCMI_VSYNC and DCMI_HSYNC polarity: high
• Data formats: 14 bits
• Capacitive load CL=30 pF
• Measurement points are done at CMOS levels: 0.5VDD
• VOS level set to VOS0

Table 102. DCMI characteristics(1)

Symbol Parameter Min Max Unit

- Frequency ratio DCMI_PIXCLK/fHCLK - 0.4 -

DCMI_PIXCLK Pixel Clock input - 110 MHz
Dpixel Pixel Clock input duty cycle 30 70 %
tsu(DATA) Data input setup time 2 -
th(DATA) Data hold time 1 -
tsu(HSYNC), ns
DCMI_HSYNC/ DCMI_VSYNC input setup time 2 -
tsu(VSYNC)
th(HSYNC),
DCMI_HSYNC/ DCMI_VSYNC input hold time 1 -
th(VSYNC)
1. Guaranteed by characterization results.

Figure 51. DCMI timing diagram

1/DCMI_PIXCLK

DCMI_PIXCLK

tsu(HSYNC) th(HSYNC)

DCMI_HSYNC

tsu(VSYNC) th(HSYNC)

DCMI_VSYNC
tsu(DATA) th(DATA)

DATA[0:13]

MS32414V2

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6.3.34 Parallel synchronous slave interface (PSSI) characteristics

Unless otherwise specified, the parameters given in Table 103 and Table 104 for PSSI are
derived from tests performed under the ambient temperature, fHCLK frequency and VDD
supply voltage summarized in Table 12: General operating conditions.

Table 103. PSSI transmit characteristics(1)

Symbol Parameter Min Max Unit

Frequency ratio
- - 0.4 -
PSSI_PDCK/fHCLK
- 50
PSSI_PDCK PSSI Clock input MHz
- 35(2)
Dpixel PSSI Clock input duty cycle 30 70 %
tov(DATA) Data output valid time - 10
- - - 14(2)
toh(DATA) Data output hold time 4.5 -
tov((DE) DE output valid time - 10 ns
toh(DE) DE output hold time 4 -
tsu(RDY) RDY input setup time 0 -
th(RDY) RDY input hold time 0 -
1. Guaranteed by characterization results.
2. This value is obtained by using PA9, PA10 or PH4 I/O.

Table 104. PSSI receive characteristics(1)

Symbol Parameter Min Max Unit

Frequency ratio
- - 0.4 -
PSSI_PDCK/fHCLK
PSSI_PDCK PSSI Clock input - 110 MHz
Dpixel PSSI Clock input duty cycle 30 70 %
tsu(DATA) Data input setup time 1.5 -
th(DATA) Data input hold time 0.5 -
tsu((DE) DE input setup time 2 -
ns
th(DE) DE input hold time 1 -
tov(RDY) RDY output valid time - 15
toh(RDY) RDY output hold time 5.5 -
1. Guaranteed by characterization results.

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6.3.35 LCD-TFT controller (LTDC) characteristics

Unless otherwise specified, the parameters given in Table 105 for LCD-TFT are derived
from tests performed under the ambient temperature, fHCLK frequency and VDD supply
voltage summarized in Table 12: General operating conditions, with the following
configuration:
• LCD_CLK polarity: high
• LCD_DE polarity: low
• LCD_VSYNC and LCD_HSYNC polarity: high
• Pixel formats: 24 bits
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load CL=30 pF
• Measurement points are done at CMOS levels: 0.5VDD
• IO Compensation cell activated.
• HSLV activated when VDD ≤ 2.7 V
• VOS level set to VOS0

Table 105. LTDC characteristics(1)

Symbol Parameter Min Max Unit

2.7<VDD<3.6 V, 20 pF 150
LTDC clock
fCLK output 2.7<VDD<3.6 V - 133 MHz
frequency
1.62<VDD<3.6 V 90/76.5(2)
DCLK LTDC clock output duty cycle 45 55 %
tw(CLKH),
Clock High time, low time tw(CLK)//2−0.5 tw(CLK)/2+0.5
tw(CLKL)
2.7<VDD<3.6 V 2.0
tv(DATA) Data output valid time -
1.62<VDD<3.6 V 2.5/6.5(2)
th(DATA) Data output hold time 0 -
ns
tv(HSYNC), 2.7<VDD<3.6 V - 1.5
HSYNC/VSYNC/DE output
tv(VSYNC),
valid time 1.62<VDD<3.6 V - 2.0
tv(DE)
th(HSYNC),
th(VSYNC), HSYNC/VSYNC/DE output hold time 0 -
th(DE)
1. Guaranteed by characterization results.
2. This value is valid when PA[9], PA[10], PA[11], PA[12], PA[15], PB[11], PH[4], PJ[8], PJ[9], PJ[10], PJ[11], PK[0], PK[1] or
PK[2] is used.

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Figure 52. LCD-TFT horizontal timing diagram

tCLK

LCD_CLK

LCD_VSYNC

tv(HSYNC) tv(HSYNC)

LCD_HSYNC
tv(DE) th(DE)

LCD_DE
tv(DATA)
LCD_R[0:7]
LCD_G[0:7] Pixel Pixel Pixel
1 2 N
LCD_B[0:7]
th(DATA)

HSYNC Horizontal Active width Horizontal

width back porch back porch

One line
MS32749V1

Figure 53. LCD-TFT vertical timing diagram

tCLK

LCD_CLK

tv(VSYNC) tv(VSYNC)

LCD_VSYNC

LCD_R[0:7]
LCD_G[0:7] M lines data
LCD_B[0:7]

VSYNC Vertical Active width Vertical

width back porch back porch

One frame
MS32750V1

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6.3.36 Timer characteristics

The parameters given in Table 106 are guaranteed by design.
Refer to Section 6.3.17: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).

Table 106. TIMx characteristics(1)(2)

Symbol Parameter Conditions(3) Min Max Unit

AHB/APBx prescaler=1
or 2 or 4, fTIMxCLK = 1 - tTIMxCLK
275 MHz
tres(TIM) Timer resolution time
AHB/APBx
prescaler>4, fTIMxCLK = 1 - tTIMxCLK
137.5 MHz
Timer external clock
fEXT 0 fTIMxCLK/2 MHz
frequency on CH1 to CH4 f
TIMxCLK = 240 MHz
ResTIM Timer resolution - 16/32 bit
Maximum possible count 65536 ×
tMAX_COUNT - - tTIMxCLK
with 32-bit counter 65536
1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers.
2. Guaranteed by design.
3. The maximum timer frequency on APB1 or APB2 is up to 275 MHz, by setting the TIMPRE bit in the
RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x
Frcc_pclkx1 or TIMxCLK = 4x Frcc_pclkx2.

6.3.37 Low-power timer characteristics

The parameters given in Table 107 are guaranteed by design.
Refer to Section 6.3.17: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).

Table 107. LPTIMx characteristics(1)(2)

Symbol Parameter Min Max Unit

tres(TIM) Timer resolution time 1 - tTIMxCLK

fLPTIMxCLK Timer kernel clock 0 137.5

Timer external clock frequency on Input1 and MHz
fEXT 0 fLPTIMxCLK/2
Input2
ResTIM Timer resolution - 16 bit
tMAX_COUNT Maximum possible count - 65536 tTIMxCLK

1. LPTIMx is used as a general term to refer to the LPTIM1 to LPTIM5 timers.

2. Guaranteed by design.

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6.3.38 Communication interfaces

I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual revision 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I 2C
timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0399 reference manual) and when the i2c_ker_ck frequency is
greater than the minimum shown in the table below:

Table 108. Minimum i2c_ker_ck frequency in all I2C modes

Symbol Parameter Condition Min Unit

Standard-mode - 2
Analog Filtre ON
8
DNF=0
Fast-mode
Analog Filtre OFF MHz
I2CCLK 9
f(I2CCLK) DNF=1
frequency
Analog Filtre ON
17
DNF=0
Fast-mode Plus
Analog Filtre OFF
16 -
DNF=1

The SDA and SCL I/O requirements are met with the following restrictions:
• The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain,
the PMOS connected between the I/O pin and VDD is disabled, but still present.
• The 20 mA output drive requirement in Fast-mode Plus is not supported. This limits the
maximum load CLoad supported in Fm+, which is given by these formulas:
tr(SDA/SCL)=0.8473xRP * CLoad
RP(min)= (VDD-VOL(max))/IOL(max)
Where RP is the I2C lines pull-up. Refer to Section 6.3.17: I/O port characteristics for
the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog fil-
ter characteristics:

Table 109. I2C analog filter characteristics(1)

Symbol Parameter Min Max Unit

Maximum pulse width of spikes

tAF that are suppressed by analog 50(2) 80(3) ns
filter
1. Guaranteed by characterization results.
2. Spikes with widths below tAF(min) are filtered.

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3. Spikes with widths above tAF(max) are not filtered.

USART interface characteristics

Unless otherwise specified, the parameters given in Table 110 for USART are derived from
tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 12: General operating conditions, with the following
configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load CL = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD
• IO Compensation cell activated.
• VOS level set to VOS0
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, CK, TX, RX for USART).

Table 110. USART characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Master mode,
17.0
1.62 V < VDD < 3.6 V
- -
Slave receiver mode,
45.0
1.62 V < VDD < 3.6 V
fCK USART clock frequency MHz
Slave transmitter mode,
27.0
1.62 V < VDD < 3.6 V
- -
Slave transmitter mode,
37.0
2.5 V < VDD < 3.6 V
tsu(NSS) NSS setup time Slave mode tker+1 - -
th(NSS) NSS hold time Slave mode 2 - -
tw(SCKH),
CK high and low time Master mode 1/fCK/2-2 1/fCK/2 1/fCK/2+2
tw(SCKL)
Master mode 16 - -
tsu(RX) Data input setup time
Slave mode 1.0 - -
Master mode 0 - -
th(RX) Data input hold time
Slave mode 2.0 - - ns

Slave mode, ,
- 12.0 18
1.62 V < VDD < 3.6 V
tv(TX) Data output valid time Slave mode, ,
- 12.0 13.5
2.5 V < VDD < 3.6 V
Master mode - 0.5 1
Slave mode 9 - -
th(TX) Data output hold time
Master mode 0 - -
1. Guaranteed by characterization results.

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Figure 54. USART timing diagram in Master mode

1/fCK

CK output
CPHA = 0
CPOL = 0
CPHA = 0
CK output CPOL = 1

CPHA = 1
CPOL = 0
CPHA = 1
CPOL = 1
tw(CKH)
tsu(RX) tw(CKL)
RX
INPUT MSB IN BIT6 IN LSB IN
th(RX)
TX
OUTPUT MSB OUT BIT1 OUT LSB OUT
tv(TX) th(TX)
MSv65386V4

1. Measurement points are done at 0.5VDD and with external CL = 30 pF.

Figure 55. USART timing diagram in Slave mode

NSS
input
1/fCK th(NSS)
tsu(NSS) tw(CKH)

CPHA = 0
CK input

CPOL = 0
CPHA = 0
CPOL = 1

tw(CKL) tv(TX) th(TX)

TX output First bit OUT Next bits OUT Last bit OUT

th(RX)
tsu(RX)

RX input First bit IN Next bits IN Last bit IN

MSv65387V4

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SPI interface characteristics

Unless otherwise specified, the parameters given in Table 111 for SPI are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 12: General operating conditions, with the following
configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load CL = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD
• IO Compensation cell activated.
• HSLV activated when VDD ≤ 2.7 V
• VOS level set to VOS0
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).

Table 111. SPI characteristics(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

Master mode,
125
2.7 V < VDD < 3.6 V, SPI1, 2, 3
Master mode,
1.62 V < VDD < 3.6 V, SPI1, 2, 80/66(3)
3
Master mode,
1.62 V < VDD < 3.6 V, SPI4, 5, 68.5
6
Slave receiver mode,
fSCK SPI clock frequency - - MHz
1.62 V < VDD < 3.6 V, SPI1, 2, 100
3
Slave receiver mode,
1.62 V < VDD < 3.6 V, SPI4, 5, 68.5
6
Slave mode transmitter/full
45
duplex, 2.7 V < VDD < 3.6 V
Slave mode transmitter/full
42.5/31(4)
duplex, 1.62 V < VDD < 3.6 V
tsu(NSS) NSS setup time Slave mode 2 - -
th(NSS) NSS hold time Slave mode 1 - -
-
tw(SCKH),
SCK high and low time Master mode tSCK /2-1(5) tSCK/2(5) tSCK /2+1(5)
tw(SCKL)

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Table 111. SPI characteristics(1)(2) (continued)

Symbol Parameter Conditions Min Typ Max Unit

tsu(MI) Master mode 2.5 - -

Data input setup time
tsu(SI) Slave mode 1 - -
th(MI) Master mode 3 - -
Data input hold time
th(SI) Slave mode 1.5 - -
ta(SO) Data output access time Slave mode 9 13 27
tdis(SO) Data output disable time Slave mode 0 1 5
Slave mode, ns
- 7.5 11
2.7 V < VDD < 3.6 V
tv(SO)
Slave mode,
Data output valid time - 7.5 12/16(4)
1.62 V < VDD < 3.6 V
Master mode,
tv(MO) - 1 1.5/5.5(6)
1.62 V < VDD < 3.6 V
th(SO) Slave mode 7 - -
Data output hold time
th(MO) Master mode 0.5 - -
1. Guaranteed by characterization results.
2. The values given in the above table might be degraded when PC3_C/PC2_C I/Os are used (not available on all packages).
3. This value is obtained by using PA9 or PA12 I/O.
4. This value is obtained by using PC2 or PJ11 I/O.
5. tSCK = tker_ck * baud rate prescaler.
6. This value is obtained by using PC3 or PJ10 I/O.

Figure 56. SPI timing diagram - slave mode and CPHA = 0

NSS input

tc(SCK) th(NSS)

tsu(NSS) tw(SCKH) tr(SCK)

CPHA=0
SCK input

CPOL=0

CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tf(SCK) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

th(SI)
tsu(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41658V1

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Figure 57. SPI timing diagram - slave mode and CPHA = 1(1)

NSS input

tc(SCK)

tsu(NSS) tw(SCKH) tf(SCK) th(NSS)

CPHA=1
SCK input

CPOL=0

CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tr(SCK) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

tsu(SI) th(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41659V1

1. Measurement points are done at 0.5VDD and with external CL = 30 pF.

Figure 58. SPI timing diagram - master mode(1)

High

NSS input

tc(SCK)
SCK Output

CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
SCK Output

CPHA=1
CPOL=0
CPHA=1
CPOL=1

tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INP UT MSB IN BIT6 IN LSB IN

th(MI)
MOSI
MSB OUT B I T1 OUT LSB OUT
OUTPUT
tv(MO) th(MO)
ai14136c

1. Measurement points are done at 0.5VDD and with external CL = 30 pF.

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I2S Interface characteristics

Unless otherwise specified, the parameters given in Table 112 for I2S are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 12: General operating conditions, with the following
configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load CL = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD
• IO Compensation cell activated.
• HSLV activated when VDD ≤ 2.7 V
• VOS level set to VOS0
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (CK,SD,WS).

Table 112. I2S dynamic characteristics(1)

Symbol Parameter Conditions Min Max Unit

- - 50
Master transmitter - 50/40(2)
fMCK I2S main clock output Master receiver - 50/40(2) MHz
Slave transmitter - 41.5/31(3)
Slave receiver - 50
tv(WS) WS valid time - 2/6(4)
Master mode
th(WS) WS hold time 1 -
tsu(WS) WS setup time 3 -
Slave mode
th(WS) WS hold time 1 -
tsu(SD_MR) Master receiver 2.5 -
Data input setup time
tsu(SD_SR) Slave receiver 1 -
th(SD_MR) Master receiver 3 -
Data input hold time
th(SD_SR) Slave receiver 1.5 - ns

Slave transmitter (after enable

tv(SD_ST) - 12/16(3)
edge)
Data output valid time
Master transmitter (after
tv(SD_MT) - 2/6(5)
enable edge)
Slave transmitter (after enable
th(SD_ST) 6.5 -
edge)
Data output hold time
Master transmitter (after
th(SD_MT) 0.5 -
enable edge)
1. Guaranteed by characterization results.
2. This value is obtained when PA9 or PA12 are used.
3. This value is obtained when PC2 is used.
4. This value is obtained when PA11 or PA15 are used.

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5. This value is obtained when PC3 is used.

Figure 59. I2S slave timing diagram (Philips protocol)(1)

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.

Figure 60. I2S master timing diagram (Philips protocol)(1)

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.

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SAI characteristics
Unless otherwise specified, the parameters given in Table 113 for SAI are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 12: General operating conditions, with the following
configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load CL = 30 pF
• IO Compensation cell activated.
• Measurement points are done at CMOS levels: 0.5VDD
• VOS level set to VOS0
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
alternate function characteristics (SCK,SD,WS).

Table 113. SAI characteristics(1)

Symbol Parameter Conditions Min Max Unit

fMCK SAI Main clock output - - 50

Master transmitter, 2.7 V ≤ VDD ≤ 3.6 V - 45
Master transmitter, 1.62 V ≤ VDD ≤ 3.6 V - 32
Master receiver, 1.62 V ≤ VDD ≤ 3.6 V - 32 MHz
fCK SAI clock frequency(2)
Slave transmitter, 2.7 V ≤ VDD ≤ 3.6 V - 47.5
Slave transmitter, 1.62 V ≤ VDD ≤ 3.6 V - 41.5
Slave receiver, 1.62 V ≤ VDD ≤ 3.6 V - 50

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Table 113. SAI characteristics(1) (continued)

Symbol Parameter Conditions Min Max Unit

Master mode, 2.7 V ≤ VDD ≤ 3.6 V - 11

tv(FS) FS valid time
Master mode, 1.62 V ≤ VDD ≤ 3.6 V - 15.5
tsu(FS) FS setup time Slave mode 2.5 -
Master mode 6 -
th(FS) FS hold time
Slave mode 0.5 -
tsu(SD_A_MR) Master receiver 3 -
Data input setup time
tsu(SD_B_SR) Slave receiver 3.5 -
th(SD_A_MR) Master receiver 3.5 -
Data input hold time
th(SD_B_SR) Slave receiver 0 -
ns
Slave transmitter (after enable edge),
- 10.5
2.7 V ≤ VDD ≤ 3.6 V
tv(SD_B_ST) Data output valid time
Slave transmitter (after enable edge),
- 12
1.62 V ≤ VDD ≤ 3.6 V
th(SD_B_ST) Data output hold time Slave transmitter (after enable edge) 6.5 -
Master transmitter (after enable edge),
- 10.5
2.7 V ≤ VDD ≤ 3.6 V
tv(SD_A_MT) Data output valid time
Master transmitter (after enable edge),
- 14.5
1.62 V ≤ VDD ≤ 3.6 V
th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 6 -
1. Guaranteed by characterization results.
2. APB clock frequency must be at least twice SAI clock frequency.

Figure 61. SAI master timing waveforms

1/fSCK

SAI_SCK_X
th(FS)

SAI_FS_X
(output) tv(FS) tv(SD_MT) th(SD_MT)

SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_MR) th(SD_MR)

SAI_SD_X Slot n
(receive)
MS32771V1

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Figure 62. SAI slave timing waveforms

1/fSCK

SAI_SCK_X
tw(CKH_X) tw(CKL_X) th(FS)

SAI_FS_X
(input) tsu(FS) tv(SD_ST) th(SD_ST)

SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_SR) th(SD_SR)

SAI_SD_X Slot n
(receive)
MS32772V1

MDIO characteristics
Unless otherwise specified, the parameters given in Table 114 for the MDIO are derived
from tests performed under the ambient temperature, fPCLKx frequency and VDD supply
voltage conditions summarized in Table 12: General operating conditions, with the following
configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• I/O Compensation cell activated.
• Measurement points are done at CMOS levels: 0.5VDD
• HSLV activated when VDD ≤ 2.7 V
• VOS level set to VOS0

Table 114. MDIO Slave timing parameters

Symbol Parameter Min Typ Max Unit

FMDC Management Data Clock - - 30 MHz

td(MDIO) Management Data Iput/output output valid time 8 10 18
tsu(MDIO) Management Data Iput/output setup time 1 - - ns
th(MDIO) Management Data Iput/output hold time 1 - -

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Electrical characteristics STM32H730xB

Figure 63. MDIO Slave timing diagram

tMDC)

td(MDIO)

tsu(MDIO) th(MDIO)

MSv40460V1

SD/SDIO MMC card host interface (SDMMC) characteristics

Unless otherwise specified, the parameters given in Table 115 and Table 116 for SDIO are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage summarized in Table 12: General operating conditions, with the following
configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load CL=30 pF
• Measurement points are done at CMOS levels: 0.5VDD
• IO Compensation cell activated.
• HSLV activated when VDD ≤ 2.7 V
• VOS level set to VOS0
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.

Table 115. Dynamics characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V(1)(2)
Symbol Parameter Conditions Min Typ Max Unit

Clock frequency in data transfer

fPP - 0 - 120 MHz
mode
- SDIO_CK/fPCLK2 frequency ratio - - - 8/3 -
tW(CKL) Clock low time 8.5 9.5 -
fPP =52MHz ns
tW(CKH) Clock high time 8.5 9.5 -

CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR/DDR mode

tISU Input setup time HS - 2.5 - -

tIH Input hold time HS - 0.5 - - ns
(3)
tIDW Input valid window (variable window) - 1.5 - -

CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR/DDR mode

tOV Output valid time HS - - 5.5 6

ns
tOH Output hold time HS - 4.5 - -

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STM32H730xB Electrical characteristics

Table 115. Dynamics characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V(1)(2)
Symbol Parameter Conditions Min Typ Max Unit

CMD, D inputs (referenced to CK) in SD default mode

tISUD Input setup time SD - 1.5 -

ns
tIHD Input hold time SD - 0.5 -

CMD, D outputs (referenced to CK) in SD default mode

tOVD Output valid default time SD - - 1 1

ns
tOHD Output hold default time SD - 0 - -
1. Guaranteed by characterization results.
2. Above 100 MHz, CL = 20 pF.
3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.

Table 116. Dynamics characteristics: eMMC characteristics VDD = 1.71V to 1.9V(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

Clock frequency in data transfer

fPP - 0 - 85 MHz
mode
- SDIO_CK/fPCLK2 frequency ratio - - - 8/3 -
tW(CKL) Clock low time 8.5 9.5 -
fPP =52 MHz ns
tW(CKH) Clock high time 8.5 9.5 -

CMD, D inputs (referenced to CK) in eMMC mode

tISU Input setup time HS - 1.5 - -

tIH Input hold time HS - 1.5 - -
ns
(3) Input valid window (variable
tIDW - 3.5 - -
window)

CMD, D outputs (referenced to CK) in eMMC mode

tOVD Output valid time HS - - 6 6.5

ns
tOHD Output hold time HS - 5.5 - -
1. Guaranteed by characterization results.
2. CL = 20 pF.
3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.

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Figure 64. SD high-speed mode

tC(CK)
tW(CKH) tW(CKL)

CK
tOH
tOV

D, CMD output
tIH
tISU

D, CMD input
MSv69709V1

Figure 65. SD default mode

CK
tOV tOH

D, CMD output MSv69710V1

Figure 66. SDMMC DDR mode

D input Valid data Valid data

tISU tIH tISU tIH

tW(CKH)

CK

tW(CKL)
tOV tOV
tOH tOH

D output Valid data Valid data

MSv69158V1

USB OTG_FS characteristics

Unless otherwise specified, the parameters given in Table 118 for ULPI are derived from
tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
summarized in Table 12: General operating conditions, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load CL=20 pF
• Measurement points are done at CMOS levels: 0.5VDD
• IO Compensation cell activated.
• VOS level set to VOS0

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Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.

Table 117. USB OTG_FS electrical characteristics

Symbol Parameter Condition Min Typ Max Unit

VDD33US
USB transceiver operating voltage - 3.0(1) - 3.6 V
B

Embedded USB_DP pull-up value

RPUI - 900 1250 1600
during idle
Embedded USB_DP pull-up value
RPUR - 1400 2300 3200 Ω
during reception
Driver high
ZDRV Output driver impedance(2) 28 36 44
and low
1. The USB functionality is ensured down to 2.7 V. However, not all USB electrical characteristics are
degraded in the 2.7 to 3.0 V voltage range.
2. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching
impedance is already included in the embedded driver.

USB OTG_HS characteristics

Unless otherwise specified, the parameters given in Table 118 for ULPI are derived from
tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
summarized in Table 12: General operating conditions, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load CL=20 pF
• Measurement points are done at CMOS levels: 0.5VDD
• IO Compensation cell activated.
• VOS level set to VOS0
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.

Table 118. Dynamics characteristics: USB ULPI(1)

Symbol Parameter Condition Min Typ Max Unit

Control in (ULPI_DIR , ULPI_NXT)

tSC - 5.5 - -
setup time
Control in (ULPI_DIR, ULPI_NXT) hold
tHC - 0 - -
time
tSD Data in setup time - 2.5 - -
ns
tHD Data in hold time - 0 - -
2.7 V < VDD < 3.6 V,
- 6.0 8.0
CL = 20 pF
tDC/tDD Control/Datal output delay
1.71 V < VDD < 3.6 V
- 6.0 12
, CL = 15 pF
1. Guaranteed by characterization results.

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Figure 67. ULPI timing diagram

Clock

tSC tHC
Control In
(ULPI_DIR,
ULPI_NXT) tSD tHD
data In
(8-bit)

tDC tDC
Control out
(ULPI_STP)
tDD
data out
(8-bit)
ai17361c

Ethernet interface characteristics

Unless otherwise specified, the parameters given in Table 119, Table 120 and Table 121 for
SMI, RMII and MII are derived from tests performed under the ambient temperature,
frcc_c_ck frequency and VDD supply voltage conditions summarized in Table 12: General
operating conditions, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load CL=20 pF
• Measurement points are done at CMOS levels: 0.5VDD
• IO Compensation cell activated.
• HSLV activated when VDD ≤ 2.7 V
• VOS level set to VOS1
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics:

Table 119. Dynamics characteristics: Ethernet MAC signals for SMI (1)
Symbol Parameter Min Typ Max Unit

tMDC MDC cycle time( 2.5 MHz) 400 400 403

Td(MDIO) Write data valid time 0.5 1.5 4
ns
tsu(MDIO) Read data setup time 12.5 - -
th(MDIO) Read data hold time 0 - -
1. Guaranteed by characterization results.

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STM32H730xB Electrical characteristics

Figure 68. Ethernet SMI timing diagram

tMDC

ETH_MDC

td(MDIO)

ETH_MDIO(O)

tsu(MDIO) th(MDIO)

ETH_MDIO(I)

MS31384V1

Table 120. Dynamics characteristics: Ethernet MAC signals for RMII (1)
Symbol Parameter Min Typ Max Unit

tsu(RXD) Receive data setup time 2 - -

tih(RXD) Receive data hold time 2 - -
tsu(CRS) Carrier sense setup time 1.5 - -
ns
tih(CRS) Carrier sense hold time 1.5 - -
td(TXEN) Transmit enable valid delay time 8 0 10.5
td(TXD) Transmit data valid delay time 7 8 9.5
1. Guaranteed by characterization results.

Figure 69. Ethernet RMII timing diagram

RMII_REF_CLK

td(TXEN)
td(TXD)

RMII_TX_EN
RMII_TXD[1:0]

tsu(RXD) tih(RXD)
tsu(CRS) tih(CRS)

RMII_RXD[1:0]
RMII_CRS_DV

ai15667b

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Table 121. Dynamics characteristics: Ethernet MAC signals for MII (1)
Symbol Parameter Min Typ Max Unit

tsu(RXD) Receive data setup time 2.0 - -

tih(RXD) Receive data hold time 2.0 - -
tsu(DV) Data valid setup time 1.5 - -
tih(DV) Data valid hold time 1.5 - -
ns
tsu(ER) Error setup time 1.5 - -
tih(ER) Error hold time 0.5 - -
td(TXEN) Transmit enable valid delay time 9.0 11 19
td(TXD) Transmit data valid delay time 8.5 10 19
1. Guaranteed by characterization results.

Figure 70. Ethernet MII timing diagram

MII_RX_CLK

tsu(RXD) tih(RXD)
tsu(ER) tih(ER)
tsu(DV) tih(DV)

MII_RXD[3:0]
MII_RX_DV
MII_RX_ER

MII_TX_CLK

td(TXEN)
td(TXD)

MII_TX_EN
MII_TXD[3:0]

ai15668b

JTAG/SWD interface characteristics

Unless otherwise specified, the parameters given in Table 122 and Table 123 for
JTAG/SWD are derived from tests performed under the ambient temperature, frcc_c_ck
frequency and VDD supply voltage summarized in Table 12: General operating conditions,
with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load CL=30 pF
• Measurement points are done at CMOS levels: 0.5VDD
• VOS level set to VOS0
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics:

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STM32H730xB Electrical characteristics

Table 122. Dynamics JTAG characteristics

Symbol Parameter Conditions Min Typ Max Unit

Fpp 2.7V <VDD< 3.6 V - - 37

TCK clock frequency
1/tc(TCK) 1.62 <VDD< 3.6 V - - 27.5
MHz
tisu(TMS) TMS input setup time - 2.5 - -
tih(TMS) TMS input hold time - 1 - -
tisu(TDI) TDI input setup time - 1.5 - - -
tih(TDI) TDI input hold time - 1 - - -
2.7V <VDD< 3.6 V - 8 13.5 -
tov(TDO) TDO output valid time
1.62 <VDD< 3.6 V - 8 18 -
toh(TDO) TDO output hold time - 7 - - -

Table 123. Dynamics SWD characteristics

Symbol Parameter Conditions Min Typ Max Unit

Fpp 2.7V <VDD< 3.6 V - - 71

SWCLK clock frequency MHz
1/tc(SWCLK) 1.62 <VDD< 3.6 V - - 52.5
tisu(SWDIO) SWDIO input setup time - 2.5 - - -
tih(SWDIO) SWDIO input hold time - 1 - - -
2.7V <VDD< 3.6 V - 8.5 14 -
tov(SWDIO) SWDIO output valid time 1.62 <VDD< 3.6 V
- 8.5 19 -

toh(SWDIO) SWDIO output hold time - 8 - - -

Figure 71. JTAG timing diagram

tc(TCK)

TCK

tsu(TMS/TDI) th(TMS/TDI)
tw(TCKL) tw(TCKH)
TDI/TMS

tov(TDO) toh(TDO)

TDO

MSv40458V1

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Figure 72. SWD timing diagram

tc(SWCLK)

SWCLK

tsu(SWDIO) th(SWDIO) twSWCLKL) tw(SWCLKH)

SWDIO
(receive)

tov(SWDIO) toh(SWDIO)

SWDIO
(transmit)

MSv40459V1

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Package information STM32H730xB

7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at www.st.com. ECOPACK
is an ST trademark.

240/270 DS13315 Rev 3

STM32H730xB Package information

7.1 LQFP100 package information

This LQFP100 is a 100-pin, 14 x 14 mm low-profile quad flat package.

Figure 73. LQFP100- Outline

θ2 θ1

R1

H
R2

B
B-
N
O
(4)

TI
C
SE
D1/4 B GAUGE PLANE

S
E1/4
B θ
4x N/4 TIPS
θ3 L
4x L1
aaa C A-B D
bbb H A-B D

BOTTOM VIEW SECTION A-A

(N-4) x e
C
A
0.05
b ccc C b WITH PLATING
A2 A1 aaa C A-BD

SIDE VIEW

D c
D1 c1
D
(5) N

b1 BASE METAL
1
2
3 E1/4 SECTION B-B

D1/4 (4)
A B

E1 E

SECTION A-A

A A

TOP VIEW 1L_LQFP100_ME_V2

1. Drawing is not to scale.

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Table 124. LQFP100 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A - 1.50 1.60 - 0.0590 0.0630

(2)
A1 0.05 - 0.15 0.0019 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0570
(3)(4)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(4)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
(4)
c 0.09 - 0.20 0.0035 - 0.0079
c1(4) 0.09 - 0.16 0.0035 - 0.0063
(5)
D 16.00 0.6299
(6)(7)
D1 14.00 0.5512
E(5) 16.00 0.6299
E1(6)(7) 14.00 0.5512
e - 0.50 - - 0.0197 -
L 0.45 0.60 0.75 0.177 0.0236 0.0295
(4)
L1 1.00 - 0.0394 -
N(8) 100
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa(9) 0.20 0.0079
bbb(9) 0.20 0.0079
(9)
ccc 0.08 0.0031
(9)
ddd 0.08 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. A1 is defined as the distance from the seating plane to the lowest point on the package body.
3. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead
width to exceed the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the
lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm
and 0.5 mm pitch packages.
4. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
5. To be determined at seating datum plane C.
6. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm.
7. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is
“0.25 mm” per side. D1 and E1 are Maximum plastic body size dimensions including mold mismatch.

242/270 DS13315 Rev 3

STM32H730xB Package information

8. “N” is the max number of terminal positions for the specified body size.
9. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.

LQFP100 - Recommended footprint

75 51

76 50
0.5

0.3

16.7 14.3

100 26

1.2
1 25

12.3

16.7

1L_LQFP100_FP_V1

Dimensions are expressed in millimeters.

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Package information STM32H730xB

Device marking for LQFP100

The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.

Figure 74. LQFP100 marking example (package top view)

Product identification(1)
STM32H730

VBT6 Revision code

R
Date code

Y WW
Pin 1
indentifier

MSv65317V1

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.

244/270 DS13315 Rev 3

STM32H730xB Package information

7.2 TFBGA100 package information

This TFBGA is 100 - ball, 8X8 mm, 0.8 mm pitch fine pitch ball grid array package.

Figure 75. TFBGA100 - Outline

ddd C
SEATING
PLANE

A1

A
A2

A1 ball
index
B

D1 A1 ball area
identifier
e D
F

A
B
C
G

D
E
E1

E
F
G
e

H A
J
K
10 9 8 7 6 5 4 3 2 1

BOTTOM VIEW TOP VIEW

b (100 BALLS)

eee C A B
fff C

A08Q_ME_V1

1. Drawing is not to scale.

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Table 125. TFBGA100 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A - - 1.100 - - 0.0433
A1 0.150 - - 0.0059 - -
A2 - 0.760 - - 0.0299 -
b 0.350 0.400 0.450 0.0138 0.0157 0.0177
D 7.850 8.000 8.150 0.3091 0.3150 0.3209
D1 - 7.200 - 0.2835 -
E 7.850 8.000 8.150 0.3091 0.3150 0.3209
E1 - 7.200 - - 0.2835 -
e - 0.800 - - 0.0315 -
F - 0.400 - - 0.0157 -
G - 0.400 - - 0.0157 -
ddd - - 0.100 - - 0.0039
eee - - 0.150 - - 0.0059
fff - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 76. TFBGA100 - Recommended footprint

Dpad

Dsm
BGA_WLCSP_FT_V1

1. Dimensions are expressed in millimeters.

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STM32H730xB Package information

Table 126. TFBGA100 - Recommended PCB design rules (0.8 mm pitch BGA)
Dimension Recommended values

Pitch 0.8
Dpad 0.400 mm
0.470 mm typ (depends on the soldermask
Dsm
registration tolerance)
Stencil opening 0.400 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.120 mm

Device marking for TFBGA100

The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.

Figure 77. TFBGA100 marking example (package top view)

Product
identification(1)

STM32H730 Revision code

VBH6

R
Date code

Ball Y WW
A1identifier

MSv65318V1

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.

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Package information STM32H730xB

7.3 LQFP144 package information

This LQFP is a 144-pin, 20 x 20 mm low-profile quad flat package.

Figure 78. LQFP144 - Outline

SEATING
PLANE
C
A

A1
A2

c
0.25 mm
ccc C GAUGE PLANE

A1
D
L

K
D1
L1
D3

108 73

109
72
b

E1
E3

37
144

PIN 1 1 36
IDENTIFICATION

e
1A_ME_V4

1. Drawing is not to scale.

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STM32H730xB Package information

Table 127. LQFP144 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 21.800 22.000 22.200 0.8583 0.8661 0.8740
D1 19.800 20.000 20.200 0.7795 0.7874 0.7953
D3 - 17.500 - - 0.6890 -
E 21.800 22.000 22.200 0.8583 0.8661 0.8740
E1 19.800 20.000 20.200 0.7795 0.7874 0.7953
E3 - 17.500 - - 0.6890 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7° 0° 3.5° 7°
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

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Package information STM32H730xB

Figure 79. LQFP144 - Recommended footprint

1.35
108 73

109 0.35 72

0.5

19.9 17.85
22.6

144 37

1 36
19.9

22.6
ai14905e

1. Dimensions are expressed in millimeters.

250/270 DS13315 Rev 3

STM32H730xB Package information

Device marking for LQFP144

The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.

Figure 80. LQFP144 marking example (package top view)

Product
identification(1)
ES32H730
ZBT6
Revision code

R
Date code
Y WW

Pin 1 identifier

MSv65319V1

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.

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Package information STM32H730xB

7.4 UFBGA144 package information

This UFBGA is a 144-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package.

Figure 81. UFBGA144 - Outline

Z Seating plane

ddd Z

A4 A3 A2 A1 A
E1 A1 ball A1 ball X
identifier index area E
e F

A
F

D1 D

e
Y
M

12 1
BOTTOM VIEW Øb (144 balls) TOP VIEW
Ø eee M Z Y X
Ø fff M Z A0AS_ME_V2

1. Drawing is not to scale.

Table 128. UFBGA144 - Mechanical data

millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.

A 0.460 0.530 0.600 0.0181 0.0209 0.0236

A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 0.400 0.450 0.500 0.0157 0.0177 0.0197
A3 - 0.130 - - 0.0051 -
A4 0.270 0.320 0.370 0.0106 0.0126 0.0146
b 0.230 0.280 0.320 0.0091 0.0110 0.0126
D 6.950 7.000 7.050 0.2736 0.2756 0.2776
D1 5.450 5.500 5.550 0.2146 0.2165 0.2185
E 6.950 7.000 7.050 0.2736 0.2756 0.2776
E1 5.450 5.500 5.550 0.2146 0.2165 0.2185
e - 0.500 - - 0.0197 -
F 0.700 0.750 0.800 0.0276 0.0295 0.0315

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Table 128. UFBGA144 - Mechanical data (continued)

millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.

ddd - - 0.100 - - 0.0039

eee - - 0.150 - - 0.0059
fff - - 0.050 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 82. UFBGA144 - Recommended footprint

Dpad

Dsm
BGA_WLCSP_FT_V1

Table 129. UFBGA144 - Recommended PCB design rules (0.50 mm pitch BGA)
Dimension Recommended values

Pitch 0.50 mm
Dpad 0.280 mm
0.370 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil opening 0.280 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.120 mm

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Device marking for UFBGA144

The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.

Figure 83. UFBGA144 marking example (package top view

STM32H

Product identification(1)

730ZBI6

Revision code

Date code

Y WW R

Ball A1
identifier

MSv65320V1

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.

254/270 DS13315 Rev 3

STM32H730xB Package information

7.5 UFBGA169 package information

This UFBGA is a 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package.

Figure 84. UFBGA169 - Outline

Z Seating plane
A2 A4
ddd Z
A
A3 A1
b
SIDE VIEW A1 ball A1 ball
identifier index area X
E
E1
e F

A
F

D1 D

e
Y
N
13 1

BOTTOM VIEW Øb (169 balls) TOP VIEW

Ø eee M Z X Y
Ø fff M Z
A0YV_ME_V2

1. Drawing is not in scale.

Table 130. UFBGA169 - Mechanical data

millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.

A 0.460 0.530 0.600 0.0181 0.0209 0.0236

A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 0.400 0.450 0.500 0.0157 0.0177 0.0197
A3 - 0.130 - - 0.0051 -
A4 0.270 0.320 0.370 0.0106 0.0126 0.0146
b 0.230 0.280 0.330 0.0091 0.0110 0.0130
D 6.950 7.000 7.050 0.2736 0.2756 0.2776
D1 5.950 6.000 6.050 0.2343 0.2362 0.2382
E 6.950 7.000 7.050 0.2736 0.2756 0.2776
E1 5.950 6.000 6.050 0.2343 0.2362 0.2382
e - 0.500 - - 0.0197 -
F 0.450 0.500 0.550 0.0177 0.0197 0.0217

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Table 130. UFBGA169 - Mechanical data (continued)

millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.

ddd - - 0.100 - - 0.0039

eee - - 0.150 - - 0.0059
fff - - 0.050 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 85. UFBGA169 - Recommended footprint

Dpad

Dsm MS18965V2

Table 131. UFBGA169 - Recommended PCB design rules (0.5 mm pitch BGA)
Dimension Recommended values

Pitch 0.5
Dpad 0.27 mm
0.35 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Solder paste 0.27 mm aperture diameter.

Note: Non-solder mask defined (NSMD) pads are recommended.

4 to 6 mils solder paste screen printing process.

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STM32H730xB Package information

Device marking for UFBGA169

The following figure gives an example of topside marking versus ball A1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.

Figure 86. UFBGA169 marking example (package top view)

Ball A1
identifier

STM32H

Product identification(1)

730ABI6Q

Revision code
Date code

Y WW R

MSv65321V1

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.

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7.6 LQFP176 package information

This LQFP is a 176-pin, 24 x 24 mm low profile quad flat package.

Figure 87. LQFP176 - Outline

θ θ

R1

H R2

B(See SECTION B-B)

GAUGE PLANE
0.25
D1/4
S θ
B
L
E1/4 θ3
4x N/4 TIPS 4x (L1)
bbb H A-B D
aaa C A-B D

BOTTOM VIEW SECTION A-A

A2 0.05
(N-4) x e
C
A
A1 ddd C A-BD ccc C
b

SIDE VIEW

D
D1
D
N
b WITH PLATING

E1/4

c c1
D1/4
A B
E1 E b1 BASE METAL

SECTION A-A
A A
SECTION B-B

TOP VIEW 1T_LQFP176_ME_V1

1. Drawing is not to scale.

2. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
3. Datums A-B and D to be determined at datum plane H.
4. Detail of pin 1 identifier are optional but must be located within the zone indicated.
5. Exact shape of each corner is optional.

Table 132. LQFP176 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1(2) 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
(3)(4)
b 0.170 0.220 0.270 0.0067 0.0087 0.0106

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Table 132. LQFP176 - Mechanical data (continued)

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
(4)
b1 0.170 0.200 0.230 0.0067 0.0079 0.0091
(4)
c 0.090 - 0.200 0.0035 - 0.0079
(4)
c1 0.090 - 0.160 0.0035 - 0.063
D(5) 26.000 1.0236
D1(6)(7) 24.000 0.9449
(5)
E 26.000 0.0197
(6)(7)
E1 24.000 0.9449
e 0.500 0.1970
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
(4)
L1 1 0.0394 REF
(8)
N 176
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.080 - - 0.0031 - -
R2 0.080 - 0.200 0.0031 - 0.0079
S 0.200 - - 0.0079 - -
(9)
aaa 0.200 0.0079
bbb(9) 0.200 0.0079
(9)
ccc 0.080 0.0031
(9)
ddd 0.080 0.0031
1. Values in inches are converted from mm and rounded to four decimal digits.
2. A1 is defined as the distance from the seating plane to the lowest point on the package body.
3. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead
width to exceed the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the
lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm
and 0.5 mm pitch packages.
4. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
5. To be determined at seating datum plane C.
6. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm.
7. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is
“0.25 mm” per side. D1 and E1 are Maximum plastic body size dimensions including mold mismatch.
8. “N” is the max number of terminal positions for the specified body size.
9. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.

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Figure 88. LQFP176 - Recommended footprint

1.2
176 133
1 0.5 132

0.3
26.7

21.8

44 89
45 88
1.2

21.8

26.7

1T_FP_V1

1. Dimensions are expressed in millimeters.

260/270 DS13315 Rev 3

STM32H730xB Package information

Device marking for LQFP176

The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.

Figure 89. LQFP176 marking example (package top view

Product STM32H730IBT6Q
identification(1)

Revision code

R
Date code
Y WW

Pin 1 identifier

MSv65323V1

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.

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7.7 UFBGA176+25 package information

This UFBGA176+25 is a 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array
package.

Figure 90. UFBGA176+25 - Outline

Seating plane
C A4
ddd C

A
A3 A2 b A1
A1 ball A
A1 ball index E
identifier area
E1
e Z
A
Z

D1 D

e
B
R
15 1
Øb (176 + 25 balls)
BOTTOM VIEW Ø eee M C A B
TOP VIEW
Ø fff M C

A0E7_ME_V8

1. Drawing is not to scale.

Table 133. UFBGA176+25 - Mechanical data

millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.

A - - 0.600 - - 0.0236
A1 - - 0.110 - - 0.0043
A2 - 0.130 - - 0.0051 -
A3 - 0.450 - - 0.0177 -
A4 - 0.320 - - 0.0126 -
b 0.240 0.290 0.340 0.0094 0.0114 0.0134
D 9.850 10.000 10.150 0.3878 0.3937 0.3996
D1 - 9.100 - - 0.3583 -
E 9.850 10.000 10.150 0.3878 0.3937 0.3996
E1 - 9.100 - - 0.3583 -
e - 0.650 - - 0.0256 -
Z - 0.450 - - 0.0177 -
ddd - - 0.080 - - 0.0031

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STM32H730xB Package information

Table 133. UFBGA176+25 - Mechanical data (continued)

millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.

eee - - 0.150 - - 0.0059

fff - - 0.050 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 91. UFBGA176+25 - Recommended footprint

Dpad
Dsm

A0E7_FP_V1

Table 134. UFBGA176+25 - Recommended PCB design rules (0.65 mm pitch BGA)
Dimension Recommended values

Pitch 0.65 mm
Dpad 0.300 mm
0.400 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil opening 0.300 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.100 mm

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Device marking for UFBGA176+25

The following figure gives an example of topside marking versus ball A1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.

Figure 92. UFBGA176+25 marking example (package top view

Product
identification(1)

STM32H730 Revision code

IBK6Q

R
Date code

Ball Y WW
A1identifier

MSv65322V1

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.

264/270 DS13315 Rev 3

STM32H730xB Package information

7.8 Thermal characteristics

The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max × ΘJA)
Where:
• TA max is the maximum ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 135. Thermal characteristics
Symbol Definition Parameter Value Unit
Thermal resistance junction-ambient
43.8
LQFP100 - 14 x 14 mm /0.5 mm pitch
Thermal resistance junction-ambient
43.2
TFBGA100 - 8 x 8 mm /0.8 mm pitch
Thermal resistance junction-ambient
44.8
LQFP144 - 20 x 20 mm /0.5 mm pitch
Thermal resistance Thermal resistance junction-ambient
ΘJA TBD °C/W
junction-ambient UFBGA144 - 7 x 7 mm /0.5 mm pitch
Thermal resistance junction-ambient
38
UFBGA169 - 7 x 7 mm / 0.5 mm pitch
Thermal resistance junction-ambient
48.3
LQFP176 - 24 x 24 mm / 0.5 mm pitch
Thermal resistance junction-ambient
38
UFBGA176+25 - 10 x 10 mm / 0.65 mm pitch

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Table 135. Thermal characteristics (continued)

Symbol Definition Parameter Value Unit
Thermal resistance junction-ambient
19.8
LQFP100 - 14 x 14 mm /0.5 mm pitch
Thermal resistance junction-ambient
24.8
TFBGA100 - 8 x 8 mm /0.8 mm pitch
Thermal resistance junction-ambient
24.4
LQFP144 - 20 x 20 mm /0.5 mm pitch

Thermal resistance Thermal resistance junction-ambient

ΘJB TBD °C/W
junction-board UFBGA144 - 7 x 7 mm /0.5 mm pitch
Thermal resistance junction-ambient
18
UFBGA169 - 7 x 7 mm / 0.5 mm pitch
Thermal resistance junction-ambient
29.1
LQFP176 - 24 x 24 mm / 0.5 mm pitch
Thermal resistance junction-ambient
20
UFBGA176+25 - 10 x 10 mm / 0.65 mm pitch
Thermal resistance junction-ambient
7.3
LQFP100 - 14 x 14 mm /0.5 mm pitch
Thermal resistance junction-ambient
13.2
TFBGA100 - 8 x 8 mm /0.8 mm pitch
Thermal resistance junction-ambient
7.4
LQFP144 - 20 x 20 mm /0.5 mm pitch

Thermal resistance Thermal resistance junction-ambient

ΘJC TBD °C/W
junction-case UFBGA144 - 7 x 7 mm /0.5 mm pitch
Thermal resistance junction-ambient
11
UFBGA169 - 7 x 7 mm / 0.5 mm pitch
Thermal resistance junction-ambient
7.9
LQFP176 - 24 x 24 mm / 0.5 mm pitch
Thermal resistance junction-ambient
24
UFBGA176+25 - 10 x 10 mm / 0.65 mm pitch

7.8.1 Reference documents

• JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
• For information on thermal management, refer to application note “Thermal
management guidelines for STM32 applications” (AN5036) available from www.st.com.

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STM32H730xB Ordering information

8 Ordering information
Example: STM32 H 730 V B T 6 Q TR

Device family
STM32 = Arm-based 32-bit microcontroller

Product type
H = High performance

Device subfamily
730 = STM32H730

Pin count
V = 100 pins
Z = 144 pins
A = 169 pins
I = 176 pins/balls

Flash memory size

B= 128 Kbytes

Package
T = LQFP ECOPACK2
K = UFBGA pitch 0.65 mm ECOPACK2
I = UFBGA pitch 0.5 mm ECOPACK2
H = TFBGA ECOPACK2

Temperature range
6 = –40 to 85 °C

Option
Q = with SMPS
Blank = without SMPS

Packing
TR = tape and reel
No character = tray or tube

For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.

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Revision history STM32H730xB

9 Revision history

Table 136. Document revision history

Date Revision Changes

10-Jul-2020 1 Initial release.

Renamed Section 3.31 into True random number generator (RNG).
Replaced VDDIOx by VDD in Section 6: Electrical characteristics.
Updated IIO in Table 10: Current characteristics and Table 17: Inrush
current and inrush electric charge characteristics for LDO and SMPS.
Removed Table 13: Supply voltage and maximum temperature
configuration.
Updated Table 27: Typical current consumption in Autonomous mode,
Table 30: Typical and maximum current consumption in Standby mode
03-Sep-2020 2
and Table 31: Typical and maximum current consumption in VBAT mode.
Added Section 6.3.16: I/O current injection characteristics.
Removed reference to PI8 in Table 55: Output voltage characteristics for
all I/Os except PC13, PC14 and PC15 and Table 56: Output voltage
characteristics for PC13, PC14 and PC15.
Added Section : Analog switch between ports Pxy_C and Pxy.
Added Figure 88: LQFP176 - Recommended footprint and Table 131:
UFBGA169 - Recommended PCB design rules (0.5 mm pitch BGA).
Added indication that patents apply to the devices in Section : Features.

Table 1: STM32H730xB features and peripheral counts:

– Changed number of general-purpose 32-bit timers to 4.
– For LQFP100 and TFBGA100 packages, replaced 2 Octo-SPI/Quad-
SPI interfaces by 1 and remove note
– Changed number of SPI/I2S from 4/4 to 6/4 for UFBGA169.

In Section 3.8.1: Power supply scheme, changed VDD power supply

requirements.
Section 3.8.3: Voltage regulator: Scale0 is available even without LDO.
Section 3.37: Universal synchronous/asynchronous receiver transmitter
(USART): changed USART communication speed to 17 Mbit/s.
07-Dec-2021 3

Table 7: STM32H730xB pin and ball descriptions:

– for PA15(JTDI), replaced SPI3_NSS/I2S3_WS alternate function by
SPI3_NSS(boot)/I2S3_WS.
– Added Note 1.and Note 2.to the package pin/balls corresponding to
Pxy and Pxy_C.

Added VBAT in Table 12: General operating conditions.

Moved LSI clock from backup domain to VDD domain in Figure 13: Power
supply scheme.
Modified Section 6.3.3: SMPS step-down converter including Figure 16:
External components for SMPS step-down converter.

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Table 136. Document revision history

Date Revision Changes

Updated Table 18: Operating conditions at power-up/power-down title

and added tVCORE.
Updated measurement conditions for Typical and maximum current
consumption. Modified Table 29: Typical and maximum current
consumption in System Stop mode. Updated Figure 17: Typical SMPS
efficiency (%) vs load current (A) in Run mode at TJ = 30 °C.
Section : On-chip peripheral current consumption: updated measurement
conditions and Table 32: Peripheral current consumption in Run mode.
Updated Table 34: High-speed external user clock characteristics.
Changed unit for PLL long-term jitter in Table 42: PLL1 characteristics
(wide VCO frequency range).

Renamed ILEAK parameter into Ilkg in Table 54: I/O static characteristics.

Table 58: Output timing characteristics (HSLV ON): updated load

capacitance condition for tr/tf and for speed = 10.
Updated Figure 40: OCTOSPI SDR read/write timing diagram, Figure 41:
OCTOSPI DTR mode timing diagram, Figure 42: OCTOSPI Hyperbus
clock timing diagram, Figure 43: OCTOSPI Hyperbus read timing
diagram and Figure 44: OCTOSPI Hyperbus write timing diagram.
07-Dec-2021 3 (continued)
Table 83: 16-bit ADC characteristics: updated sampling rate for slow
channels.
Updated Figure 45: ADC accuracy characteristics and Figure 46: Typical
connection diagram when using the ADC with FT/TT pins featuring
analog switch function as well as notes below figure.
Updated Figure 47: Power supply and reference decoupling (VREF+ not
connected to VDDA).
Updated TL max value in Table 92: Temperature sensor characteristics.
Changed temperature condition to 130 °C for TS_CAL2 in Table 93:
Temperature sensor calibration values.

Updated Figure 54: USART timing diagram in Master mode and

Figure 55: USART timing diagram in Slave mode.
Updated Figure 64: SD high-speed mode, Figure 65: SD default mode
and Figure 66: SDMMC DDR mode.
Updated Figure 70: Ethernet MII timing diagram.
Updated Figure 73: LQFP100- Outline, Table 124: LQFP100 -
Mechanical data, Figure 76: TFBGA100 - Recommended footprint,
Figure 87: LQFP176 - Outline and Table 132: LQFP176 - Mechanical
data.

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 STM32H730xB

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