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Assignment 1, 2021-22 (1) DMU Assignment

This document provides specifications for Assignment 1 of the Advanced Digital Design course. It requires students to design a 4-bit universal decimal counter in VHDL, simulate it using a graphical testbench in Xilinx ISE v10.1.03, and submit a formal report explaining the design, code, simulation results, and conclusions. The report is worth 40% of the overall module mark. Students must submit an electronic copy of their assignment by December 4, 2022. Late submissions within 14 days will be capped at 40% if passed.

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96 views

Assignment 1, 2021-22 (1) DMU Assignment

This document provides specifications for Assignment 1 of the Advanced Digital Design course. It requires students to design a 4-bit universal decimal counter in VHDL, simulate it using a graphical testbench in Xilinx ISE v10.1.03, and submit a formal report explaining the design, code, simulation results, and conclusions. The report is worth 40% of the overall module mark. Students must submit an electronic copy of their assignment by December 4, 2022. Late submissions within 14 days will be capped at 40% if passed.

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Assignment 1 Coursework Specification

Module name: Advanced Digital Design


Module code: ENGD3001
Title of the Assignment: Assignment 1
This coursework item is: Formative
This coursework will be marked anonymously: Yes
The module learning outcomes that are assessed by this coursework are:
1. “Knowledge and specialist analytic development techniques in the areas of VLSI design, ASM design
and implementation, and VHDL design.”
2. “Development of generic and transferable skills in advanced digital system design methodologies using
industry standard design tools.”
This coursework is: Individual
This coursework constitutes 40% to the overall module mark.
Date Set: by DMU
Date & Time Due: by Sunday, 04 Dec 2022
When completed you are required to submit the following:
Submit an electronic copy of your assignment via Blackboard by the advertised deadline.

Please note that once a submission is made it is final. No resubmissions are allowed under any
circumstances, so please ensure that your report is correct and complete before submitting it.

Your marked coursework and feedback will be available to you on:


If for any reason this is not forthcoming by the due date your module leader will let you 25 Dec 2022
know why and when it can be expected.
Late submission of coursework policy:
Late submissions will be processed in accordance with current University regulations which state:
“The time period during which a student may submit a piece of work late without authorisation and have the
work capped at 40% [50% at PG level] if passed is 14 calendar days. Work submitted unauthorised more
than 14 calendar days after the original submission date will receive a mark of 0%. These regulations
apply to a student’s first attempt at coursework. Work submitted late without authorisation which constitutes
reassessment of a previously failed piece of coursework will always receive a mark of 0%.”
Academic Offences and Bad Academic Practices:
These include plagiarism, cheating, collusion, copying work and reuse of your own work, poor referencing or
the passing off of somebody else's ideas as your own. If you are in any doubt about what constitutes an
academic offence or bad academic practice you must check with your tutor. Further information and details of
how DSU can support you, if needed, is available at:
https://www.dmu.ac.uk/current-students/student-support/exams-deferrals-regulations-policies/student-
regulations-and-policies/academic-offences.aspx
and
https://www.dmu.ac.uk/current-students/student-support/exams-deferrals-regulations-policies/student-
regulations-and-policies/bad-academic-practice.aspx
Module leader/tutor name: Mr. Duminda Wijesinghe
Contact details: Email: [email protected]
Assignment 1
Design in VHDL a 4-bit universal decimal counter as presented below:

LD

D3 Q3
D2 Q2
D1 Q1
D0 Q0

U/D LD – Synchronous Parallel Load


D3,…,D0 – Parallel Data Inputs
RST Q3,…,Q0 – Data Outputs
RST – Asynchronous Reset Input
U/D – Count direction (up/down)

The operation of the universal counter is described by the following function table:

RST LD U/D Action


0 x x Asynchronous Reset
1 0 0 Count Down
1 0 1 Count Up
1 1 x Synchronous Parallel Load

Simulate this design with the aid of a ‘graphical testbench’ (also known as a “Test Bench
Waveform” file), using the Xilinx ISE v10.1.03 software. It is a mandatory requirement to use
the correct software version and the correct type of testbench.

What you should submit

You should submit a formal report explaining your design and your results. For general guidance
on writing (technical) reports please refer to the following links:
https://www.theiet.org/media/5182/technical-report-writing.pdf
https://library.dmu.ac.uk/ld.php?content_id=31952526
https://library.dmu.ac.uk/class/HEAT
Specifically, your report should contain at least: a) an introduction including the design brief, b) a
background section on counters, their types and their operation, c) a section explaining how
you’ve solved the design task given to you and if applicable why you’ve selected a particular
solution out of several possible, d) the complete listing of the code you’ve written, bearing in
mind good programming and design practice, e) a screenshot of your graphical testbench, f) the
results of the simulations carried out (i.e. suitable, legible and detailed simulation waveforms)
accompanied by detailed comments and explanations, and g) conclusions (and possible further
improvements if applicable). Avoid including simulation waveforms with a black background.
For full marking details please consult the associated marking scheme from Blackboard.

Please also make sure that you carefully read the corresponding Blackboard announcement and the
ENGD3001 Module Handbook which contain important information, advice and guidelines
regarding your assignments.

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