Vol.

2, 63
Proceedings of SPIT-IEEE Colloquium and International Conference, Mumbai, India

Design of Low Power Integrated SAR-ADC in

0.18µm Mixed-Mode CMOS Process
Aniruddha C. Kailuke, Vrushali G. Nasre, M.Shojaei-Baghini, Rajendra.D.Kanphade Member, IEEE

Abstract- Main building blocks of a SAR-ADC are: sample & High resolution and accuracy can be achieved using
hold circuit, comparator, timing and logic control which is capacitor array during data conversion. Considering these
mainly SAR logic, DAC (Digital to Analog Converter) in the factors, SAR becomes an ideal component for some portable
feedback loop of ADC. For low-power applications designer
or battery-powered instruments. The overall system
needs to come up with a compromise among speed, resolution
and speed. In this paper a SAR-ADC is designed in 0.18µm architecture is shown in “Fig.1”. We designed and
CMOS technology in such a way that the total power is implemented all the blocks of SAR-ADC and results are
minimized while medium sampling rate and 8 bit resolution are validated using CADENCE Virtuoso Analog Design
achieved. A passive sample-and-hold stage and a capacitor-based Environment IC (5.0.33/5.1.41) tool.
digital-to-analog converter are used to avoid use of current to
voltage converter. This design is suitable for standard CMOS II. CONVERTER PRINCIPLE
technology with low-power low-cost VLSI implementation. It is
well applied when embedded into system-on-chip (SOC) circuit Successive Approximation Converter based on a Charge
designs. Redistribution Principle is characterized in “Fig. 2”. Binary
Index Terms-Analog-to-digital converters (ADCs), CMOS weighted capacitors are used for the DAC. The switching
analog integrated circuits, low power, low supply voltage, point of the comparator is independent of the value of the
successive approximation.
input signal. During conversion, at the comparator input
positive and negative voltages VC referred to analog ground
I. INTRODUCTION occur, whose magnitude is continuously decreasing with the
T ODAYS trend in mixed-signal ASICs leads to integration
of Analog-Digital-Converters (ADCs) with complex
digital circuitry on a single chip. ADCs are a key element in
number of conversion steps performed within a complete
conversion cycle. Consequently, at the end of the conversion
cycle, i.e., when highest precision is demanded, both
mixed-signal ICs. The SAR architecture has the advantage of comparator inputs are operated near analog ground [1].
low power consumption at medium speed and medium
resolution. With the charge redistribution technique it is
possible to use self calibration to increased accuracy beyond
device mismatching limits. Compared with other popular
types of ADC architecture, successive approximation register
(SAR) ADC provides numbers of advantages. With only one
comparator in the whole system, SAR can achieve the demand
for low power consumption.
Fig. 2. SAR-ADC Based on a Charge Redistribution Principle

III. THE SAMPLE & HOLD CIRCUIT DESIGN

The Sample & Hold circuit is completely passive. It

contains just a sampling switch, a dummy switch, a sampling
capacitor and two clock buffers “Fig. 3”. The passive S/H
circuit gives a simple solution to the requirements of both
Fig. 1. Overall system Architecture of SAR-ADC small offset and wide input bandwidth of the SA-ADC to be
used in an ADC array [2].
Aniruddha Kailuke is with the Department of Electronics And
Telecommunication Engineering, Dept. DIMAT Raipur. (C.G.) INDIA
(e-mail: [email protected]).
Vrushali G. Nasre is with the Department of Electronics Engineering, Dept.
BDCOE, Sewagram Wardha. (M.H.) INDIA (e-mail: [email protected])
Dr. M.Shojaei-Baghini is with the Electrical Engineering Department at IIT,
Bombay, INDIA (e-mail: [email protected])
Rajendra.D.Kanphade is with the Department of Electronics And
Telecommunication Engineering, Dept. SSGMCE, Shegaon. (M.H.) INDIA Fig. 3. Passive Sample & Hold Circuit
(e-mail: [email protected])
 Vol. 2, 64
Proceedings of SPIT-IEEE Colloquium and International Conference, Mumbai, India

In this architecture “Fig.3”, one dummy switch is used to III. CAPACITOR ARRAY DAC
minimize clock feed through error [3]. The theory behind this
The Binary weighted Capacitor DAC or Charge scaling
technique is that if the width of M1 is one half of M0
DAC architecture is as shown in “Fig.6”.In this architecture, a
transistor, and clock wave form is fast enough then charge will
parallel array of the binary weighted capacitors is connected
cancel. The “Fig.4”, shows the schematics of Sample and
[3],[8]. The voltage output, VOUT, can be expressed as relation
Hold circuit. The value of holding capacitor is 1pF.
(6)
Where transistor M0 operating in linear region, the
condition for operating in linear region is VOUT = KVREF D (6)
VGS > VT (1)
VDS < VDSAT = VGS − VTH (2) Where, VOUT is the analog voltage output, VREF is the
reference voltage, K is a scaling factor and the digital word D
W ⎛ VDS ⎞ is given by relation (7)
I DS = K | ⎜ VGS − VTH − ⎟ VDS (3)
L ⎝ 2 ⎠ b1 b2 b3 b
Where, D= 1
+ 2 + 3 + ... + NN (7)
2 2 2 2
K = µn Cox , VGS = Gate Source Voltage,
'

N is the total number of bits of the digital word, and bi is

VDD = Supply Voltage, VT = Threshold voltage the ith coefficient and is either 0 or 1. The relation (8) gives the
K| W value of VOUT for any digital word.
gm = (VGS − VTH ) (4)
2 L
Ceq (8)
Vout = × Vref
(2C − Ceq ) + Ceq
Where, Ceq is the capacitors whose bits are set.

Fig. 6 Architecture of Charge Scaling DAC

We have implemented the architecture shown in “Fig.6”

Fig. 4. Schematic of Sample-and –Hold Circuit
using CMOS capacitors and transistor switches as shown in
The calculated value of W/L for M0 & M1 is given in Table I “Fig.7”, which is simulated using CADENCE Analog Design
The “Fig.5”, shows the simulation result of S&H circuit Environment. The values of capacitors CMSB……..CLSB are
“Fig.4”. used as a multiple of unit capacitor of 20fF. Here we are
TABLE I
assuming the unit capacitance is 20fF. The calculated values
ASPECT RATIO OF SAMPLE & HOLD CIRCUIT
of all capacitors are given in Table II.
Transistor W L
M0 2u 0.5u
M1 1u 0.5u

Fig. 5. Output Wave form for selected Sample-and Hold Circuit Fig. 7. Schematic of Charge scaling DAC
 Vol. 2, 65
Proceedings of SPIT-IEEE Colloquium and International Conference, Mumbai, India

IV. DAC SWITCH DESIGN

This design is used to reduce charge injection and clock
feed through errors by complimentary PMOS and NMOS
switches shown in “Fig.8”. All MOS transistors are operating
in linear region [4],[5].
The “Fig. 8” shows a unit capacitor connecting to VREF
when bit-1 is set (High). Switch-1 PMOS, NMOS
combination goes ON and connects to VREF.
Fig.11 INL plot for Charge Scaling DAC

The Charge Scaling DAC is simulated in 0.18um CMOS

process. The threshold voltages are 0.327 V for the nMOS and
-0.4064V for the pMOS device. From “Fig.10”, and “Fig.11”,
it is observed that a value of DNL is ±0.7LSB and INL is
Fig. 8. DAC Switch architecture
±0.8LSB respectively.

Switch-2 PMOS, NMOS combination goes ON and V. COMPARATOR

connects to ground when bit-1 is reset [4],[6]. We have The comparator is designed as a simple regenerative reset
calculated the W/L of switch transistors and is given in Table able circuit “Fig. 12”, [1],[8] followed by inverters for signal
II. level recovery. This type of comparator is use positive feed
back bi-stable element to compare two signals. The advantage
of this circuit is that there is no steady state power
consumption. The only current will be the one required by
bias circuit. The design approach is based on slew rate and
optimum propagation delay constraints. Apart from offset
related issues, the comparator is working as expected.
The bias current can be controlled by the bias transistor is
as shown in “Fig.13”, both transistor M2 and M3 is operating
in saturation region and drain current of M2 and M3 can be
given by equation (10)
K| W
(VGS − VTH ) (1 + λVDS )
2
I DS = (10)
Fig. 9. Schematic of DAC switches 2 L
We have assumed 2uA bias current to calculate the W/L
The “Fig. 9” shows implementation of DAC switch. The ratio of the transistor M2 & M3. The aspect ratios of transistor
RON resistance of PMOS and NMOS transistor can be M2 & M3 given in Table III. The complete schematic of
calculated using relation (9). comparator is as shown in “Fig.12”.
−1
⎡ W ⎤
RON = ⎢ K ' (VGS − VT ) ⎥ (9)
⎣ L ⎦

Fig.10 DNL plot for Charge Scaling DAC Fig. 12. Schematic of Regenerative Comparator
 Vol. 2, 66
Proceedings of SPIT-IEEE Colloquium and International Conference, Mumbai, India

TABLE II
DAC SWITCHES SIZES AND ON RESISTANCES
For 0.18µm Technology

Capacitor C7 C6 C5 C4 C3 C2 C1 C0
(MSB) (LSB)
Capacitor 2.56pF 1.28pF 640fF 320fF 160fF 80fF 40fF 20fF
Value
NMOS/PMO
S Switch Size 0.27/0.18 0.27/0.18 0.27/0.18 0.27/0.18 0.27/0.18 0.27/0.18 0.27/0.18 0.27/0.18
in um
RON (NMOS) 2.04K 2.04K 2.04K 2.04K 2.04K 2.04K 2.04K 2.04K
RON (PMOS) 2.96K 2.96K 2.96K 2.96K 2.96K 2.96K 2.96K 2.96K

(3). Considering VDD=1.8V and maximum current 2uA.The

calculated W/L is given in Table III.
The output stage of comparator is nothing but the inverter
for high output impedance. The aspect ratio of inverter is also
given in Table III.
The simulation result of comparator is given in “Fig.14”,
where Vin2 is used one Ramp signal as a input for simulation
and Vin1 is as a fixed input. The simulation result clearly
show that when Vin1> Vin2 and clock is low the Vout2 is low
and when clock is high then Vout2 is always high. So we
conclude that this comparator is working when clock is not
Fig. 13 Schematic of Biasing current source present.
The current ID or bias current split in to ID1 and ID2 which
flows through M4 and M5 respectively in differential pair
transistor. This two current are depends on Vin1 and Vin2.
Which can be expressed as relation (11).
1
W ⎛ 4I W ⎞2 (11)
I D = 0.5 I D + 0.25K ′ ∆V ⎜ D − ∆V 2 ⎟
L ⎝ K′ L ⎠
Where ∆V = Vin1 − Vin 2
The (regenerative) decision making circuit is the heart of
any clock comparator where two pair of transistors are used
for making decision.
Fig. 14. Output waveform of Regenerative comparator
TABLE III
TRANSISTOR SIZE
VI. SAR LOGIC DESIGN
Circuit MOS W L A successive approximation register (SAR) is a digital
M2 2u 0.4u
control circuit, which is implemented using D flip-flop. We
Bias Current
Source have designed D flip-flop using Verilog-A code. It has a
M3 0.33u 0.4u
M4 0.4u 0.18u
parallel world output, which is connected to the input of an n-
Differential
Pair M5 0.4u 0.18u bit D/A converter. The input of the SAR is a one bit digital
M6,M7 0.35u 0.18u signal, which is taken from the output of the comparator. To
Switches
M8,M9 0.27u 0.18u start the conversion, MSB in the SAR is set to 1 and all the
PMOS 3u 0.18u other bit are set to 0. If the input is higher than the output of
Inverter
NMOS 1.23u 0.18u DAC then MSB of the SAR is set to d0=1 other wise d0=0.
The decision making circuit is as shown in schematic in The content of SAR is changed to [d0 1 0…….0] in the
“Fig.12”. In the schematic both M6 and M7 are acting as a second step, and [d0 d1 1 0….0] in the third step. The
switch and this two transistor operating in linear region. And procedure of the successive approximation is continued until
similarly transistor M8 and M9 is the heart of decision making the desired accuracy is reached. The classic SAR algorithm
circuit this two transistor are also operating in linear region the flow chart is as shown in “Fig. 15” and the logic diagram of
aspect ratio of this four transistor can be calculated by relation successive approximation register is shown in “Fig.16”.
 Vol. 2, 67
Proceedings of SPIT-IEEE Colloquium and International Conference, Mumbai, India
[6] National Semiconductor Article – ABC’s of ADC’s by Nicholas
Gray, November 24 2003.
[7] V. Peluso, P. Vancorenland, A. Marques, M. Steyaert, and W.
Sansen, "A 900mV 40µW Switched Opamp ∆Σ Modulator with
77dB Dynamic Range", ISSCC Digest of Technical Papers, pp.
68-69, p. 414, 1998
[8] R. J. Baker, Li H. W., D. E. Boyce, CMOS Circuit Design, Layout,
and Simulation (IEEE Press)

X BIOGRAPHIES
Aniruddha C. Kailuke was born in India, on Aug 18,
1981. Currently he is pursuing M.E.(Digital
Fig. 15. SAR algorithm flow chart Electronics) degree from the Department of Electronics
and Telecommunication Engineering, SSGM College
of Engineering, Shegaon SGB University, Amravati.
He received BE from the Govt. College of Engg.
Amravati. He has joined DIMAT, Raipur 2006 and is
currently working as lecturer in the Department of
Electronics and Telecommunication Engineering. His
areas of research are VLSI and Embedded system Design and Analog and
Mixed Signal Design.

Vrushali G. Nasre was born in India, on 25 Jan,

1983. Currently She is pursuing M.E.(Digital
Electronics) degree from the Department of
Electronics and Telecommunication Engineering,
SSGM College of Engineering, Shegaon SGB
University, Amravati. She received BE from the
Fig. 16. logic diagram of successive approximation register
Bapurao Deshmukh college of Engg. Sewagram,
Wardha. She has joined Bapurao Deshmukh college
VII. CONCLUSION of Engg. and is currently working as lecturer in the
Department of Electronics Engineering. Her areas of
A successive approximation converter suitable for research are VLSI and Embedded system Design and Analog and Mixed
Signal Design. Specially design of Data converter.
operation at low supply voltage is designed in a standard
0.18um CMOS technology. We design all the building blocks M. Shojaei-Baghini received M.S. and Ph.D. degrees
of SAR-ADC using transistors with threshold voltages of in electronics engineering from the Sharif University
approximately 0.327V for NMOS and – 0.4064 for PMOS. of Technology, Tehran, Iran, in 1991 and 1999,
respectively, where she was the first Ph.D. graduate
The simulation results indicate that the circuit achieves 8-bit
in electronics. She received Post Doc. From IIT
monotonic conversion at high speed with differential Bombay, in 2006.She was with the Emad
nonlinearity less than 1 LSB. This device is suitable for Semiconductor Company where she was a Senior
standard CMOS technology VLSI implementation. These Analog IC Design Engineer. She has been
results are validated using CADENCE mixed signal Virtuoso Designer/Codesigner of several research/commercial
analog and mixed-signal chips. She has also designed and successfully
Analog Design Environment IC (5.0.33/5.1.41) tool. tested an ultralow-power signal conditioning chip for biomedical
applications, and has worked on the impact of technology scaling on the
VIII. ACKNOWLEDGMENT behavior of digital synchronizers and CMOS technologies for
analog/mixed-signal circuits. Dr. Shojaei was a corecipient of the third
The work is supported by VLSI & Embedded Design award on Research and Development at the 15th International Festival of
Kharazmi in 2002. Her research interests include Analog/Mixed-signal/RF
Center SSGM College of Engg. Shegaon (M.S.), India. CAD tools, theory and implementation, Analog aspects of digital circuits,
VLSI design and embedded systems. She is currently on the faculty of the
IX.REFERENCES Electrical Engineering Department at IIT, Bombay

[1] Jens Sauerbrey, Doris Schmitt-Landsiedel, Roland Thewes, “A Rajendra D. Kanphade is presently working as
0.5V, 1µW Successive Approximation ADC”, IEEE Journal of Incharge of “VLSI & Embedded System Design
Solid State Circuit, IEEE 2002. Center” of SSGMCE, Shegaon. He has joined SSGM
[2] Jiren Yuan and Christer Svensson,” A 10-bit 5-MS/s Successive College of Engineering, Shegaon in 1987. He has
Approximation ADC Cell Used in a 70-MS/s ADC Array in 1.2- been Head of the Electronics Department for the
pm CMOS”, Ieee Journal Of Solid-State Circuits, Vol. 29, No. 8, period Oct 2003 to Jan 2006. He received B.E.
August 1994. (Electronics) degrees from SGB Amravati
[3] David A. Johns and Ken Martin ,”Analog Integrated Circuit University, Amravati in the year 1987 & M.E
Design”2nd Ed. 2002 John Wiley & Sons(ASIA) Pvt. Ltd. (Electronics) from Dr. Babasaheb Ambedkar
Marathwada University, Aurangabad in the year 1993. His areas of
Singapore.
research are VLSI and Embedded system Design, Analog and Mixed
[4] P. E. Allen, Holberg, CMOS Analog Circuit Design (New York
Signal Design. Currently he is pursuing Ph. D degree from SGB Amravati
Oxford Uni. Press.2004)
University, Amravati. He is a member of IEEE, IETE and ISTE. He has
[5] Jens Sauerbrey, Doris Schmitt-Landsiedel, Roland Thewes, “A published papers in journals and Conferences.
0.5V, 1µW Successive Approximation ADC”, IEEE Journal of
Solid State Circuit, IEEE 2002.