February 28 – March 1, 2012

Low Power SoC Verification: IP Reuse and

Hierarchical Composition using UPF

Sorin Dobre Amit Srivastava

Rudra Mukherjee
Erich Marschner
Chuck Seeley
Agenda
• Introduction
• Power Aware Design and Verification
• IEEE 1801 Unified Power Format
• Need for UPF Methodology
• UPF 2.0 Methodology
– Overview
– Concepts
– Features
– Steps
– Highlights
• Summary
Introduction
Today's SoCs are
• Incredibly Complex
• Multiple Sub-Systems
• Providing Many Functions
• Increasingly Integrated
• Battery-Powered

They Must
• Minimize Power Use
– Power Management
• But Still Function Correctly
– Power Aware Verification
SnapdragonTM Mobile Processor
http://www.qualcomm.com/chipsets/snapdragon
SoC Design
• Module-Based Methodology
– Many IP blocks
– System of Subsystems
• For Base Functionality
– Divide and Conquer
– Hierarchical Composition
• For Power Management Too
– Power Intent for IP blocks
– Power Intent for Subsystems
– Power Intent for System
Power Aware Design and Verification
• Different Systems
have different power Power Domain 1 1.0 V Power Domain 2 0.8 V
management
• Power Gating PMB
Processor
• Isolation Core
RAM
• Retention
• Multi-Voltage
• Level Shifting
• Body Bias
• Forward Bias Iso_en

• Reverse Bias
• Dynamic Voltage &
Frequency Scaling 1100
• UPF provides 01100100
commands which can
express the power 000011
management
Power Domain 3 Power Domain 4
 IEEE 1801 Unified Power Format
(UPF 2.0)
• RTL is augmented with a UPF UPF
specification

Simulation, Logical Equivalence Checking, …

RTL
– To define the power architecture
for a given implementation
Synthesis

• RTL + UPF drives implementation

tools
– Synthesis, place & route, etc. UPF
Netlist
• RTL + UPF also drives power-aware
verification
Place & Route
– Ensures that verification
matches implementation

UPF
Netlist
IEEE Std 1801™-2009
6
The Need for UPF Methodology

Current Practice
• UPF is written at one go (instance-based view of design)
– Tedious and error prone
– Doesn’t scale well in an SoC environment
– Relies on full system verification for correctness

UPF Methodology Should

• Align UPF creation with design process (block/module view of design)
– Enable parallel development
• Divide and conquer approach
• Hierarchical partitioning and composition
– Promote interoperability
– Ensure success
UPF 2.0 Methodology Overview
• Two components of Power Intent
– Power Intent Interface
– Power Intent Body IP Interface UPF
• Power Intent Interface IP Body UPF
– Provides abstract interface for any
block (hard or soft)
Interface UPF Interface UPF
– Enables transparent replacement of
soft IP with hard(ened) IP Hard Soft
– Can remain stable throughout the flow Macro Macro
• Power Intent Body
– Defines the actual
behavior/implementation of the Power
Intent
IP Block
– Only depends on Interface UPFs for
external communication
– Body for soft macro integrates lower
level component interfaces
Methodology Concepts

• Recursive definition IP Interface UPF

IPIPBody UPF
Block
– Same concepts apply from at all
levels of hierarchy
Interface UPF
• Module (or model) based Interface UPF Interface UPF
IP
development
Hard Interface UPF Soft
• Support different IP flavors IP
Macro Macro
– Hard IPs IP
– Soft IPs
• IP reuse and hierarchical
composition IP Block
Methodology Features
• Top-level Power Domain defines power interface
– Supply Set handles on Power Domain represent supply interface
– Supply constraints provide constraint checking during integration
– Enables definition of IP block power states for use in larger context
• Formal parameters enable configuration/integration
– Supply set handles for supply connections and port attributes
– Logic ports for control connections
– Hides implementation specific details
• Information flows down and up the hierarchy
– Supply network structure, including embedded switches/LDOs
– Supply set constraints and power states
• Voltage constraints on input supplies
• Power states on domains powered by input supplies
• Power states on the block based on power domain states
• Consistent modeling principles for all blocks
– Hard IPs or Soft IPs
– Internal switches and LDOs
Interface Structure
Top-level power domain
create_power_domain PD \
-include_scope issh iso_en Interface UPF

Input supply sets

create_power_domain PD -update \
-supply { issh … }
Constraints
Input supply constraints ON_1V 1.0
add_power_state PD.issh \ … …
-state ON_1V {
-supply_expr { power == 1.0 … }
}

Input power control ports

create_logic_port iso_en

Top Level PD
Interface Structure
Input power control ports sw_en
create_logic_port sw_en issh iso_en Interface UPF ossh

Internal supply constraints

load_upf_protected switch_intf.upf \ R D
–params { … } –hide_globals Attributes
Constraints
Output supplies ON_1V 1.0
create_power_domain PD –update \ … …
-supply { ossh … }

Interface logic port constraints switch_intf.upf

set_port_attributes Pi –driver_supply…
set_port_attributes Pj –receiver_supply…

Top Level PD
Interface Structure
Output system states sw_en Strategies
add_power_state PD \ issh iso_en Interface UPF ossh
-state PD_Active {
-logic_expr { PD.issh1 == ON_1V … }
} R D
Attributes
Interface strategies Constraints System States
set_isolation … ON_1V 1.0 PD_Active ON_1V …
set_level_shifter … … … … … …

set_retention …

switch_intf.upf

Top Level PD
Body Structure
Internal power domains sw_en
create_power_domain PDI \
issh iso_en ossh
–elements { … }

Integrate subcomponent interfaces

Load interface definition
load_upf sub_ip.upf -scope sub_ip
Constraints System States
Connect supplies ON_1V 1.0 PD_Active ON_1V …
associate_supply_set PD.issh \ … … … … …
-handle sub_ip/PD_ip.issh

Update supply constraints

add_power_state … # correlate parent Internal PD
and child power state defns

Connect control signals

connect_logic_net iso_en \ IP Block Body UPF
-port { sub_ip/iso_en }
Body Structure
Load subcomponent bodies sw_en
(incl. switches/LDOs)
load_upf_protected … -params { … } \ issh iso_en ossh
–hide_globals

Define simstate behavior of

internal power domains
add_power_state PD.primary –update \
-state ON_1V \ Constraints System States
{ -simstate NORMAL }
ON_1V 1.0 PD_Active ON_1V …
Define internal power domain … … … … …
strategies
set_isolation …
set_level_shifter … Simstates
set_retention … Internal PD
Specify automatic connections
connect_supply_set … \ Strategies
-connect { issh pgtype }
IP Block Body UPF
Update output power states
(defined in interface)
add_power_state PD –update …
Verification of IP at different
Levels
SoC TestBench
• IP Level Verification
– Integrate in TestBench
– Perform exhaustive TestBench
verification of IP SoC

• System Level Verification

– Integrate in SoC
– Perform verification of full IP Block
SoC similar to IP Level
Verification
Methodology Highlights
• Defines constraints via add_power_state power state definitions
– Supply expressions to define voltage constraints
– Logic expressions to define control conditions and power state dependencies
• Enables constraint checking by tools
– Statically during UPF processing
– Dynamically during simulation
• Leverages UPF’s progressive refinement capability
– Allows efficient reuse and common UPF throughout the flow
– Correct integration
– Parallel development
• Combines the benefits of various approaches
– Top-down
– Bottom-up
• Leverages Tcl capabilities to increase automation
– Parameterize UPF files for greater reuse
– Reduces code by combining redundant steps
• Provides sufficient flexibility to cater to various needs
– Provides different variations in UPF for each steps
• Supports both Hard IP and Soft IP
– Goes beyond Liberty files to provide a complete power intent specification
• Enables Reusability and Portability
– Gives IP providers a standard way to deliver a comprehensive power model for an IP block
Summary
• Aligned with IP based SoC design practices
• Simplifies verification complexity
• Parallel development of system and IP
• Consistent modeling for Hard and Soft IPs
• Documents power intent of IP for reuse
• Works within UPF 2.0 constraints
Summary of Key UPF Commands
Define/Update Interface Define/Update Constraints
• create_power_domain -include_scope • add_power_state -state -supply_expr
-elements -supply -update -update
• create_logic_port
• set_port_attributes –driver_supply Define/Update/Correlate Power States
-receiver_supply • add_power_state -state -logic_expr
-update
Load UPF for Instances/Power Elements
• load_upf –scope Define/Update Simstates
• load_upf_protected -params -hide_globals • add_power_state -state -simstate
-update
Connect Supply Sets/Nets
• associate_supply_set -handle Define/Update Strategies
• connect_supply_set -connect • set_isolation …
• connect_logic_net -port • set_level_shifter …
• set_retention …
THANK YOU

Amit Srivastava ([email protected] )

Rudra Mukherjee ( [email protected])
Erich Marschner ( [email protected] )
Chuck Seeley ( [email protected] )
Sorin Dobre ( [email protected] )
Memory (Hard IP)
Interface UPF - part 1
1. #Top level system PD -state ON_Min {
create_power_domain pd_SRAM -include_scope -supply_expr {
2. # INPUT Supply Set Handles ( pd_SRAM.primary.power == { FULL_ON, 0.5 } )
create_power_domain pd_SRAM -update \ && ( pd_SRAM.primary.ground == FULL_ON )
-supply { core_ssh } \
}
-supply { primary }
}\
3. # INPUT logic Ports – None
4. # INPUT Supply Set CONSTRAINTS -state OFF_STATE {
add_power_state pd_SRAM.primary \ -supply_expr {
-state ON_Svs { ( pd_SRAM.primary.power == OFF )
-supply_expr { }
( pd_SRAM.primary.power == { FULL_ON, 0.7 } ) }
&& ( pd_SRAM.primary.ground == FULL_ON )
}
}\
-state ON_Nom {
-supply_expr {
( pd_SRAM.primary.power == { FULL_ON, 0.8 } )
&& ( pd_SRAM.primary.ground == FULL_ON )
}
}\
-state ON_Turbo {
-supply_expr {
( pd_SRAM.primary.power == { FULL_ON, 1.0 } )
&& ( pd_SRAM.primary.ground == FULL_ON )
}
}\
Memory (Hard IP)
Interface UPF - part 2
add_power_state pd_SRAM.core_ssh \ 5. # INTEGRATE internal supplies – None
-state ON_Svs_Normal { 6. # OUTPUT Supply Set Handle – None
-supply_expr { 7. # OUTPUT System States
( pd_SRAM.core_ssh.power == { FULL_ON, 0.855 } ) add_power_state pd_SRAM \
&& ( pd_SRAM.core_ssh.ground == FULL_ON ) -state PD_SRAM_Active {
} -logic_expr {
}\ ( ((pd_SRAM.primary == ON_Turbo) &&
-state ON_Turbo { (pd_SRAM.core_ssh == ON_Turbo))
-supply_expr { || ((pd_SRAM.primary == ON_Nom) &&
( pd_SRAM.core_ssh.power == { FULL_ON, 1.0 } ) (pd_SRAM.core_ssh == ON_Svs_Normal))
&& ( pd_SRAM.core_ssh.ground == FULL_ON ) || ((pd_SRAM.primary == ON_Svs) && (pd_SRAM.core_ssh
== ON_Svs_Normal))
}
)
}\
&& (slp1 == 1'b0)
-state ON_Min {
&& (slp2 == 1'b0)
-supply_expr {
&& (clamp_mem == 1'b0)
( pd_SRAM.core_ssh.power == { FULL_ON, 0.65 } )
}
&& ( pd_SRAM.core_ssh.ground == FULL_ON )
}\
}
}\
-state OFF_STATE {
-supply_expr {
( pd_SRAM.core_ssh.power == OFF )
}
}
Memory (Hard IP)
Interface UPF - part 3
-state PD_SRAM_Dormant { -state PD_SRAM_OFF {
-logic_expr { -logic_expr {
(((pd_SRAM.primary == ON_Turbo) && (pd_SRAM.core_ssh ( (pd_SRAM.primary == OFF_STATE) &&
== ON_Turbo)) (pd_SRAM.core_ssh == OFF_STATE)
|| ((pd_SRAM.primary == ON_Nom) && ) || ( (slp1 == 1'b1) && (slp2 == 1'b1) &&
(pd_SRAM.core_ssh == ON_Svs_Normal)) (clamp_mem == 1'b0) )
|| ((pd_SRAM.primary == ON_Svs) && (pd_SRAM.core_ssh }
== ON_Svs_Normal))
}
|| ((pd_SRAM.primary == ON_Min) && (pd_SRAM.core_ssh
== ON_Min)) 8. # Port Constraints
) set_port_attributes -ports { clamp_mem } \
&& (slp1 == 1'b1) -receiver_supply pd_SRAM.core_ssh
&& (slp2 == 1'b0) set_port_attributes -domains { pd_SRAM -applies_to inputs } \
&& (clamp_mem == 1'b0) -exclude_ports { clamp_mem } \
} -receiver_supply pd_SRAM.primary
}\ set_port_attributes -domains { pd_SRAM -applies_to outputs } \
-state PD_SRAM_Retention { -driver_supply pd_SRAM.primary
-logic_expr { 9. # Interface Rules
(pd_SRAM.primary == OFF_STATE) set_isolation iso_data -domain pd_SRAM \
&& (pd_SRAM.core_ssh == ON_Min) -elements [ find_objects . -pattern {din*,dout*, ad* } -object_type
port ] \
&& (clamp_mem == 1'b1)
-isolation_signal { slp1 clamp_mem } -isolation_sense high \
}
-clamp_value latch
}\
set_isolation iso -domain pd_SRAM \
-elements {slp1 slp2 } \
-isolation_signal clamp_mem -isolation_sense high \
-clamp_value latch
Memory (Hard IP)
Body UPF
1. # Internal PDs – None as its Hard Macro
2. # INTEGRATE sub-component – None
3. # LOAD body UPF of sub-component – None
4. # Define simstates – Not required as it’s a hard macro
5. # Specify Internal Rules – Not required
6. # Automatic Connection Semantics
# This information optional if the attributes are from liberty
set_port_attributes -ports { vddmx } -pg_type pg_sram_array
set_port_attributes -ports { vddx } -pg_type primary_power
set_port_attributes -ports { vss0 } -pg_type primary_ground

connect_supply_set pd_SRAM.primary \
-connect { power {primary_power } } \
-connect { ground {primary_ground} }

#since ground is common, hence not connecting it again

connect_supply_set pd_SRAM.core_ssh \
-connect { power {pg_sram_array} }
7. # UPDATE System States – Not needed
Decoder (Soft IP)
Interface UPF - 1
1. # Top level PD 5. # INTEGRATE Internal Supplies
create_power_domain pd_DEC -include_scope load_upf_protected upf/switch_interface.upf -params {
2. # INPUT Supply Set Handles {sw_op_sset ss_DEC_switchable}
create_power_domain pd_DEC -update \ {sw_ip_sset pd_DEC.aon_ssh}
-supply { aon_ssh } \ {sw_en En1}
-supply { sram_ssh } {inp_ss_state_list {ON_1d2V}}
3. # INPUT Control Ports } -hide_globals
create_logic_port En1 6. # OUTPUT Supply Set Handles
create_logic_port slp_en create_power_domain pd_DEC -update \
4. # INPUT Supply Constraints -supply { primary ss_DEC_switchable }
add_power_state pd_DEC.aon_ssh \ 7. # OUTPUT System States
-state ON_1d2V { add_power_state pd_DEC \
-supply_expr { -state MOD_S1 { -logic_expr { <based on supply set handle states>
( pd_DEC.aon_ssh.power == { FULL_ON, 1.2 } ) }}\
&& ( pd_DEC.aon_ssh.ground == FULL_ON ) -state MOD_S2 { -logic_expr { <based on supply set handle states>
} }}\
} …
add_power_state pd_DEC.sram_ssh \ 8. # ** INTERFACE: PORT Constraints
-state ON_Svs_Normal { set_port_attributes …
-supply_expr {
( pd_DEC.sram_ssh.power == { FULL_ON, 0.855 } ) 9. # ** INTERFACE: Isolation/Level Shifter/Retention of
INTERFACE PD
&& ( pd_DEC.sram_ssh.ground == FULL_ON )
set_retention …
}
set_isolation …
}
set_level_shifter …
…
Decoder (Soft IP)
Body UPF - 1
upf_version 2.0 ;# optional # ** BODY: LOAD BODY of sub-component IP and Internal Supplies
set_design_top MOD ;# body will usually apply to a single module load_upf_protected switch_body.upf -params {
type {sw_op_sset ss_DEC_switchable}
{sw_ip_sset pd_DEC.aon_ssh}
# ** BODY: DEFINE Internal Power Domains {sw_en En1}
# create_power_domain intPD1 … {inp_ss_state_list {ON_1d2V}}
{domain pd_DEC}
# ** BODY: INTEGRATE Sub-component IP and Internal Supplies } -hide_globals

# ** INTEGRATE: LOAD Interface UPF # ** BODY: DEFINE SIMSTATE BEHAVIOR for Internal and INTERFACE
load_upf_protected <upf for an instance> -scope <scope of the PDs
instance> # ** BODY: Specify ISOLATION, LEVEL SHIFTER and Retention with
controls connected
# ** INTEGRATE: CONNECT Supplies # ** BODY: Automatic connections for hard macros
associate_supply_set pd_DEC.ssh1 -handle <ssh of the instance PD> set_port_attributes -ports { is_hd_sensor_i/vdd } -pg_type
… primary_power
set_port_attributes -ports { is_hd_sensor_i/vss } -pg_type
# ** INTEGRATE: UPDATE Supplies Constraints primary_ground
# add_power_state pd_DEC.sram_ssh –update … connect_supply_set pd_DEC.aon_ssh \
-elements is_hd_sensor_i \
# ** INTEGRATE: CONNECT Logic Controls -connect { power {primary_power} } \
# NA -connect { ground {primary_ground} }

# ** BODY: Update SYSTEM STATES based on sub-component IPs