Cache Memory Special very high-speed memory that acts as a buffer between RAM and the CPU. Used to speed up and synchronizing with high-speed CPU, An extremely fast memory type Holds frequently requested data and instructions so that they are immediately available to the CPU when needed. Technique of storing a copy of data temporarily in rapidly accessible storage media (also known as memory) local to the CPU and separate from bulk storage. a Cache MemoryCache Memory Costlier than main memory or disk memory but economical than CPU registers. Used to reduce the average time to access data from the Main memory. Smaller and faster memory ( 5 to 10 times) which stores copies of the data from frequently used main memory locations. Instructions of few localized area of the program are repeatedly executed. while remainder of program is accessed relatively less. This phenomenon is referred as Locality of ReferenceLevels of Cache Memory Level 1(L1) Cache: e@ Fastest cache and usually comes within the processor chip itself e The LI cache typically ranges in size from 8KB to 64KB and uses the high- speed SRAM (static RAM) instead of DRAM (dynamic RAM). e Referred as internal cache or primaryLevels of Cache Memory Level 2(L2) Cache: Level 3(L3) Cache: e This cache is larger but slower in @ An enhanced form of memory speed than L1 cache: present on the motherboard of the @ Stores recently accessed information computer. & also known as secondary cache, e Used to feed the L2 cache. e [2 cache comes between Ll and e Faster than the system’s main RAM and is bigger than the primary memory, but slower than L2 cache (typically 64KB to 4MB). cache. e Having more than 3 MB of storage nitPlacement of Cache Memory in processorMapping Function Processor issues a Read request. a block of words is transferred from the main memory to the cache. one word at a time. Subsequent references to the data in this block of words are found in the cache. At any given time, only some blocks in the main memory are held in the cache. Which blocks in the main memory are in the cache is determined by a “mapping function”.Mapping Function When the cache is full. and a block of words needs to be transferred from the main memory. some block of words in the cache must be replaced. This is determined by a “replacement algorithm”. Block Transfer Word Transfer mo aeiG i © 5 Cache Operation . CPU requests content of memory location. Checks Cache for this data If present get it from there(Fast) If not present. read required block from main memory to cache. Then deliver from cache to CPU. Cache includes tags to identify which block of main memory is in each cache slot.Hit Ratio Cache Hit Ratio is the ratio of the number of cache hits to the number of lookups, usually expressed as a percentage. Depending on the nature of the cache. expected hit ratios can vary from 60% to greater than 99%, + Cache Hit = Desired data is in current level of cache * Cache Miss = Desired data is not present in current level. * When a cache miss occurs. the new block is brought from the lower level into cache. If cache is full a block must be evicted Number of cache hits we (Number of cache hits + Number of cache misses) — =Cache hit ratioHit Ratio-Problem Calculate the average access time of memory for a computer with cache access time of 100ns, a main memory access of 1000ns and a hit ratio is 0.9Hit Ratio-Problem Calculate the average access time of memory for a computer with. L_cache access time of 100ns. a main memory access of 1000ns and a hit ratio is 0.9 — ———————— ——— Fo + /. F data is Purd Gche = (o-ax lens ee (1-0-9) x loons + looses = Joys + loysWriting into the Cache When memory write operations are performed, CPU first writes into the cache memory. These modifications made by CPU during a write operations, on the data saved in cache, need to be written back to main memory or to auxiliary memory. These two popular cache write policies (schemes) are: ¢ Write-Through ¢ Write-BackWriting into the Cache Two popular cache write policies (schemes) are: Write-through The main memory is updated each time the CPU writes into cache. Pros: Avoid coherency issues between levels. Cons: Poor performance if next level of hierarchy is slow or if many, repeated accesses Write-back Only the cache memory is updated during a write operation. and the updated locations in the cache memory are marked by a flag. The words are removed from the cache time to time to make room for a new block of words. * Pros : Fast if many repeated accesses * Cons : Coherency issues