IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 53, NO.

8, AUGUST 2018 2389

Low-Power Noise-Immune Nanoscale Circuit

Design Using Coding-Based Partial MRF Method
Yan Li, Student Member, IEEE, Yufeng Li , Student Member, IEEE, I-Chyn Wey, Jianhao Hu, Member, IEEE,
Fan Yang , Member, IEEE, Xuan Zeng , Member, IEEE, Xiaoxue Jiang , Student Member, IEEE,
and Jie Chen , Fellow, IEEE
Abstract— Reliability is one of the major concerns for ultralow past decades. One of the most important attributes of nanoscale
power circuit designs. Markov random field (MRF) techniques devices is their low-power consumption. However, when the
have been applied to logic circuits to resist random noise when supply voltage is scaled down, the energy difference between
operating under ultralow supply voltage or sub-threshold voltage.
Although conventional MRF networks can be easily mapped onto logic states is comparable to the surrounding noise, rendering
simple logic circuits, it becomes difficult when the circuits are the resulting circuit vulnerable to operational uncertainty and
large and complex. In this paper, we present a general coding- logic failures [1]. These signal errors are dynamic in nature,
based partial MRF (CPMRF) method for multi-logic operations occurring anywhere in the circuit, and are difficult to detect
in one basic unit, which is referred to as a CPMRF pair. by regular testing methodologies [1]. Such errors are often
A CPMRF pair saves circuit area by sharing a common MRF
network. It also inherits noise immunity from the MRF theory referred to as “dynamic errors.” As the dimensions of devices
while obtaining noise immunity from the coding structure as a scale down further into the nanometer realm, one of the
combination of robust “1s” and “0s.” The resulting architectures major challenges we will need to confront is the increasing
become more cost effective than conventional ones. To validate prevalence of dynamic errors in nanoscale logic circuits.
the performance of our proof-of-concept design, we fabricated An error-free logic operation is assumed in the design
a carry-lookahead adder implemented by the proposed CPMRF
pairs using IBM 130-nm CMOS technology. Measurement results of conventional CMOS digital circuits and systems.
indicate that the CPMRF CLA can achieve high noise tolerance It implies that conventional circuit designs mainly focus
with 20% improvement while occupying 37.7% less area and on the data transmission errors due to capacitive–inductive
reducing power consumption by 93% compared with the master- crosstalk [2], [3], ground bounce, and IR drops [4]. However,
and-slave MRF CLA design. this assumption is not applicable to circuit designs in the
Index Terms— Carry-lookahead adder, clique energy, low nanoscale realm when an ultra-low supply voltage is
power, Markov random field (MRF), noise immunity, proba- adopted. Because the uncertainty in signal faults is inherent
bilistic design.
in nanoscale computing systems, conventional design methods
I. I NTRODUCTION (crosstalk [5], ground bounce [6], and IR drops [7]) cannot
effectively solve the random noise problems, which are
T HE continuous miniaturization of electronic components
has enabled rapid growth of microelectronics over the intrinsic to nanoscale VLSI systems [8], [9]. Implementing
reliable Boolean functions by using noisy logic gates
Manuscript received December 30, 2017; revised March 9, 2018 and was first proposed by Von Neumann [10]. With noisy
April 26, 2018; accepted April 26, 2018. Date of publication May 25, 2018;
date of current version July 20, 2018. This paper was approved by Associate gates, conventional noise-immunity techniques, such as
Editor Vivek De. This work was supported in part by the Natural Sciences and triple modular redundancy (TMR) [11], will add hardware
Engineering Research Council of Canada, in part by Thousand Talents Initia- redundancy to handle faults. However, due to these logic gates
tive for the City of Shanghai, China, in part by the National Science Council,
Taiwan, under Grant MOST105-2218-E-002-024 and Grant MOST106-2221- also being prone to errors, intrinsic noise can significantly
E-182-069, and in part by the Chang Gung Medical Research Program under interfere with individual redundant modules, and thus noisy
Grant BMRPA77. (Yan Li and Yufeng Li are co-first authors.) (Corresponding signals often lead to incorrect results of the voters in TMR.
author: Jie Chen.)
Y. Li and J. Hu are with National Key Laboratory of Science and Technology As a result, the TMR-based structures cannot effectively solve
on Communications, the University of Electronic Science and Technology the random intrinsic noise that often occurs in nanoscale
of China, Chengdu 611731, China (e-mail: [email protected]; circuits.
[email protected]).
Y. Li, X. Jiang, and J. Chen are with the Department of Elec- Recently, three new alternative and innovative probabilistic
trical and Computer Engineering, University of Alberta, Edmonton, techniques were proposed. They are stochastic computa-
AB T6G 2W3, Canada (e-mail: [email protected]; [email protected]; tion (SC) [12]–[18] at the number representation level,
[email protected]).
I-C. Wey is with the Electrical Engineering Department, Chang Gung algorithmic noise tolerant (ANT) techniques [19]–[21] at the
University, Taoyuan 33302, Taiwan, and also with the Department of algorithmic level, and probabilistic CMOS (PCMOS) [22]
Neurology, Linkou Chang Gung Memorial Hospital, Taoyuan 33305, Taiwan at the circuit level. SC is an un-weighted number representa-
(e-mail: [email protected]).
F. Yang and X. Zeng are with the Department of Microelectronics, tion, which represents a number by a bitstream. For example,
Fudan University, Shanghai 200433, China (e-mail: [email protected]; 0.3 is represented as a stochastic bitstream “1, 0, 0, 1, 1,
[email protected]). 0, 0, 0, 0, 0” where the probability of the occurrence of
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. bit “1” represents the value. Although stochastic representation
Digital Object Identifier 10.1109/JSSC.2018.2834464 can be implemented by much simpler logic compared with
0018-9200 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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2390 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 53, NO. 8, AUGUST 2018

traditional representation, the propagation delay of SC systems tion and time delay [34]. Meanwhile, the traditional MRF
is proportional to the length of bitstreams, which renders such design pays attention to the structure of each logic oper-
techniques unsuitable for high-speed VLSI design. In addition, ation, which limits this method for further VLSI structure
a few SCs have been implemented for noise-tolerant circuit design.
designs under an ultra-low supply voltage. Based on ANT, In this paper, we propose a coding-based partial
the design in [19] focuses on low-complexity and reduced MRF (CPMRF) method for multi-logic operations. First, we
precision redundancy (RPR) modules to compensate for errors divide the MRF clique energy, U , into two subsets {U0 , U1 }.
in the main computing unit. This technology is power efficient Here, U0 is the clique energy corresponding to logic
since the main unit operates under a low supply voltage, while output “0,” while U1 is for logic output “1.” In logic circuits,
the RPR modules are supplied at a regular voltage. If the main there arise many instances of asymmetric gates, including
unit and the RPR modules work under the same ultra-low NAND , NOR , AND , as well as OR gates. For example, a NAND
supply voltages, dynamic errors can influence both the main gate has an asymmetric probability distribution for its output
unit and the RPR modules such that the performance loss (three logic “1” outputs versus one logic “0” output) when
cannot be compensated for. Another probabilistic technique, its inputs satisfy the Bernoulli distribution. We discovered
PCMOS, is a model used in noise-tolerant designs [22]. Its that some asymmetric gates can be paired with others such
performance depends on the chosen noise model. However, as an AND – NOR pair to complement the clique energy with
there is no prior knowledge about the distribution of intrinsic each other, referred to as complementary pairs. On the
noise in nanoscale circuits. Therefore, such a model is not contrary, there are non-complementary gate pairs, such as a
suitable for noise tolerant designs. NOR – NOR pair. Based on these observations, we propose a
In contrast to the above approaches, Markov random CPMRF method using complementary gate pairs and non-
field (MRF) theory is applied on circuit designs as a complementary gate pairs. In the previous work, a partial-
probabilistic-based technique to deal with the issue of noise. clique-energy MRF design [35] was carried out to investigate
Recently, many researchers have adopted this approach in the its area efficiency. However, it has some limitations: 1) it
circuit design to handle dynamic errors [23]–[34]. In the only considers designs for complementary gate pairs; 2) output
probabilistic framework, it is unreasonable to assume each logic operations must correspond to input logic operations; and
logic value, as each node in a real circuit can stay correct 3) it does not summarize a general mapping method. Aiming
at all times. What we can expect is that the probability to overcome these limitations, the proposed CPMRF, which
distribution of these values will have the highest likelihood combines the idea of partial-clique-energy with the idea of
in a correct logic state. The appropriate mathematical frame- strong/weak outputs implemented by the coding structures,
work according to the analysis is MRF, which optimizes achieves: 1) general mapping methods for both complementary
the values of a large set of random variables so that their and non-complementary gate pairs and 2) multi-logic opera-
overall joint probability is a global maximum. In a logic tions not limited to input logic operations. Therefore, the prime
circuit, hundreds of internal logic signal paths exist from the novelty of the proposed CPMRF method lies in offering:
inputs to the outputs. Only one set of variable assignments 1) a general design method to achieve multi-logic operations
has the highest probability of being correct, and the correct by specially designed coding structures for partial MRF gate
set corresponds to the optimum setting. The propagation of pairs and 2) large area and power savings while maintaining
logic states through the network is orchestrated such that high noise immunity.
the distribution of each variable is at its local probability The rest of this paper is organized as follows. Section II
maximum in order to achieve the correct logic values at the clearly introduces the MRF theory and previous MRF circuit
output. Through this design paradigm, MRF circuits can designs. Section III presents a general CPMRF design method
achieve high noise immunity under ultra-low supply volt- for complementary gate pairs and non-complementary gate
ages [24]. However, there exist significant shortcomings of pairs. In Section IV, we implement an 8-bit CPMRF carry-
traditional MRF designs due to its complex hardware architec- lookahead adder using the IBM 130-nm process to prove the
ture. MRF-based circuits often require 20 times the number of effectiveness of the proposed method. This paper is concluded
transistors as compared to traditional circuit implementations. in Section V.
To minimize this shortcoming, area-performance optimization
becomes the major challenge for using MRF-based designs. II. MRF-BASED C IRCUIT D ESIGN M ETHODOLOGY
An area-efficient MRF structure [31] and a master-and-slave The MRF circuit design is based on the MRF theory [27].
(MS) [28] MRF can achieve about 50% area saving compared It involves the mapping from a multi-level Boolean logic
to the original MRF circuits. However, the MS-based units circuit to an MRF network followed by the mapping from an
experience a performance loss as studied in [33]. An area- MRF network to MRF standard cells. In this section, we will
sharing cyclic structure was proposed in [30] having high area introduce some basic concepts and the mapping processes
efficiency with shared structures. Unfortunately, the structures involved in the MRF design.
cannot implement the complete MRF clique energy functions,
and thus the system performance is limited. A hardware-
efficient feedback-based design combines the idea of MRF A. Markov Random Field Theory
and the Schmitt trigger to enhance the noise immunity Let X = {x 0 , x 1 , . . . , x n } be a set of random
based on the MS design, but it increases power consump- variables. A graph example is shown in Fig. 1, where

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LI et al.: LOW-POWER NOISE-IMMUNE NANOSCALE CIRCUIT DESIGN USING CPMRF METHOD 2391

Fig. 1. Graph example of MRF.

Fig. 2. Logic circuit.

X = {x 0 , x 1 , . . . , x 5 }. These variables are connected to

each other either directly or indirectly. The subset of X,
in which variables are directly connected with each other,
is defined as a clique [24]. In Fig. 1, cliques are {x 0 , x 1 },
{x 1 , x 2 , x 3 }, and {x 3 , x 4 , x 5 }. Variables in a clique show Fig. 3. MRF circuits. (a) MRF inverter [24]. (b) MRF NAND [24].
obvious dependence marked by edges between two variables (c) Area-efficient MRF NAND [31]. (d) MS MRF NAND [28].
in Fig. 1. In these subsets, one directly connected variable
beside the other is called a neighbor [24]. x 0 is a neighbor
TABLE I
of x 1 . The probability of an MRF variable depends only on its
E NERGY T RUTH TABLE OF AN I NVERTER
neighborhood. These variables form an MRF if the collections
of the random variables satisfy positivity, which means the
probability of a variable can be neither negative nor zero and
markovianity, which means that a variable must be indepen-
dent of others except for those in its neighborhood [27].

B. Mapping a CMOS-Circuit to an MRF Network

The transformation from multi-level CMOS circuits to an
MRF network is as follows.
1) Variables in an MRF graph correspond to input/output
nodes in a logic circuit with the logic values “0” or “1.”
C. Mapping an MRF Network Onto an MRF-Based Circuit
2) Edges in an MRF graph represent the dependence
between the input/output nodes corresponding to a vari- High-performance basic MRF logic gates are designed to
able and its neighborhood in a clique. obtain an MRF-based circuit mapped from an MRF network.
Followed by the above rules, a logic circuit, shown Note that we can maximize the joint probability by minimizing
in Fig. 2, can be mapped to an MRF network in Fig. 1. the clique energy instead, as shown in (1). The rules of an
The input/output nodes x 0 , x 1 , . . . , x 5 correspond to the same MRF-based design are intended to satisfy the requirement that
variables in Fig. 1. The input/output nodes in a logic gate form the clique energy of correct logic states should be lower than
a clique in Fig. 1. Three logic gates represent three cliques. that of incorrect logic states as the following points.
After the transformation, we can apply the MRF theory to 1) The energy truth table is formed by the clique energy
the nodes in a circuit. According to the Hammersley–Clifford terms of the valid/invalid input–output states. Assume
theorem, the joint probability for the whole set of nodes in a that f (x 0 , x 1 , . . . , x n ) is an operation function for the
circuit is the product of all clique energy functions [24] input X = {x 0 , x 1 , . . . , x n } in the same clique, f = 0
 1   when the MRF network operates incorrectly, otherwise
−Uc (x c )
P(X) = exp (1) f = 1.
Z kb T 
c∈C 2) Let the clique energy Uc (x c ) = − i fi (x 0 , x 1 , . . . , x n )
where Z is a normalization constant, C is the set of all cliques, be the entire state (i represents the different input
Uc (x c ) represents the clique energy for a clique x c , and kb T values, for example, i = 0 refers to {0, 0, . . . , 0}) of an
is the thermal energy. Note that the reliability of a circuit operation, where the design of the MRF-based elements
can be translated to the likelihood of the joint probability for depends on the function Uc (x c ), where f i = 1.
all correct states, which is represented by their clique energy The energy truth table of an inverter [see Fig. 3(a)] is shown
in (1). Thus, maximizing the reliability of a circuit is analogous in Table I, including its correct and incorrect states. The energy
to achieving the highest joint probability for all correct states function U (x, y) = −(x̄ y + x ȳ) represents the clique energy
corresponding to the lowest clique energy [23]. of an inverter (the rules of symbolic Boolean logic in terms of

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2392 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 53, NO. 8, AUGUST 2018

TABLE II
T RUTH TABLE OF AN AND – NOR PAIR

Fig. 4. Local mapping-based MRF MUX.

algebraic operations are shown in [25]). In Fig. 3(a), the upper

NAND can implement the clique energy function x  and the
lower NAND is designed for the implementation of x y  . These
two NAND gates help strengthen the input and output signals.
Although there are feedback loops in the MRF circuit design,
the structures are still considered to be combinational logic,
since the output only depends on its present inputs. Obviously,
the feedback loop in combinational noise-tolerant logic is a
characteristic of the MRF-based design, which comes from the
clique energy function. The MRF-NANDshown in Fig. 3(b) is
a direct hardware implementation based on the clique energy
as follows [24]:
U (x 1 , x 2 , y) = −(x 1 x 2 y + x 1 x 2 y + x 1 x 2 y + x 1 x 2 y). (2)
Fig. 5. Compensation clique energy-based structure for an AND – NOR pair.
The MRF-NAND structure is modified based on an equivalent
transformation of clique energy function [28]
U (x 1 , x 2 , y) = −[(x 1 + x 2 )y + x 1 x 2 y]. (3) and one of the U P−NOR terms x 1 · x 2 · yNOR to represent the
lost clique energy of AND
Fig. 3(c) shows a cost-effective structure of an MRF-NAND
based on the equivalent transformation in (3). The MS MRF- UAND = U P−AND − x 1 · x 2 · yNOR . (7)
NAND in Fig. 3(d) separates the truth table into two groups,
and it is the most area-efficient implementation compared with The clique energy to represent the lost energy terms of an
AND – NOR pair is
the others. Nevertheless, the complexity of MRF elements is
still a bottleneck for an MRF-based VLSI design. For example, UC−AND−NOR = −x 1 · x 2 · yNOR − x 1 · x 2 · yAND . (8)
the MRF-based MUX in Fig. 4 consumes 6∼12 times the area
of a traditional MUX. Clearly, there is an issue of excessive Equation (8) is just an addition of the lost clique energy of
area required for a complex logic design, since each logic gate NOR in (6) and the lost clique energy of AND in (7). In (8),
should be replaced by a corresponding MRF version in the the term x 1 · x 2 · yAND of AND can also be regarded as a
circuit. compensation for the lost clique energy of NOR, while the
term x 1 · x 2 · yNOR of NOR can be regarded as a compensation
III. C ODING -BASED PARTIAL MRF M ETHODOLOGY for the lost clique energy of AND. Therefore, we simplify the
joint clique energy of an AND – NOR pair based on (6)–(8),
In this section, a CPMRF method is proposed based on as shown in Table II
sub-clique energy where the clique energy is asymmetric.
First, a PMRF AND–NOR pair is proposed as an example for UAND−NOR = −(x 1 · x 2 · yNOR + x 1 · x 2 · yAND )
complementary pairs. − (x 1 · x 2 · yNOR + x 1 · x 2 · yNOR )
According to the truth table of an AND–NOR pair in Table II,
− (x 1 · x 2 · yAND + x 1 · x 2 · yAND )
the partial clique energy U p of AND is
= UC−AND−NOR − (x 1 ⊕ x 2 ) · yNOR
U p−AND (x 1 , x 2 , y) = −x 1 · x 2 · y − x 1 · x 2 · y − x 1 · x 2 · y
− (x 1 ⊕ x 2 ) · yAND (9)
= −(x 1 · x 2 ) · y (4)
Based on (8), a clique energy-based structure used to compen-
while the partial clique energy of NOR is sate the lost terms in AND and NOR is shown in Fig. 5. We add
the following coding unit in Fig. 6 to the compensation clique
U P−NOR (x 1 , x 2 , y) = −x 1 · x 2 · y − x 1 · x 2 · y − x 1 · x 2 · y
energy-based structure, which confers advantages based on the
= −(x 1 + x 2 ) · y. (5) following analysis. From the energy viewpoint, the coding unit
We can use one of the U P−AND terms x 1 · x 2 · yAND to represent achieves the full NOR – AND joint clique energy in (9). Gates g1
the lost clique energy of NOR and g2, which form the feedback structure, can implement the
compensation function UC−AND−NOR . Gates g4 and g5 shown
UNOR = U P−NOR − x 1 · x 2 · yAND (6) in Fig. 6 are proposed for the corresponding clique energy

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LI et al.: LOW-POWER NOISE-IMMUNE NANOSCALE CIRCUIT DESIGN USING CPMRF METHOD 2393

Fig. 8. Coding-based structure for a complementary AND – XOR pair.

Fig. 6. Coding-based structure for a complementary AND – NOR pair with
two logic operations.

Fig. 9. (a) Mixed mapping MUX. (b) CPMRF pair-based MUX structure.

elements. Therefore, the probability match can influence the

performance of the two-level structure. Both t1 and t2 shown
Fig. 7. MS [28] structure with only one kind of logic. in Fig. 7 are operated by NOR and NAND gates, which then
have strong bits and weak bits. If the strong bits out of the
first level are connected to the higher noise-tolerant input pair
(x 1 ⊕x 2 )·yNOR and (x 1 ⊕x 2 )·yAND , respectively. From the prob- of NAND – NAND feedback structure, the effect of noise will be
ability viewpoint, the coding unit can strengthen the input bits. weakened again. However, if the weak bit (such as the bit “1”
The structure in Fig. 7 is the traditional MS-MRF structure, of t2 ) is connected to the weak input pair of next level such as
which has an MS structure (NAND – NAND feedback), while {11} for g2 , the effect of noise will be amplified. Therefore,
the design only considers the energy relation while neglecting the MS structure experiences significant performance losses
the probability match between the master and the feedback when the output of g2 is “0” since this bit overlaps two
loop. Therefore, there is a performance loss according to the cascade weaknesses. We also propose a coding-based structure
study [33]. for a complementary asymmetric and symmetric AND – XOR
As we mention in the introduction, a gate, such as a NAND pair in Fig. 8, which can achieve the functions of the carry bit
gate, has an asymmetric output property, characterized by and the sum bit of a half adder. The coding structure shown
different output correct probabilities for being digital “1” in Fig. 8 helps the weak bit “1” of t1 and t2 transfer to strong
and “0” when the input follows the Bernoulli distribu- bit “0” of tc1 and tc2 and prevent the two-cascade weakness
tion. Assume “strong” represents high correct probability from overlapping. Therefore, the proposed structure has higher
and “weak” represents low correct probability. For example, noise tolerance than the conventional MRF structures. Based
the inputs of a NANDgate are x 1 , x 2 ; the output is y; under on the above examples for AND – XOR and AND – NOR , a large
the presence of noise, the probability of an input being weak number of complementary modules are possible: NAND–OR,
is pw (0 ≤ pw ≤ 0.5), while the probability of the input being AND – XOR ( XNOR), OR– XOR ( XNOR), NAND – XOR ( XNOR),
strong is 1− pw . Assume that the symbol p(y|x 1 x 2 ) represents NOR– XOR ( XNOR); NAND – AND, NOR– OR, and XOR– XNOR,
the conditional probability of output y being strong are self-complementary pairs designed by logic transforma-
tion. In the same complementary module, two logic operations
p(1|00) = 1 − pw
2
can share a common MRF network.
p(1|01) = 1 + pw
2
− pw The above complementary pairs can also construct a
p(1|10) = 1 + pw
2
− pw MUX-AND block for multiple logic operations used in fast
p(0|11) = (1 − pw )2 tree-based carry-lookahead adders for selecting the carry bit.
This case study extends the two inputs to three-input
p(1|00) ≥ p(1|01) = p(1|10) ≥ p(0|11). (10) AND – NOR pairs for MUX function based on the following
Therefore, for such input pairs, the NAND has higher noise transformation:
tolerance for being {00, 01, 10} rather than {11}. In terms ymux = x a · x s + x b · x s = x a · x s + x b + x s . (11)
of the output bits, the NAND has a higher noise tolerance
when being “1” than “0.” For an MS structure, the master Both g1 and g2 shown in Fig. 9(a) can achieve x a · x s
unit and the slave unit are both composed of asymmetric and x b + x s in (11) by the proposed coding-based AND – NOR

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2394 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 53, NO. 8, AUGUST 2018

TABLE III
T RANSISTOR C OUNT C OMPARISON FOR D IFFERENT S TRUCTURES

Fig. 10. Non-complementary CPMRF pair: NOR – NOR, where S1 W2 refers

to strong for the first level and weak for the second level achieving the two
cascades complementary instead of weaknesses overlap.

Compared with the MRF-Schmitt design [34], it saves at least

19.1% of transistors. The area saving in the proposed method
benefits from the shared MRF network in a gate pair for
multiple logic operations. The noise-tolerant performance of
the proposed method for a MUX, shown in Fig. 11, was
investigated in an HSPICE simulation, where the performance
was evaluated by measuring the bit error rate (BER) under
varying input signal-to-noise ratios (SNRs). The simulation
was operated at 0.25-V supply voltage using a 130-nm
BSIM4 model. Additive white Gaussian noise (AWGN) was
generated in MATLAB and was combined with noise-free
signals for all inputs. Fig. 11 shows the BER results of a
traditional non-MRF MUX, a conventional MRF [24] MUX,
Fig. 11. BER results for a MUX. an MS [28] MUX, an MRF-Schmitt [34] MUX, and a
proposed MUX. Compared with an MS MUX, the proposed
MUX has at least 14% lower BER. The improvement can be
structure shown in Fig. 9(b). g4 shown in Fig. 9(a) is utilized explained by the general mapping process from a circuit to the
for the MUX function by x a · x s + x b + x s . We group g3 corresponding CPMRF network. Generally, mapping a circuit
and g4 together to form a four-input AND–OR module shown onto the CPMRF network involves two major steps.
in Fig. 9(b). The logic operations, AND and OR, share a 1) Designing a shared PMRF network for a pair of two
common MRF network to achieve area efficiency. logic gates based on the partial clique energy functions.
We further extend complementary pairs to non- 2) Designing a coding structure to complement the rest
complementary pairs for more general designs. A non- clique energy and transform weak bits to strong bits
complementary NOR – NOR pair is shown in Fig. 10. The avoiding weak bit cascade.
intermediate signals t1 and t2 are the outputs of gates These two steps guarantee that the implementation of the
g5 and g6 , which have the high correct probability of clique energy for the internal valid states is the same as
bit “0” referred to strong bit “0” for the first level (S1 ) that in the MS design. In addition, the coding structure
and the low correct probability of bit ‘1’ represented in the proposed method utilizes the combination of the inner
by symbol W1 . We use gate g4 for coding and then for noise tolerance of asymmetric logic gates such as the robust
the second level feedback OR–OR structure: g1 and g2 , output “1” in a NAND gate and the robust output “0” in a
outputting strong bit “1,” can compensate the loss of the NOR gate in order to transform weak bits into strong bits.
first level, achieving two complementary cascades instead of In this way, the noise-tolerance capability is ensured through
overlapping weaknesses. redundancy in the CPMRF method by the MRF theory and
The effectiveness of the proposed area-efficient method is the inner noise tolerance of logic gates. This explains why
illustrated by the transistor counts for the above structures the proposed CPMRF method has better BER results than the
in Figs. 6, 8–10, and 12. In Table III, the conventional MRF MS method. Since a logic gate pair shares a common MRF
design [24] for each structure requires the largest number network in the CPMRF method, it can save more area than
of transistors. The proposed method saves at least 61.7% the MS method. In Fig. 11, it is shown that the conventional
transistors compared with the conventional MRF [24], while MRF [24] design has the best noise tolerance under various
it saves at least 17.9% transistors compared with MS [28]. SNRs, while the MRF-Schmitt [34] design has the second-best

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LI et al.: LOW-POWER NOISE-IMMUNE NANOSCALE CIRCUIT DESIGN USING CPMRF METHOD 2395

Fig. 14. Testing platform.

TABLE IV
P ERFORMANCE OF THE P ROPOSED CLA

Fig. 12. Proposed CPMRF carry-lookahead adder.

Fig. 13. Die photograph of the proposed CLA.

noise tolerance. This is because the conventional MRF method

maps completely all possible valid sates without any loss
of the clique energy, while the MRF-Schmitt [34] method
combines the high noise tolerance of the MRF and Schmitt
trigger circuits. However, the conventional MRF design is Fig. 15. Measured waveforms of input (upper) and output (lower) of the
proposed chip under 6.02-dB SNR.
very complex to implement and consumes large area over-
head. The MRF-Schmitt design consumes more hardware
than the proposed design as well. Considering hardware cost,
the proposed method achieves a better tradeoff between area shown in Fig. 14. We used an Agilent 33120A 15-MHz
cost and noise tolerance. Function/Arbitrary Waveform Generator to generate random
noise and an Agilent 81110A Pattern Generator to provide
the input noise-free signal and combine them together by a
IV. C HIP I MPLEMENTATION combiner to mimic the noisy environment as the input injected
We designed an 8-bit carry-lookahead adder chip to inte- to the proposed CLA circuit.
grate the proposed CPMRF pairs. Each CPMRF pair is marked As shown in Fig.15, the input and output waveforms were
in a gray rectangle, as shown in Fig. 12. The proposed CLA measured under the interference of noise with 6.02-dB SNR
chip employs the IBM 130-nm CMRF8SF process. The die at a core voltage of 0.25 V. The largest peak variance of both
photograph is shown in Fig. 13. In Table IV, we summarize the high levels and low levels of input and output signals is
the performance of the proposed chip in terms of its area, marked in Fig. 15. It is found that the quality of the output
power consumption, and BER. To assess the noise-tolerance signal is much better than the noisy input signal, especially for
capability of the proposed chip, we built a testing platform the low logic levels. The above conclusion is also supported

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2396 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 53, NO. 8, AUGUST 2018

measured in [28], [29], and [34], all comparisons are based on

the previous results, including the analysis, the measurement,
and the performance of the chips qualitatively. Results are
consistent with the theoretical analysis in [28], [29], and [34].
The results in Fig. 18 indicate good noise resilience of the
proposed CLA chip under the interference of high noise
power. Compared with an MS CLA [28], the proposed CLA
is characterized by a 20% reduction in BER with 37.7% area
saving. Although a full MRF CLA [29] has the lowest BER
(28% lower than the proposed CLA), it consumes 64.4% more
transistor area. The MRF-Schmitt CLA [34] has 29% lower
BER than the proposed CLA, but it cost 35.1% more transistor
area. The observation that the BER of the MRF-Schmitt
Fig. 16. Eye pattern of the input signal of the proposed CLA chip CLA is close to that of the conventional MRF is consis-
under 6.02-dB SNR. tent with what is presented in [34]. Although the proposed
adder requires about three times the transistor number used
in a non-MRF traditional design, it achieves about 51% the
reduction of BER. For power savings, the proposed CLA
only consumes 125 nW/MHz, which saves 93% of the power
consumption of an MS CLA [28] at a supply voltage of
0.25 V. As indicated in [34], the MRF-Schmitt CLA consumes
more power than the MS CLA. Although it has a better
BER than the proposed method, it uses much more power
and requires more transistors. Therefore, the proposed MRF
circuit is a promising design, which can satisfy a great balance
between the demanding requirements of noise immunity,
power consumption, and hardware cost.

Fig. 17. Eye pattern of the output signal of the proposed CLA chip
V. C ONCLUSION
under 6.02 dB.
In this paper, we propose a low-power CPMRF method for
multi-logic operations in order to achieve a better tradeoff
between chip area and noise immunity at low power supply
voltage. First, we put forward an idea of partial clique energy
corresponding to the full clique energy used in the conven-
tional MRF design [24]. The partial clique energy is intended
to combine multiple logic operations within a shared MRF
network. Second, a coding unit is built based on the benefit
of asymmetric gates. We also propose general coding units
for complementary pairs and non-complementary pairs. Using
this CPMRF method, we fabricated an 8-bit CLA chip using
IBM 130-nm technology. In the chip validation, the proposed
CPMRF CLA achieves significant area saving and power
saving compared with the traditional MRF design [29] and
exhibits relatively high noise immunity. In comparison with
the MS design [28], the proposed CLA outperforms MS CLA
with 20% BER improvement, 37.7% area saving, and 93%
power saving at a supply voltage of 0.25 V. Considering the
Fig. 18. BER comparison under different SNRs. automation of the whole process, the CPMRF pairs proposed
in this paper can be generalized into corresponding standard
by the observed waveforms of the input and output signals, cells in cell-based designs by hardware description languages
which is shown in Figs. 16 and 17. Furthermore, we measured in the existing EDA flows. Macro blocks formed by a large
the BER of the proposed CLA under different levels of set of logic operations (standard cells) can also be trans-
noise power evaluated by SNR. Fig. 18 is the comparison of formed into the corresponding CPMRF designs by the same
BER measurements for a conventional CLA (constructed by approaches listed in this paper. Additionally, by following
normal logic gates), a full MRF CLA [29], an MS CLA [28], the mapping rules, designers can easily construct their own
an MRF-Schmitt CLA [34], and the proposed CPMRF CLA. CPMRF mapping cells to replace the old versions. The infor-
Since other designs have been implemented in silicon and mation can be included along with other parameters, such

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LI et al.: LOW-POWER NOISE-IMMUNE NANOSCALE CIRCUIT DESIGN USING CPMRF METHOD 2397

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vol. 16, no. 3, pp. 389–391, Mar. 2011. in communication engineering from the University
[15] A. Naderi, S. Mannor, M. Sawan, and W. J. Gross, “Delayed stochastic of Electronic Science and Technology of China,
decoding of LDPC codes,” IEEE Trans. Signal Process., vol. 59, no. 11, Chengdu, China, where she is currently pursuing the
pp. 5617–5626, Nov. 2011. Ph.D. degree in electrical engineering.
[16] Q. T. Dong, M. Arzel, C. Jego, and W. J. Gross, “Stochastic decoding She is currently a joint Ph.D. Student with
of turbo codes,” IEEE Trans. Signal Process., vol. 58, no. 12, the Department of Electrical and Computer Engi-
pp. 6421–6425, Dec. 2010. neering, University of Alberta, Edmonton, AB,
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2398 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 53, NO. 8, AUGUST 2018

Yufeng Li (S’18) received the B.Eng. and M.Sc. Xuan Zeng (M’97) received the B.S. and Ph.D.
degrees in measuring and testing technologies and degrees in electrical engineering from Fudan Univer-
instruments inform the Wuhan University of Tech- sity, Shanghai, China, in 1991 and 1997, respec-
nology, Wuhan, China. She is currently pursuing tively.
the Ph.D. degree with the Department of Electrical She was a Visiting Professor with the Department
and Computer Engineering, University of Alberta, of Electrical Engineering, Texas A&M University,
Edmonton, AB, Canada. College Station, TX, USA, and with the Department
Her research interests include low-power error- of Microelectronics, Technische Universiteit Delft,
tolerant digital-integrated circuits and systems. Delft, The Netherlands, in 2002 and 2003, respec-
tively. She is currently a Full Professor with the
Department of Microelectronics, Fudan University,
where she was the Director of the State Key Laboratory of ASIC and
System from 2008 to 2012. Her current research interests include design for
I-Chyn Wey received the Ph.D. degree in elec- manufacturability, high-speed interconnect analysis and optimization, analog
tronics engineering from National Taiwan Univer- behavioral modeling, circuit simulation, and ASIC design.
sity, Taipei, Taiwan, in 2008. Dr. Zeng was a recipient of the Chinese National Science Funds for
He is currently an Associate Professor with the Distinguished Young Scientists in 2011 and the First-Class of Natural Science
Green Technology Research Center, Center for Prize of Shanghai in 2012. She is the Changjiang Distinguished Professor with
Reliability Sciences and Technologies, Electrical the Ministry of Education Department of China in 2014.
Engineering Department, School of Electrical and
Computer Engineering, College of Engineering,
Graduate Institute of Electrical Engineering, Chang
Gung University, Taoyuan, Taiwan, and with the
Department of Neurology, Chang Gung Memorial Xiaoxue Jiang (S’16) received the B.Sc. and M.Sc.
Hospital, Taoyuan. His current research interests include VLSI CMOS circuit degrees in electrical engineering from Jilin Univer-
design, noise-tolerant CMOS circuits, near-threshold-voltage CMOS circuits, sity, Changchun, China, in 2012 and 2015, respec-
ultralow-power CMOS circuits design, and circuits and system designs for tively. She is currently pursuing the Ph.D. degree
biomedical and wearable health applications. in electrical engineering with the University of
Alberta, Edmonton, AB, Canada.
Her current research interests include low-power
analog/mixed-signal integrated circuits and systems
Jianhao Hu (M’10) received the B.E. and Ph.D.
for biomedical applications, including wearable low-
degrees in communication systems from the Univer-
intensity pulsed-ultrasound system and impedance-
sity of Electronic Science and Technology of
based point-of-care biosensors.
China (UESTC), Chengdu, China, in 1993 and 1999,
respectively.
He is currently a Professor and Vice-Dean with
the National Key Laboratory of Communication,
UESTC. From 1999 to 2000, he was a Post-Doctoral
Jie Chen (F’16) received the Ph.D. degree in elec-
Researcher with the City University of Hong Kong,
trical and computer engineering from the University
Hong Kong. He served as a Senior System Engineer
of Maryland at College Park, College Park, MA,
with the 3G Research Center, The University of
USA.
Hong Kong, Hong Kong, from 2000 to 2004. His current research interests
He is currently a Professor with the Electrical and
include high-speed and low-power digital signal processing technology, very
Computer Engineering Department and an Adjunct
large-scale integration, NoC, wireless communications, and software radio.
Professor with the Biomedical Engineering Depart-
ment, University of Alberta, Edmonton, AB, Canada.
He is also a Research Officer at the National
Fan Yang (M’08) received the B.S. degree from Research Council/National Institute for Nanotech-
Xi’an Jiaotong University, Xi’an, China, in 2003 and nology, Edmonton. He has co-authored two books,
the Ph.D. degree from Fudan University, Shanghai, 93 journals, and 88 conference proceeding papers. He holds seven patents
China, in 2008. awarded, several of which have been either used in production or licensed by
From 2008 to 2011, he was an Assistant Professor various companies. He has i10-index of 64 according to the Google search.
with Fudan University, where he is currently His current research interests include low-power fault-tolerant nanoscale
an Associate Professor with the Microelectronics circuit and device design, impedance-based microfluidic biosensors for
Department. His current research interests include disease diagnosis and environmental monitoring, and pulsed-wave device for
model order reduction, circuit simulation, high-level increasing renewable biofuel production and cell therapy.
synthesis, yield analysis, and design for manufac- Dr. Chen is a fellow of the Canadian Academy of Engineering and the
turability. Engineering Institute of Canada.

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