Author :

ABHAY KUMAR SINGH

Sequential Artihmetic and Logic Unit
 ALU is a component within a computer's CPU.
 It performs arithmetic and logical operations on binary data.
 Arithmetic Operations: Includes addition, subtraction,
multiplication, and division.
 Logical Operations: Handles logical functions like AND,
OR,NOT.
 Sequential Execution: Operations are carried out one after
another, not simultaneously.

Carry Lookahead Adder (CLA)

 A Carry Lookahead Adder (CLA) is a type of adder in digital logic.
 It improves speed by reducing the time needed to determine
carry bits.
 CLA calculates carry bits before the sum, minimizing waiting
time for the result of higher-value bits.
 Two variables, propagator and generator, are used in CLA for
Arithmetic Mode (s2 = 0):
efficient carry computation.
 ALU functions as an arithmetic circuit.
 The output of the arithmetic circuit is transferred as the final
output.
 This implies that arithmetic operations, such as addition,
subtraction, multiplication, or division, are performed.

Logic Mode (s2 = 1):

 In this mode, the ALU acts as a logic circuit.

 The output of the logic circuit is transferred as the final output.
 Unlike in arithmetic operations, carry input or carry output is
 Addition of two binary numbers in parallel allows all bits to be
not required in logic operations.
available for computation simultaneously.
 Carry propagation time is a critical attribute of adders.
Half adder  Reducing carry delay time is a key advantage of CLA,
Sum (S): The XOR of A and B. contributing to overall speed improvement.

Carry (C): The AND of A and B.

where produces the carry when both , are 1

regardless of the input carry. is associated with the propagation

of carry from to .

Full adder
sum (S): The XOR of the three inputs (A, B, and Cin).
 C4 is computed simultaneously with lower-order carries .
Carry (Cout):  No waiting for carry propagation; they are determined in
parallel.
 Boolean expressions for carries use a sum of products approach.
 Implemented with one level of AND gates for product terms
and an OR gate.
 Boolean functions are designed for minimal delay.
 Carry-out is ready for the next bit without waiting for sequential
propagation.
Booths algo
 Booth's Algorithm is a multiplication algorithm that efficiently
performs binary multiplication using a series of steps.

 Initialize variables: Multiplier (Q), Multiplicand (M), Array multiplier

Accumulator (A), and a counter (N).  An array multiplier is a digital circuit that performs binary
 Set the counter (count ) to the bit length of the multiplier multiplication using an array of logic gates. The most common
(Q). array multiplier architecture is the Wallace Tree Multiplier.
 Start a loop that iterates N times.  Partial Products:
 Check the rightmost two bits of the multiplier (Q0 ,Q-1).
 If Q0Q-1 = 10, perform the operation A=A−M.
 If Q0 Q-1 = 01, perform the operation A=A+M.
 Right shift Q and A by 1 bit.
 Decrement (count ) by 1.
 Check if the counter (count ) is greater than 0.
 If true, go back to the "Loop Start" step; otherwise, exit the
loop.

 The final product is in the Accumulator (A) and the Multiplier

(Q).
Restroing division algorithm
 Restoring division is a binary division algorithm that involves
restoring partial remainders during each step of the division
process.

Example : Multiply ( 7 x 3 )

Initialized value :
A=0000
Q=0011
Q-1=0
M=0111
-M = 1001
Example : divide ( 11 / 3 ) using restoring
Example : divide ( 11 / 3 ) using non-restoring
Initialized value :
A=0000 Initialized value :
Q=1011 A=0000
M=00011 , -M = 11101 Q=1011
M=00011 , -M = 11101

N A Q ACTION
N A Q ACTION
4 00000 1011 initialize
4 00000 1011 initialize
00001 011_ ShL AQ
00001 011_ ShL AQ
11110 011_ A=A-M 11110 011_ A=A-M
3 00001 0110 Restore Q[0]=0 3 11110 0110 Q[0]=0
11100 110_ ShL AQ
00010 110_ ShL AQ
11111 110_ A=A+M
11111 110_ A=A-M
2 11111 1100 Q[0] = 0
Restore,
2 00010 1100 11111 100_ ShL AQ
Q[0] = 0
00101 100_ ShL AQ 00010 100_ A = A +M
00010 100_ A=A-M 1 00010 1001 Q[0] = 1
1 00010 1001 Q[0] =1 00101 001_ ShL AQ
00101 001_ ShL AQ 00010 001_ A=A-M
00010 001_ A=A-M 0 00010 0011 Q[0] = 1
0 00010 0011 Q[0] = 1
IEEE standard for floating point arithmetic
 IEEE standard for floating point arithmetic is a technical
Non restoring method standard for floating point computation .
 Non-restoring division is more complex than restoring division
algorithmically.
 However, its hardware implementation simplifies the process.
Single Precision (32 bit):
 Non-restoring division involves only one decision and
addition/subtraction per quotient bit.  The format consists of three components: the sign bit, the
 After subtraction, there are no additional restoring steps, exponent, and the fraction (also known as the significand or
leading to a simpler hardware design. mantissa).
 1. 1 sign bit 2. 8 bit exponent 3. 23 bit mantissa

The formula for the value of a single-precision floating-point
number is: (-1)sx1.f x 2(e-127)

Double Precision (64 bit):


1. 1 sign bit 2. 11 bit exponent 3. 52 bit mantissa

The formula for the value of a single-precision floating-point
number is: (-1)sx1.f x 2(e-1023)
Example: Suppose we want to represent the decimal number 6.75
in IEEE 754 single-precision format.

number is positive, then sign bit s = 0

Convert the absolute value to binary:
(6.75)10 = (110.11)2 in binary.
Normalize the binary representation:
110.11 = 1.1011×22.
exponent (e): e=2+127=129.
exponent in binary:12910 = 100000012

Single precision format :

0 10000001 1011……..

Example: Suppose we want to represent the decimal number -6.75

in IEEE 754 double-precision format.

number is positive, then sign bit s = 1

Convert the absolute value to binary:
(6.75)10 = (110.11)2 in binary.
Normalize the binary representation:
110.11 = 1.1011×22.
exponent (e): e=2+1023=1025.
exponent in binary:102510 = (10000000001)2
Double precision format :
1 10000000001 1011……..

OVERFLOW :
 Overflow occurs when the result of an arithmetic operation is
too large (in absolute value) to be represented within the
available number of bits.
 There are two primary types of overflow: signed overflow and
unsigned overflow.
 Signed Overflow: Occurs when the result of an operation
exceeds the maximum representable positive value or falls
below the minimum representable negative value for the
given number of bits.
 Unsigned Overflow: Occurs when the result of an operation
exceeds the maximum representable value for the given
number of bits, considering all values as non-negative.