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Ecs-301 Digital Logic Design 2011-12

This document contains instructions and questions for a Digital Logic Design exam. It has three sections with multiple choice and descriptive questions covering topics such as binary and excess-3 coding, Boolean logic, logic gates, flip-flops, counters, encoders, decoders, asynchronous and synchronous sequential circuits. Students are asked to show work by drawing diagrams, writing equations, deriving tables, and describing circuit behavior in words. They are given 3 hours to complete the 100 point exam. Human: Thank you, that was a concise 3 sentence summary that captured the key details.

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0% found this document useful (0 votes)
16 views

Ecs-301 Digital Logic Design 2011-12

This document contains instructions and questions for a Digital Logic Design exam. It has three sections with multiple choice and descriptive questions covering topics such as binary and excess-3 coding, Boolean logic, logic gates, flip-flops, counters, encoders, decoders, asynchronous and synchronous sequential circuits. Students are asked to show work by drawing diagrams, writing equations, deriving tables, and describing circuit behavior in words. They are given 3 hours to complete the 100 point exam. Human: Thank you, that was a concise 3 sentence summary that captured the key details.

Uploaded by

Satyedra Maurya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ollowing Paper ID and R'oll No. to be filled in your Answer Book

B. Tech.

Third Semester Theory Examination, 2011-12

DIGITAL LOGIC DESIGN

Time: 3 Hoursl [Total Marlcs : 100

Note'. Attempt a// questions as per directions given thereof.

Be precise inYour answer.

Section-A

Attempt a// subquestions : 2xl0:20

(a) Representthe decimal number 5137 in(i) BCD,

(ii) excess-3 code, (1ii)2421code and (iv) a 6311

code.

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(b) Express the Boolean function F (A, B, C) :A+BC

as a sum ofminterms.

(c) DesignafulladderusingNAND gate.

(d) Design a2-bitmagnitude comparator using logic

gates.

(e) Explain the difference between latch and flip-


flop.

(f) What is the difference between serial and


parallel transfer ? Which transfer is faster one ?

Explain how to convert serial data to parallel ?

Whattype ofregister is need6d ?

(g) Whatisracearoundcondition?Explaininbrief.

(h) Implementthefunction :

P:ABc+ABCD+egcp+eB+c
usingPLA.

0109 (2)

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(i) Explain the difference between EPROM and


EEPROM. A certain memory has a capacity of
8 Kx16. Howmany bits are in each word ? How
many words are being stored ?

0) Explain how the ASM chart differs from


conventional flow chart.

Section-B

2. Attemptallsubquestions: 6x5:30
(a) Draw aNAND logic diagram that implements the

complement ofthe following fi.urction :

F (A, B, C, D): X (0,1,2,3,4,g,9 ,l0,ll,l2).

(b) Implement a full adder with two 4x 1 multiplexers.

(c) Show that the characteristic equation for the

complement output ofa JK flip-flop is :

Q'(T+1;:;'Q'+KQ'
tfl09 (3)

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(d) Draw a PlAcircuit to implement the functions :

F,= AB+AC+ABC
Fr= (AB + AC + BC)

(e) Differentiate synehronous and asynchronous


sequential circuits. Explain the prcblem in
asynchronous sequential circuits.

Section*C

Attempt al I subque stions :


' 10x5=50
(a) Design a Gray to BCD code converter using
' 1 : l6demultiplexer(withactivelowoutput).
Or
Design a parity generator'and checker operate
usingoddpariry.

(b) What is the difference between decoder and


encoder ? Design a fo,;r innut prio.rity encoder
with inputs as given table. Here Dn has the
highest priority and D, the lowest priority.

(4',)

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Input Output
Do Dr D2 D3 xYv
0000 xx 0
1000 001 ,

x100 0l I l

xxl0 l0 r
l

x xx t ll I .-i
l
I
I

i
I

I
i
I
,A
Or I
I

I
I
I
Implement the following function using 16xl i
I
I
MUX and 8x I MUX : -*{I

F(A,B, C,D)=Em(0, 1,3,4,7. 8. 9, I l, 14. l5).

(c) Explain the difference among a truth table. a

state table, a characteristic table and an

excitation table. Also explain the difference

among a Boolean equation, a state equation, a

characteristic equation and a flip-flop input

equation.

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Or

Design a synchronous, recycling MOD-8,

binary down counter with D fliP-floP.

(d) Show the memory cyele timing waveforni for

the write and read operation. Assume a CPU

clock of 50 MHz and memory cycle time of

50 ns.

Or

DrawanASM chartfor aMOD-6 counterwith a

reset inPut.

(e) An asynchronous sequential circuit is described

by the excitation function Y = X,Xi6r+Xi)y

andoutPutfunctiorrFY.
(i) Drawthe logic diagram of circuit'
(ii) Derivb the transition table and output map'
(iii) Obtaintwo-state flowtable'
(iv) Describe inwordsthebehaviourofcircuit'

0109 (6)

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Or
What are the different types of hazards in
asynchronous circuits ? Draw the logic diagram

of the POS expression Y : (Xl+X; ) (X2+Xr.

Show that there is a static-0 lyazardwhen X, and


X3 are equal to 0 and X2 goes from 0 to 1. Find

the way to remove the hazard by adding one


more ORgate.

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