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Ect342 Scheme

This document is a scheme for valuation and answer key for an examination on embedded systems. It contains 20 questions across 5 modules: 1. The first module covers embedded system design processes. 2. The second module covers embedded operating systems and interrupt handling. 3. The third module covers embedded processor architecture and instruction sets. 4. The fourth module covers embedded communication interfaces. 5. The fifth and final module covers embedded system resource management including memory management, deadlocks, and real-time scheduling.

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MAHESWARY SREENATH EC
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79 views

Ect342 Scheme

This document is a scheme for valuation and answer key for an examination on embedded systems. It contains 20 questions across 5 modules: 1. The first module covers embedded system design processes. 2. The second module covers embedded operating systems and interrupt handling. 3. The third module covers embedded processor architecture and instruction sets. 4. The fourth module covers embedded communication interfaces. 5. The fifth and final module covers embedded system resource management including memory management, deadlocks, and real-time scheduling.

Uploaded by

MAHESWARY SREENATH EC
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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0300ECT342052201

Pages 3

APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY


Scheme for Valuation/Answer Key
Scheme of evaluation (marks in brackets) and answers of problems/key
Sixth Semester B.Tech Degree Examination June 2022 (2019 scheme)

Course Code: ECT342


Course Name: EMBEDDED SYSTEMS
Max. Marks: 100 Duration: 3 Hours

PART A
Answer all questions, each carries 3 marks. Marks

1 Definition (1mark) (3)


2 Applications(1mark each)
2 Any 3 challenges (1 mark each) (3)
3 each bus has 3 points (each point 0.5 mark) (3)
4 Figure(2mark) (3)
Explanation (1mark)
5 Explanation (3 marks) (3)
6 Architecture (3 marks) (3)
7 Figure-(1 mark) (3)
Explanation-(2marks)
8 Binary representation (1mark) (3)
Normalize the number and add bias to the exponent (1mark)
Give 32 bit representation with sign bit(1 mark)
9 Thread(1.5marks) (3)
Process(1.5marks)
10 Operating system(1mark) (3)
Explanation(1mark)
Figure(1mark)
PART B
Answer one full question from each module, each carries 14 marks.
Module I
11 a) Design process steps figure(2 marks) (7)
Explanation(5 marks)

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0300ECT342052201
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b) Explanation (7marks) (7)


OR
12 a) Figures(4marks) (7)
Explanation(3marks)
b) EDLC (1mark) (7)
figure(1mark)
Phase explanation (5mark each)
Module II
13 a) Figure and explanation of DMA (4 marks) (7)
Brief description of 3 types of DMA (3marks)
b) Sources(5marks) (7)
Interrupts(2marks)
OR
14 a) Figure(2marks) (7)
Explanation(5marks)
b) ROM(1mark) (7)
Cache(1mark)
5 Types(each carries 1mark)
Module III
15 a) Figure (3marks) (7)
Explanation(4marks)
b) Data processing instructions 4 types(each carries 1mark) (7)
Data transfer instructions 3 basic forms(each carries 1mark)
OR
16 a) Arm programmers model figure (2 marks) (7)
CPSR register figure(2 marks)
Explanation(3 marks)
b) Logic/step (3marks) (7)
Program(4marks)
Module IV
17 a) Figures(3marks) (7)

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Explanation(4marks)
b) Figures(3marks) (7)
Explanation (4marks)
OR
18 a) Explanation(7marks) (7)
b) Figure(2marks) (7)
Buses(3marks)
Explanation(2marks)
Module V
19 a) Deadlock(1mark) (7)
Conditions(each carries 0.5 mark)(2marks)
Techniques to detect and prevent (4marks)
b) 2 types(each carries1marks) (7)
Services(5marks)
OR
20 a) Figure (2marks) (7)
States explanation(2marks)
3types(each carries 1mark)
b) Functional requirements(4 marks) (7)
Non Functional requirements(3 marks)
****

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