Introduction to

Chip-Package Co-design

Lei He, UCLA, [email protected]

Shauki Elassaad, Rio Design Automation

ISQED05 1
Outline
• Background and motivation

• Chip Package Co-design Flow

• Signal Integrity
– Simultaneous Switching Noise

• Power Integrity
– Plane impedance and resonance

• Conclusion
ISQED’
05 2
Heterogeneous Systems Integration
CMOS VLSI MEMS
•Full Custom •Bulk
•RF Telemetry •Surface
•ASIC •Emboss
•Embedded Core Novel System Integration •Other
•Human-computer interfaces
•Enhanced capabilities
(eg. smart sensors and actuators)
•High complexity
(eg. bio-complexity)

Advanced Packaging
•Seamless integration
•Embedded Passives

ISQED’
05 (From P. Franzon) 3
Connection from die to board

• Die (IO cells -> RTL routing)

• -> package (bumps -> escape routing ->
balls)
•ISQED’
->
05 board 4
 Top View of Layout
Two
P/G
bumps
sharing
a via

Escape Bump
routes
Via

Ball/Via
in one
view

ISQED’
05 5
VLSI-Centric Design (Problematic)
• IC and package tools very separated:
IC Physical Design Package Physical Design
I/O Locations
IBIS Models

Package Modeling/Simulation
IC Modeling/Simulation

ISQED’
05 (From P. Franzon) 6
On-Chip Design Concerns
nPhysical Concerns
Ø Die Netlist Connectivity (logic cells to IO cells)
Ø System Connectivity (IO cells to package)
Ø Power Network Design
nElectrical Concerns
Ø Core Timing Constraints
Ø System Timing Constraints
Ø Power Budget
Ø Signal Integrity and Reliability Constraints
ØSupply voltage scaling imposes very tight noise margins on
chip and package designs
ØSignificant noise contribution from core switching
ØBut greater on-chip exposure to package-side SSN

ISQED’
05 7
Package Design Concerns
• Physical Concerns
ØReduce Package Cost
ØReduce Stack-up Layers
ØOptimize Decoupling Capacitance
• Electrical Concerns
ØReduce AC Noise Effects
ØLow Impedance Power Distribution System
ØMeeting Timing Constraints

ISQED’
05 8
Typical Package Design Cycle
Pad/package
Pad/package Iteration:
Iteration: P&R
P&R ofof IO/Pad
IO/Pad cells,
cells,
Pins; Pwr/gnd and inter-cell connections;
Pins; Pwr/gnd and inter-cell connections;
PCB
PCB pin
pin locations
locations (x,y);
(x,y);

Package/Pad/IO
Package/Pad/IO RuleRule checking
checking (PRC):
(PRC):
Floorplanning
Floorplanning ofof IO/Pad/Pins;
IO/Pad/Pins; SI, timing, clocks, IO voltages,
SI, timing, clocks, IO voltages,
Define
Define Netlist
Netlist hierarchy/manipulations
hierarchy/manipulations assembly
assembly rules,
rules, special
special regions
regions

Manufacturing
Manufacturing andand NRE
NRE Costs;
Costs; Verify
Verify user
user specified
specified requirements
requirements and
and rules;
rules;
Die,
Die, Substrate,
Substrate, Package
Package PCB pins, Power grid, # VSS/VDD,
PCB pins, Power grid, # VSS/VDD,
decoupling
decoupling caps,
caps, EMI,
EMI, ESD,
ESD, Vias
Vias

Defining
Defining Interfaces,
Interfaces, Signals,
Signals,
PLL,
PLL, Power,
Power, Clock,
Clock, ## pins,
pins, ## IOs
IOs

Package/Substrate
Package/Substrate Architecture
Architecture Exploration
Exploration
(start
(start ~4/5 months before Tapeout)
~4/5 months before Tapeout) Finalize
Finalize IOs/Pads/Pins;
IOs/Pads/Pins;
Package
Package Tapeout
Tapeout

ISQED’
05 9
Needs for Co-Design
• High-frequency Designs
Ø 400 MHz buses becoming common
Ø On-chip exposure to package noise
ØSimultaneous switching noise
ØPackage resonance
• Tighter Turnaround Time
Ø Package design convergence
Ø System design convergence
• High Density Packaging
ISQED’
05 10
High Density Packaging Trends
• Short Term
– Increased penetration of Direct Chip Attach (DCA)
(solder balls) and Chip-On-Board (COB)
• On-chip design and functionality suffer due to
the increased scope of package -induced SSN
• Layout difficulties due to high pin count systems
• Routing resources becoming very tight, flip-chip
escape routing is difficult
• Long Term
– Package technology adding value to the system
• High density, low-cost packaging
• Meet design constraints for both SI and PI
ISQED’
05 (From P. Franzon) 11
Eye Diagram for LVDS with Frequency
Dependent Coupled Transmission Lines

100Mbit/sec

1Gbit/sec

10Gbit/sec

ISQED’
05 12
 A Co-Design Flow with RioMagic
CHIP Design PCB/Package Design
Architecture Specs Design Planning
RioMagic
RTL, Logical FP, Synthesis Package/Substrate selection;
Power/Thermal
Exploration,
Physical Floorplanning Methodological, PCB Pin order, signal
Insync Optimizationassignment, XY coords
Adhoc, in critical
P&R, Timing, SI pathRioMagic
of tapeout, Package & PCB routing
segregated
Final Routing/Timing/Buffer Substrate Extraction &
& Extraction Simulation

IO/Pad/Bump: (Order, Finalize Package Pin

P&R, SI) order, Signal Assignment
RioMagic
Full chip LVS/DRC/ERC Final Package & PCB
Verification route, extraction and ERC

ISQED’
05 13
Outline
• Background and motivation

• Chip Package Co-design Flow

• Signal Integrity
– Simultaneous Switching Noise

• Power Integrity
– Plane impedance and resonance

• Conclusion
ISQED’
05 14
Chip-Package-PCB Co-optimization
Chip Package PCB PCB Package

ml

ml

Optimize by iterating on
Pkg Pwr
1. Signal pin/pad/bump location
Plane 2. # de-
de-caps & its value & its
position
Pkg Gnd 3. # ground/pwr
ground/pwr pins
plane 4. Series resistance and its
value
5. Different packages during
architectural phase
6. …
ISQED’
05 15
Package Escape Routing
• Escape routing of IO pads imposes chip
and package design constraints

ISQED’
05 16
IO Ring Planning
• Flip-chip Design: Area IO vs Peripheral IO
Ø Area IO breaks-up most current CAD tools
Ø Peripheral IO: cost -effective to transform from wire-
bonding to FC
Ø Peripheral IO forms a ring
• IO Ring Planning
Ø IO locations (placement)
Ø Escape routing (escapability analysis)
Ø Signal IO vs PG cells/bumps (core power supply)
Ø Satisfy SI constraints (SSN)
• Needed early in the design to enable the chip-
package co-design
Ø System Level Timing Constraints
Ø Chip Level Timing Constraints
ISQED’
05 17
IO placement

• Placement of bump arrays

• Placement of I/O sites
• Placement of I/O cells
ISQED’
05 18
Example of IO placement
• Regular Bump
pattern is preferred
• IO sites are decided
by proximity
• IO sites are more
than IO cells
• Power domains are
defined

ISQED’
05 19
Core Power Supply Distribution
Voltage drop is given by
the equation: 2
p2 Wp p
VDD IR = J z ρ m , sh (1 − 2 ) ln( )
8 p Wp
GND Given the maximum
VDD allowed IR drop, it is
GND possible to solve for ρ m , sh ,
the required metal
coverage, iteratively.
p Wp
Adapted from:
However, IR drop
Power Supply Distribution and Other constraint should not be a
Wiring Issues for Deep-
Deep-Submicron ICs
by W.T. Lynch of Semiconductor Research
major issue for FC design!
Corporation

ISQED’
05 20
 IO Power Routing
VDD VDD
GND GND

GND
VDD GND VDD

Wire-bounding IO Power Route Flip-chip IO Power Routes

•IO P/G Cells embedded in IO Ring to feed •No P/G Cells in IO Ring
signal IOs
•Still Need ESD Cells
•IO P/G Cells contain ESD cells
•P/G bumps cells feed IO Ring
•Consumes a lot of space in Ring
(constrains pad-limited designs) •More Saving on Die Size (especially for pad-
limited designs)

ISQED’
05 21
Outline
• Background and motivation

• Chip Package Co-design Flow

• Signal Integrity
– Simultaneous Switching Noise

• Power Integrity
– Plane impedance and resonance

• Conclusion
ISQED’
05 22
Simultaneous Switching Noise
RP
1 Cbp Cpp
∆
∆It = ?
2 rP
RL,bp LL,bp RL,pp LL,pp

Lg CL
16 rG CL,bp CL,pp

Rpp Lpp Rbp Lbp

RG
Compact RLC
Model

• Package pins, signal traces, and stack-vias exhibit inductive effects

• Power/ground bounce effects limit the performance of design
• Noise effects become more prominent: Ldi/dt
– Higher clock speed
– More number of I/O drivers switches simultaneously

ISQED’
05 23
Simultaneous Switching Noise
• SSN Issue Addressed by Signal to PG ratios (SPG) in the
IO Ring
Ø Accounts for package trace, termination, power and ground
Ø Domain by domain: multiple-domain design is not un-usual
• SPG Estimation
Ø Accurate and efficient driver model
Ø Macro models: (IBIS)
Ø Effective inductance modeling for signal traces and package
(which yet to be designed)
Ø Pre-characterized package templates

16

ISQED’
05 24
Simultaneous Switching Noise
IO Ring IBIS Models Trace Pattern Package
Power Domains Inductance Table Tech File

dI/dt
Estimation Effective L
Estimation

Domain
SPG

• dI/dt = f(IV, R_term, VT)

• Effective L assumed Common Excitation for All Ports
• SPG value assumes all drivers switch simultaneously

ISQED’
05 25
 SSN: Detailed PEEC Modelling

Design: PEEC-based characterized models are

employed for SSN estimation

Verification: Detailed PEEC extracted models are

employed for SSN analysis
ISQED’
05 26
 Return Path Modelling
•Needed to model Ldi/dt Noise
•L is defined for a current loop
•Current distribution depends on routing path and
switching pattern
•In early stages, no package routes or power planes exist,
and estimated models are developed
•Rather pessimistic than optimistic
•Efficient, with reasonable accuracy

ISQED05 27
 Return Path Modelling
•Loop Model: a conservative (pessimistic) model
•To build a seed IO plan Ls Lsg Lsp
Lsg Lg Lgp
Lloop = Ls + Lg − 2Lsg
Lsp Lsg Lp
•Effective Inductance Modeling: based on early
PEEC models (accurate with computation cost)
Two Point Inductance
•Based on Impedance/Admittance
1
Leff = Yin
2πf Im(Yin )
Frequency
ISQED05 28
 Simultaneous Switching Noise

More ground balls

ISQED’
05 29
Outline
• Background and motivation

• Chip Package Co-design Flow

• Signal Integrity
– Simultaneous Switching Noise

• Power Integrity
– Plane impedance and resonance

• Conclusion
ISQED’
05 30
Power Integrity
• Frequency • Time domain
domain analysis Power and
of Power Signal integrity
Planes • Signal Noise Analysis
Impedance coupled with power
• Return Path plane models
Modelling for EMI • Superposition of
and SSN analysis Power Noise on
• EMI Analysis Signal Noise
• Package Plane • IBIS, SPICE and
Resonance PEEC models are
employed
ISQED’
05 31
PDS: Power Distribution System

Detailed Network Modeling is needed for

accurate analysis of Core and IO Power

ISQED’
05 32
Ideal Package Power Planes
Early Package Design Exploration
ØPlanes have no holes or perforations
ØPerfect Microstrip or Stripline Patterns
ØImpedance is well conditioned

ISQED’
05 33
Non-ideal Package Power Planes
Detailed Plane Modeling
ØPlanes are split for different voltage domains
ØPlanes could have any number of holes / perforations
ØMicrostrip or Stripline Patterns: imperfect

ISQED’
05 34
 PDS Design
• Assign power planes in package stackup
• Assign power domains: V18, V25, Vanalog,…
• Decide via stapling
• Improve power delivery
• Reduce current loop and eliminate noise
• Assign P/G balls

ISQED’
05 35
PDS Concerns
• DC Concerns
Ø On-Chip IR Drop
ØNot a big concern in Flip-chip Designs
Ø In-Package IR Drop
ØImportant but still very small
Ø In-PCB IR Drop
ØCan be ignored
• AC Concerns
Ø Low impedance Network across a broad frequency
spectrum
Ø Reduce inductive effective to reduce SSN
Ø Control Chip/Package resonance
ISQED’
05 36
 AC-Dominant Power Plane Noise

ISQED’
05 37
 PDS Design
•PDS Impedance
•Smaller Zo ó larger current 0.05 ×Vdd
Zo =
Itransient
•PDS Bandwidth
•Maintain Zo from 0 to fmax

•Decide on Decap Allocation

•High speed drivers draw current from nearby decoupling
capacitors
•Decoupling capacitors reduce the size of the current loop

ISQED05 38
Chip-Package Plane Resonance
Resonances are produced due to inductance and capacitance

Z
Capacitor becomes inductive
beyond its self resonant
Ca

ive
pa

t
uc frequency, f(SR)
cit

d
ive

In

1 frequency
f SR =
2π LESLC
1
Resonant frequency is f max =
2π 2 L pkg C pkg

Need a set of capacitors to cover small,

medium, and high frequency ranges
ISQED’
05 39
Plane Modeling Design Flow
Package Field Solver based

Plane Geometry RLCK Extraction

RLCK netlist

Circuit Pruning

RLCK netlist

Model Order
Reduction

Frequency-domain Time-domain
Analysis
Analysis Analysis
ISQED’
05 40
 Power Plane Cuts

Plane Cut

ISQED’
05 41
 Power Plane Cuts (Island)

Island

ISQED’
05 42
 Power Domain Routing

Domain
Routing

ISQED’
05 43
 Power Domain Routing

Lower
Layer

ISQED’
05 44
 Plane Impedance
(impact of de-cap)

ISQED’
05 45
 Conclusion
• High-speed IO signaling requires package-
aware design and analysis (co-design)
• Package-aware chip IO planning improves
convergence and turnaround time
• On-chip devices are increasingly exposed to
package effects
• Power integrity is getting harder
• Efficient and accurate macro models are
needed to enable chip-package co-design
ISQED’
05 46