i INSTITUTE OF TECHNOLOGY & SCIENCE, PI A CAM! ‘SEMESTER H- 2007-2008 SS GC2 L ELE MICROPR! Si TESTI MAX MARKS: 40 DURATION: 60 MINS ‘TIME: 2.00 PM TO 3.00 PM DATE: 25/02/08 COMPONENT: OPEN BOOK Instructions: Al questions are compulsory. Ail questions should be answered serially PART-A. (6X 5 =30) 1.) Implement the function Y= AB+aA+ (BTC) using a.) only NAND gates b.) 74ALS138 & basic gates 2.) Implement the following functions using minimum number of 2- input: gates a.) 4-input XOR gate b.) 4-input NAND gate 3.) Generate a waveform with duty cycle % ,/2 and % from a shift register 4.) Reduce the following functions using K-Map a.) F(A,B,C,D)= 2(4,6,7,15) b.) F(A,8,C,0)= £(3,7,11,13,14,15) 5.) Design a counter which counts from 0 to 99 6.) Draw the output waveform for the negative edge flip-flop for the given inputs | cLK DTI an QG.K PART-B 7.)Design a synchronous counter which counts the sequence of 0, 3, 5 ,6,7,7,0... {1 X 10=10)BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, FILANI, GUA CAMEUD SEMESTER Il- 2007-2008 ES GC261 (DIGITAL ELECTRONICS AND MICROPROCESSORS) ‘TESTI MAX MARKS: 40 DURATION: 60 MINS TIME: 2.00 PM TO 3.00 PM DATE: 09/04/08 COMPONENT: CLOSED BOOK Instructions: All questions are compulsory. All questions should be answered serially PART-A (5 X 6=30) 1, Answer this question assuming that the different parts are completely independent. For each part assume that AX contains SF9C to start with and determine AX after executing the instruction.a) CMP AX, BX b)NOTAX c) SUB AL, AH d)ROR AH, 3¢)SAL AL, 4 £) MOVSX AX, AL 2. In an Intel 80286 processor, the last items stored in the stack are the following hexadecimal values: 75 (very last), FA, 1B, 9B, 12, etc. Assume SS=C300, SP=F200, ECX=30 FD 1C 56, and EAX=A9 7E 42 B8. A “PUSH CX” instruction and a “POP EAX” instruction are executed in that order. Determine the following after executing these instructions. a) ECX: b) EAX: ” c) SS: d) SP: e) Physical location of the top of stack f) Content of stack (top to bottem): 3. In an Intel 8086 processor assume SS=1000H and SP=0100H. A)How many additional bytes of data you can put into stack until it is full? B) After the stack gets Full, where does an extra byte pushed into the stack will be saved? Give the physical address. C) what is the main difference between stack segment and data segment? 4. Write a single intel instruction to replace each of the following, a) DEC AX b) LEA AX, DATI c) NOT AX d)lnvert bits number 0,5,10,15 in AX. e) Multiply the content of AX by 16. £) Set the most significant nibble in AX to 1 5. a) Compare the architecture of FPGA and 8086 microprocessor? b) Compare VHDL vs VERILOG PART-B (1X 10=10) 1. Design a 4000 series IC logic family (transistor level) for the given function. a) Y=(ATBTO)D b) YSABFCIATBDTE! LOGY & NCE. PILANI. GOA CAMPUS E EU iC iD MI ESSO} (COMPHREHENSIVE EXAM MAX MARKS: 80 DURATION: 03Hrs TIME: 9.00 AM TO 12.00 PM DATE: 08/05/08 COMPONENT: CLOSED BOOK Instructions: All questions are compulsory. All questions should be answered serially PART-A [ 4x 10 = 40 Marks] 1. (a) Construct a JK flip-flop using a D flip-flop, a 4-to-1-line multiplexer and an inverter. (b) Construct a D-latch using MUX. 2. Consider the combinational circuit shown in Fig.P4-1. (a) Derive the Boolean expressions for T; through Ty, Evaluate the outputs of F; and F2 as a function of the four inputs, (b) List the truth table with 16 binary combinations of the four inputs variables. Then list the binary values for T) through T, and outputs F; and Fp in the table. (c) Plot the output Boolean functions obtained in part (b) on maps and show that the simplified Boolean expressions are equivalent to the ones obtained in part (a). A t Dm ty ie D qT . Fy FIGURE P4-1 3, Implement the synchronous counter using T-flip flop which count the sequence Q-1-2-2-3-# ete 4. (a) Write a VHDL code for 3-input NAND Gate. (b) Compare RING counter and JOHNSON counter with diagram.PART-B [ 40Marks ] 5. For each of the following 8-bit Signed binary numbers, give the 8-bit number of opposite sign but equal magnitude. Give the decimal and hexadecimal equivalents of both the positive and negative numbers as well. (a) 00000100 (b) O1111111 () LILO 6. The double word 54892ABFh is to be stored in memory by an 8086 CPU beginning at physical address A0106h. a). Draw a diagram of how this value would be stored in memory. Be sure to indicate the physical address of each byte. ). If DS = A000h what is the offset address or effective address of this double Word? c). Now assume the address for this word is associated with ES:SL If SI= AFF6h, What is ES? 7. Answer the following questions a). Why does the 8086 use segmented memory addressing? ), What function does the BIU perform? c), Assume you were working with a microprocessor that had a 32 bit wide working registers plus two special forty bit wide registers and 40 address lines. In your opinion, would this processor need segment registers? Justify your answer and include how much memory this micro can access under your assumption. 8. Show the memory allocation for the following data segment definition. The effective address (relative to the data segment start) of the variable HERE is «data prompt1 db ‘Number1:$' numl dw ? . cr equ Odh lr equ Oah COUNT dw 0 HERE db 0 9, How many times will these loops run? MOV AX,1FH MOV CX, 10H BACK: SUB AX,1 DEC CX SNC BACK 10, What is the content of DL after the execution of the below program DATA DB 51, 44, 99, 88, 80 5MOV CX,5S MOV BX, OFFSET DATA SUB AL,AL AGAIN: CMP AL, [BX] JA NEXT MOV AL, [BX] NEXT: INC BX LOOP AGAIN MOV DL, AL 11. Write a very simple code segment (maximum 4 Instructions!) to divide C3H by A4H 12. Compare short, near and far jumps. 13. Write a program to clear bits 0 and 1.set bits 6 and 7,invert bit 5 of the content in CX. 14. Comment the intel instruction a) CLD b)CLC c) STD [10 x 3 =30Marks | 15. There are 8-10 errors in the code below. Locate and explain what the error is. By the way, this code does wild meaning. +model sathwik «stack 100h .data Phanindra DW OABCh Sanjeev DW OABCh «code . 8086 yogesh: mov ax, @data mov DS, ax mov =S, 6000h add [phanindra], [1234h] F cmp ah, bx jc yogesh: ESGC261: inc CS mov ax, OOh mov [bx tax], FFh cmp ES, ax je ESGC261 [1x 10 =10Marks ]