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© © All Rights Reserved
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/ 27
Digital Blectronics Technical Series,
DIGITAL ELECTRONICS (New Course)
Time: 3 hours Full Marka: 70
Instructions:
(i) The marks are indicated in the right-hand margin.
(ii) There are NINE questions in this paper.
(iii) Attempt FIVE questions in all.
(iv) Question No. 1 is compulsory.
1. Choose the correct. answer from the following (any seven):
Sw 2x7=14
(a) Binary number 1100110110014s equal to decimal
number > '
(i) 3289 Gi) 2289 ii) 1289 (iv) 289
Ans. (iv) aC :
Hints: decimal equivalent = £ (i=0 to n) (bix 2i)
where bi is the ith digit (counting from the right) in the
binary number and n is the total number of digits.
In this case, we have: ee
110011011001 = 1 x 241 x 29+0% 2940x274 1% 29
+1X BHROX W4+1x% 41% D+ Ox B41 20
= 1024+612132+84+4+24+1
=217
(b) If number of information bits is 11, the number of
“Parity bits in hamming code is
(5 (ii) 4 (iii) 3 (iv) 2
Ans.(ii) e
Hints: The number of parity bits in a Hamming code is
given by the formula:
Number of parity bits (p) > Log2(Number of information
bite (m) +1) +1
This formula ensures that the Hamming code can detect
and correct any single bit error. B ape
For 11 information bits. the minimum nuntben of parity Digital Electronics
[28] Technical Series
pg Skee Sie ee ee
bits is:
p > Log2(11+ I+ tad
Therefore, the number of parity bits in a Hamming code
for 11 information bits is (ii) 4. :
{o) The problem of logic race occurs in
(i) SOP function Gi) POS function
(iii) hybrid function (iv) SOP and POS function
Ans. (i) and (iii) :
Hints: A logic race is a condition that occurs in a digital
circuit when the output of the circuit changes state before
all of the inputs have reached their final values. This can
cause the circuit to produce an incorrect output.
. SOP (sum-of-products) functions are, tore susceptible
to logic races than POS (product-of-sums) functions be-
cause SOP functions have a shorter*propagation delay. A
propagation delay isthe time it takes for a change in the
input of a circuit to be reflected in the output of the cir-
cuit. HOES we = iS
Hybrid functions are also susceptible to logic races be-
cause they contain both SOP and POS.terms.
(ad) As.compared to B if ECL has Z
(i) lower power dissipation
(@ lower propagation delay
Git) higher. propagation delay
(iv) higher noise margin
Ans. (ii) >
Hints:ECL (Emitter Coupled Logic) has lower propaga-
tion delay and higher noise margin than TTL (Transistor
Transistor Logic). eg é
Propagation delay is the time it takes for a change in the
input of a logic gate to'be reflected in the output of the
gate. ECL logic gates have lower propagation delay tha?
TTL logic gates, meaning that they are faster.”
Noise margin is the ability of a logic gate to resist noise:
ECL logic gates have higher noise margin than TTL Jogi
gates, meaning that they are less susceptible to noise.
However, ECL also has higher power dissipation the"
~.- TTL, meaning that they;consume more powery, Digital Electronics 29) ‘Technical Series
(e) When two 4-bit parallel adders are cascaded, we get
(i) A-bit parallel adder (ii) 8-bit parallel'adder
_ Gii) 16-bit parallel adder (iv) None of the above
Ans.(ii)
Hints: A parallel adder is a digital circuit that adds two
n-bit numbers in parallel, It is constructed by cascading n
full adders. A full adder is a digital circuit that adds three
bits: two input bits and a carry bit.
To cascade two 4-bit parallel adders, we connect the carry
output of the first adder to the carry input of the second
adder. The sum outputs of the two adders are then con-
nected together to form the sum output of thé.8-bit paral-
lel adder. 3
( To implement the expression of ABCD + ABCD + .
ABCD it takes one OR gate and <2
|. @) one AND gate i
| (ii) three AND gates EN E
Gii) three AND gates and fourinverters _
\ (iv) three AND gates and three inverters.
| Ans.(ii) x 8 : s
i (g) Abinary ladder network D/A converter requires
} (i) resistor of one value only... : :
i) resistors of many different values
(iii) resistor of two different.values
(iv) None ofthe above :
Ans. (iii) si : :
Hints: A binary ladder network D/A converter is a type of
digital-to-analog converter that uses a series of resistors
to.convert a digital signal to an analog signal. The con-
verter uses a ladder of resistors, with each resistor hav-
ing a value of either R or 2R. The digital signal is applied
to the inputs of the ladder, and.the analog outputis taken ~
from the output of the ladder. oe
The value of the analog output is proportional to the digi-
tal input signal. The more digital inputs that are high,
the higher the analog output voltage will be.
The advantage of using a binary Indder network D/A con:
Vortan tcdhialté lode wtese pole don different-resistor Vals: 0] ‘Technical Soy, 2
+ tal Blectronics r
Di ital makes it enay to design and manufacture,
(h) Ina clocked NAND latch race condition occurs wh,
») Rand S are high and CLK is low
ye and CLK are high and S is low
Gii) R, S, CLK are high
Gv) R, §, CLK are low
ns. (iii i
me ei When the R and S inputs are both high, the oy,
put of the latch is undefined. This means that the outp,
can be either high or low, depending on which inp, t
changes state first.
If the CLK input is high, the output of the latch will
latched, or stored, in the stale that itis in at that time,
Therefore, if the R and S inputs:are both high and th
CLK input is high, the output ofthe latch can be eithe
high or low, depending on which input changes state first
This is a race condition. |.“
(i) In a 4-bit ripple counter clock pulse is applied to
(@ clock input of first FF”
(ii) clock input of second FF
Gii) clock input.of all FF ~
(iv) clock input of last FF
Ans(i) ;
Hints: A‘tipple counter is a type of asynchronous counte!
which ‘means that the flip-flops in the counter are 2° ~
clocked simultaneously. The clock pulse is applied to th’ -
first flip-flop, and the output of the first flip-flop is us* :
as the clock input for the second flip-flop, and so on.
This means that the state of the counter changes one flip
flop at.a time, with the least significant bit (LSB) chant
ing first. :
G) A bistable multivibrator acts as a
(i) logic switch
(ii) flip-flop
(iii) square wave form
(iv) None of the above Sates
Ans.(ii) os
Hiinte: A flincfion ja'a cami si tal Electronics BY Technical Series
stable states. It can be used to store one bit of informa-
ton.
A bistable multivibrator is a type of multivibrator that
has two stable states. It can be triggered to switch from
one state to the other by an external signal.
Therefore, a bistable multivibrator can be used as a flip-
flop.
(a)Convert the following octal numbers into hexa-
decimal:
(i) (362), Gi) @4: );
Ans.To convert an octal number to hexadecimal, we can fol-
low these steps:
1. Convert the octal number to decimal. ( <
2. Convert the decimal number to hexadecimal.
Converting (362), to decimal: a )
(862), =3 x 8+ 6x 81+2x 80
ater exten
= 194
Converting 194, ae
194, >= 1* 1G? +2%161+6 x16
=1x2564+.2% 16+6x1
=274,, S 5
@) Converting (241); to decimal: eS
241), = 268 + 4x 814182
“2% 6444x8411
‘Sis7
Converting 137 7, to hexadecimal:
137,,=8 x 161+ 9 x 16°
=8X16+9x1
= 137,,
Therefore, the hexadecimal equivalents of the given octal
numbers are:
(362), 274,,
QAN), =137,,
(b) Convert the following numbers into binary numbers :
(639), (i) (338.2),
Ans. (i) Convert (539) 10 to binary: ¥ =
We can use the method of successive division by 2:to con- vert the de
9 remainder 1
269 / 2 = 134 remainder 1
7 remainder 0
33 remainder 1
33/2= 16 remainder 1
16/2=8 remainder 0
8/2=4 remainder 0
4/2=2 remainder 0
2/2= 1 remainder 0
1/2=0 remainder 1 S
Now, reading the remainders from Botton to top, We get
the binary representation of 539: Ss
(639)10 = (1000011011), Go
(ii) Convert (338.2)16 to binary: SN
First, let's convert. the integer part (338)
, Mal to binary. We'll convert ead! hexad
5 4-bit binary representati e
Boe 3 (hex) = 0011 (binaryy
F 3 (hex) = 0011 (binary)
8 (hex) = 1000 eas)
Now, concatenate these binary representations:
(338)16 100011000)2 *
bi Next, let's convert the fractional part (0:2) from hexadeci- «
| bi We'll convert the hexadecimal digit "2" to
its 4-bit binary representation:
2 (hex) = 0010 (binary)
i Now, concatenate this binary representation with the in-
teger part we calculated earlier:
(838.2)16 = (00110001 1000.0010),
So, (338.2)16 in binary is (001100011000.0010)2.
(c) Convert the gray code number 110011 to binary. :
Ans. Write down the leftmost digit (the most significant bit)
of the Gray code as.is. In this case, it's "1," so we write
down "1" for the binary representation.
For each subsequent digit in the Gray code from left a"
right, XOR it with the corresponding digit in the binatY |
representation obtained so far. Write down the result *
5 [32] Technical Serj,
igital Electronics 5 ; “ee
r piste he mal nuniber 589 into binary. ] Digital Electronics (33) Technical Series
the next digit in the binary representation.
Gray code: 110011
Binary so.far: 1
XOR the next Gray code digit (1) with the last binary digit
(D:
1XOR1=
Add the result to the binary representation:
Binary so far: 10
Gray code: 110011
Binary so far: 10
XOR the next Gray code digit (0) with the last binary digit
(0):
0XORO=0 =
Add the result to the binary eee
Binary so far: 100 @
Gray code: 110011 - Qe
Binary so far: 100° <=
XOR the next Gray code digit swith the last binary digit.
(0): 3
SO
OXOR0=0 o SES
Add the result to the biary representation: Stes
2 A S
Binary so far: 1000. 2
Gray code:
10011°~
Reey so far: 1000: S
XOR the next ray code digit @) with the: last binary digit ©
Q@:-
1XOR1=0 = =
Add the result to the Minar representation:
Binary so far: 10000
Gray code: 110011
Binary so far: 10000 ee
XOR the last Gray code digit (1) with the last binary digit
(0): Se
- 1XORO=.1 3
Add the result to the binary representation:
Binary so far: 100001
So, the Gray code "110011" is equivalent to the binary Digital Electronics {34 Technical Seri,
number "100001."
(d) Explain weighted and non-weighted codes, L
Aus.Weighted codes are those in which each digit POSitin,
is assigned a specific weight. The sum of the weights :
the digits in a weighted code number is equal to the deci
mal value of the number. For example, in the binary cod,
decimal (BCD) code, the weights of the digits are 8,4 4
and 1. The BCD representation of the decimal numbe,
539 is 1000011011,, which is equal to '
8x 1+ 4xO+2xO+ 1x 1t+8x1+4xO0+2x Bey xe
= 539.
Non-weighted codes are those in which the digit posi.
tiuns are not assigned specific weights-The decimal valu:
of a non-weighted code number 32 Ro imply the sum o
the weights of the digits. For “ie e, in the Gray code,
the decimal value of a number letermined by the num-
ber of times the bits change 0.to lor-vice versa. The ~
Gray code representatio: the decimal number 539 is --
1000011111, which is qual to the. sum of the weights —
of the digits. :
Weighted soos often used for arithmetic operations,
as they can be sily converted to decimal numbers. Nou-
weighted $s are often used for error detection and
correction oe they have the property that. only one bi
_ changes When a number is incremented ur decresiented
3.(a) What are De Morgan's theorems? Write them it
equation form. Prepare their truth table.
Ans. De Morgan's theorems are two laws in Boolean algebté
that express the relationship between the logical oper®
tors NOT, AND, and OR. The theorems state that:
Theorem 1: The complement of the AND of two variable?
is equal to the OR of the complements of the individu”
variables.
Theorem 2: The complement of the OR of two variablé
is equal to the AND of the complements of the individu"
variables.
In equation form, De Morgan's theorems can be writ!” [35] ‘Technical Series
Digital Elect
8 follov
. rn AND B)'= A' OR B'
(AOR B)'=A' AND B' :
where A and B are any two Boolean variables.
The truth table for De Morgan's theorems is as follows:
A | B | (A ANDB)'| A'OR B'| (AOR B)' | A'ANDB'
O10 1 | 1 1
oll 1 1 0 0
10 | | 0 0
ijt 0 0 0 0.
As you can see, the truth table shows that De Morgan's
theorems are always true, regardless o} the values of the
variables A and B. SS
De Morgan's theorems are very ugfid in digital logic de-
sign and Boolean algebra. The be used :to simplify
Boolean expressions, aan circuits, and implement
Boolean functions.
6) Simplify the eon a draw a circuit to realize
ne function :
=(A+B) eee C).+ AB+ ABC
ee To simplify th tion, we can use the following Bool-
ean algebra i les: =
. an 3
Applying these identities, we can simplify the function as
follows:
Y=(A+B) (A+ AB) C+A (B+ C) + AB + ABC
=(A+B)C+A(B+C)+AB+ ABC
=AC+BC+AB+AC+ABC+AC
= ABC + AC + BC+ AB
= ABC + AC + BC
= AC + BC (since ABC is already included in BC)
Therefore, the simplified function is Y = AC + BC.
4.(a) Draw a circuit diagram of DTL gate and explain it. What
are fan in and fan out?
) Draw a circuit diagram of RTL gate apd explain its work-
ine. pe. 71 4 i 36 Tochnien) @... EDER
Digital Electronics : 7 i a Technical Sotiy
Ans. TL gate crrew *
Ans. (a) DI ve ne
(b)
ANPUTS:
Explanation: ‘ <<
A DTL gate circuit consists of two parts: a diode input
stage anda transistor output. stage. ~
The.diode input stage consi 8 of one or more diodes, de-
pending on the number te to the gate. Each diode
is connected in series with one of the gate-inputs. If a gate
input is at a high voltage level, the corresponding diode
will be forward biased.and conduct current. ‘This wil! turn
on the transistor in the output stage.
The transistor? output stage consists of a’single transis-
tor. The sistor is connected ina common emitter con-
figuration. The base of the transistor is connected to the
output of the diode input stage. When the transistor is
turned on, it conducts current from the collector to the
emitter. This current flows through the load resistor and
produces a high voltage level at the output of the gate.
Fan-in and fan-out: ‘
Fan-in: The fan-in of a gate is the maximum number
inputs that the gate can drive without its output voltas®
being degraded.
Fan-out: The fan-out of a gate is the maximum numbe
of gates that the gate can drive without its output voltas®
being degraded.
The fan-in and fan-out of a DTL gate ‘depend on the type
ele iene ae t the sae
. G
DTI. gate cirouit’diagram | \
> Digital Electronics (37) 1
gate using a bipolar junction transistor (BAT)
lower fan-out than a DITL gate using a field-effect transia-
tor (FET).
(b) RTL gate circuit diagram:
have a
+Vec
Output
Explanation:
An RTL gate circuit consi is of two resistors and one tran-
sistor. The two resistors form a voltage divider. The tran-
sistor is connecte a common. collector-configuration.
The input to the ga is connected to the base of the tran-
sistor, >
When the input to the gate is at a high voltage level, the
transistor at be turned on and conduct current: This will
cause the output voltage of the gate to be pulled down toa
‘low voltage level.
When the input to the gate is at a low voltage level, the
transistor will be turned off. This will cause the output
Voltage of the gate to be pulled up toa high voltage level
by the voltage divider.
Advantages of RTL gates:
TL gates are very fast. ;
RTL gates are relatively simple to design and implement.
isadvantages of RTL gates: : 5
RTL gates ceaslins siara poe than other types of logic
gates, such as DTL and TTL gates. of logic gates. : . ;
RTL gates were widely used in early digital computer,
However, they have been largely replaced by other typo,
of logic gates, such as DTLand TTL gates, in modern dig.
tal systems.
5.(a) Draw the circuit of half adder and full adder ang
discuss their working. Draw their truth table.
Ans. Half Adder Circuit:
A
SUM(S)
Working: Ks) bs
A half adder circuit has two inputs (A and B) and two
outputs (Sum-and Carry, e Sum output is the sum of -
the two input bits, and: Carry output is the carry bit
generated by the addition.
The half adder. cirenit works as follows:
1. If both input bitaare low (A=0'and B = 0), then the Sum
output will be low and the Carry output will be low.
2. If one input bit is high and the other input bit is low (A=
land 0 or A=0 and B='1), then the Sum output wil
be high and the Carry output will be low.
3. If both input bits are high (A = 1 and B = 1), then the Sut
output will be low and the Carry output will be high.
Truth Table:
A| B | Sum | Carry
olo| o | o
ofi{ 1 [oo
}}oO| 4 “0
1}1} 0 1
Full Adder Circuit; (394
\ i Teokinical Maries
Tyjriva Feet ani neeanttnimamaen SHIM) Meer
i)
e
=D tO
ae — JJ an
Working
A full adder circuit has three inputs (A, B, 4 ny and
two outputs (Sum and Cout). The A and B inputs are
two hits to be added, and the Cin inputdy the carry |
from the previous addition. The Surn o fitpul the zor of
the three input bits, and the Cout output is the carry bit
generated by the addition, y
= 0,2 =0, and Cin =O),
then the Sum output will be low and the Cout output will
be low.
The full adder circuit wor 4 follows:
- If all three input bits are 1
=1, and Cin=0
. Iftwo input bits eed anon input bitis low (A=1, 2B
1, B=0, and Cin = 1orA=6,B=
1, and Cin en the Sum output will he high and the
Cout outp be low.
If all three input bits are high (A= 1, B= 1, and Cin = 1),
then the Sum output will be low and the Cout output will
be high.
Truth Table: [40]
(b) What is a decoder
truth t
Ans. A decoder is a con
has n inpul
Digital Blectronice__[00}___Pechnical Sx
® Draw the complete circ
able of a 4 line to 16 line decoder. 7 +
mbinational logic circuit that conve
a binary code into a set of mutually exclusive output
t lines and 2*n output lines. The input lip
represent the binary code, and the output lines indi:
which of the 2” possible values the binary code represen;
4-line to 16-line decoder circuit:
[Sassssssee
PIN 14 +5V
PIN7 = GND
For {C2 and 1C3
PIN 16= +5V
PIN 8 = GND
* Figure 1: 4-Line to 16-Line Decoder Circuit using aa?
B,C,
D15). Th
output li
binary
Only one
fifteen o
high ind
code rep:
For exa
line D5v
This ind
value 5.
4-line to
tions, suc
are also
micropro Digital Electronics {40}
(b) What is a decoder? Draw the complete ¢
truth table of a 4 line to 16 line decoder. 7 +7 =|
Ans. A decoder.is a combinational logic circuit that ed
a binary code into a set of mutually exclusive outputs
has n input lines and 2*n output lines. The input lin
yepresent the binary code, and the output lines indies
which of the 2" possible values the binary code represen,
4-line to 16-line decoder circuit: ‘
‘Technical Ser,
\c2 Out,
FS
Sto
fo
Sbdsss
For tcl.
PIN 14350.
PIN7 » GND.
For {C2 and 1C3
PIN 16=45V
PIN R= GND
~ Figure 1: 4-Line toi1@-Line Decoder Circuit using 4” | pigital Klectronios M4) Technical Serica
\ Truth table: =
\ Input | Output
bo
DIO
DI2
D13
Di4
DiS
Working: << .
The 4-line to 16-line decoder circuit has four input lines
(A, B, C, and D)and sixteen output lines (DO, D1, D2, ...,
D15). The inptit lines represent the binary code, and the
output lines indicate which of the 16 possible values the
binary code represents.
Only one output line will be high-at a time, and the other
fifteen output lines will be low. The output line that is
high indicates which of the 16 possible values the binary
code represents.
For example, if the input code is 0101, then the output
line D5 will be high and all other output lines will be low.
This indicates that the binary code 0101 represents the
value 5. .
4-line to 16-line decoders are used in a variety of applica-
tions, such as memory addressing and data selection. They
are also used in more complex digital circuits, such as
Inicroprocessors and dicital signal processora Digital Electronics _17] ‘Technical g,,, Di
6. (a) Explain the following flip-flops with their &
grams and truth tables : in
(i) SR _ Gi) J-K
(i) DFF (iv) TFF
Ans, (i) SR Flip-Flop
ASR flip-flop is a sequential logic circuit with two inpy,
(S and R) and two outputs (Q and Q'). The S input sets 4
output Q to 1, and the R input resets the oulput Q to;
The flip-flop has two states: set and reset. i
SR flip-flop circuit diagram:
s ————_
CLK —t
al’
* oS
Truth Table - SS
S|R é Q
o}o No change
O}l J
I ar 1 0
7 . oh Invalid Invalid”
Invalid ombination: G
The combination of S = 1 and R = Lis invalid, as itoam™
be determined whether the oulpul Q should be set r
ae In this case, the output of the flip-flop is unpr? i
able. : ;
(ii) J-K Flip-Flop if
AJd-K flip-flop is a sequential logic circuit with two int
(J and K) and two outputs (@ and @), The J input =")
output Q to 1, and the K input resets the output ¢ ai
The flip-flop has four states: set, reset, toggle. and he
J-K flip-flop circuit diagram: igual ——
eee et
I Ne
SC
Truth Table
i{k Q Q
0 | 0 | NoChange | No Change
oj1 0 Ik
1,0 1 0
1] 1] Toggle Toggle
Toggle:
If both J and K inputs are high, then the output Q will -
toggle on the next clock edge. This means that the output
Q will change from 0 veer 1 to 0, depending on its cur-
rent state. Ss
Hold: < ‘
If both J and Shputs are low, then the output Q will
remain in its current state on the next clock edge.
(iii) D Flip-Flop :
AD flip-flop is a sequential logic circuit with one input
(D) and two outputs (Q and Q'). The D input is the data
input, and the output Q follows the data input on the next
clock edge.
D flip-flop circuit diagram:
‘SR & D Flip Flop TruthTable y Digital mlectronics. Sie
=&chnical Serj,
(iv) T Flip-Flop fey
AT flip-flop is a sequential logic circuit with one in,
and two outputs (Q and Q'). The T input is the ty,
put, and the output Q toggles on the next clock ed,
T input is high. :
T flip-flop circuit diagram:
Put (‘p '
BBle in,
Se if th,
T Qa
0 | No change | No change
1 Toggle Toggle
Flip-flops are essential components of digital circuits. They.
are used in a variety of applications, such as registe!s
counters, and sequential logic controllers.
(b) Design DFF from JK FF. Teta
Aus. To design a D flip-flop (DFF) from a JK flip-flop (KF.
we can use the following steps: of
Connect the D input of the DFF to the J and K inputs
the JKFF, eo
Connect the Q output of the DFF to the feedback inp™
the JKFF, ‘ oy,
The following circuit diagram shows a DFF imP
mented using a JK FF:
f Working:
The D input of the DFF is
(CLK) input is high, the output Qoft a
data input D. The feedback input of #]
the data input. Si the clock
'F follows the
ethe JKFIS ensures
that the output Q remains in its 3 ot ‘rent state until the
next clock edge, ~
Example:
sy
Suppose the data input Dis high, When the clock input
CLK goes high, the output Q of the DFF will also go high,
‘The feedback input JKFF will then ensure that the
output Q remains ig! until the next clock edge.
Even if the cata np D goes low after-the clock input
CLK goes high,” he output Q of the DFF will remain high
until the next clock edge. This is because the feedback
input of the JKFF will keep the output Q high.
Advantages of using a JKFF to implement a DFF:
‘JKFFs are more common and widely available than DFFs.
* JKFFs can be used to implement other types of flip-flops,
such as 'I' flip-flops and SR flip-flops.
isadvantages of using a JKFF to implementa DFF:
* The circuit is more complex than a direct implementation
ofa DFF,
* The circuit is more susceptible to noise.
7(a)Draw the circuit of a 3-bit synchronous counter
and explain its working. 5
Ans, The following circuit diagram shows « 3-bit synchro 7 : LEN,
nous counter: “Hey
Clock
Sbit synchronous counter circuit dia:
The counter consists of three D flip- (DFFs), Q0, Ql,
and Q2. The clock input (CLK) is:connected to all three _
DFFs. The output of each DEF ectetl to the D input —
of the next DFF. A
Working:
When the clock input Sa high, the output of each ©
DFF follows its D iny ‘he D input of each DEF is de- ©
termined by the o it of the previous DFF and the state.
of the counter. “ f
The followin; table ahi the state transition table for
the’8-bit synchronous counter: z=
O°” [Girrent state | Next state
000 001
001 010
010 01
ou 100
too 10r &
iol Ho /
lo WW
MW 000 | i
‘The counter starts in the state 000 and increments by e
on each.clock edge. When the counter reaches the
111, it overflows and returns to,the state 000. tq) Electronics 7) echnical Series
“The 3-bit synchronous counter can be used to count up to
Seight events. It is a versatile circuit that can be used ina
variety of applications, such as digital clocks, frequency
dividers, and sequencers,
(v) Draw the cirenit of a parallel IN-scrial OUT shift
register and explain its working. T+7=14
Ans. The following circuit diagram shows a parallel in se-
rial out (PISO) shift register:
1|B oc ap
ShiftiLoad | 9
dI@le olwee
1 0 1
Al Aye, foe aNG NA
Da ne Ds.
* es ec [> Sexist Data
Le ; on
CLE
» PISO shift register circuit diagram
The shift register consists'of four D flip-flops (DFFs), QO,
Q1, Q2, and Q3. The clock input (CLK) is connécted to all
four DFFs. The fous parallel input lines (DO; D1,;D2, and
D8) are connec Lto the D inputs of the DFFs. The serial
output line ( Ss connected to the Q output of the last
DFF (Q8). =
Working: ~ “ :
When the clock input CLK goes high, the output of each
DFF follows its D input. The D input of each DFF is de-
termined by the parallel input line (DO, D1; D2, or D3)
and the state of the shift register. .
The shift register starts in the state 0000. When the clock
input CLK goes high, the D inputs of the DFFs are deter-
mined by the parallel input lines (DO, D1, D2, and ve
¢ serial output line (Q) is connected to the Q output ee
the last DFF (Q3), so the first bit of the parallel inp
word is output on the serial output line. :
On the vex clock edge, the D inputs of the ee
determined hy the outputs of the previous DFFs. The s Digital Electronics [48] Technical Sey,
8. (a) Draw the circuit of parallel A/D converter and —
Ans. The converter ons
‘divider, w1
rial output line (Q) is now connected to the Q outpuys
the second DFF (Q2), so the second bit of the paralley ;
put word is output on the serial output line.
‘This process continues until all four bits of the Para]
Jel input word have been output on the serial output lin,
The shift register then returns to the state 0000 anq;
ready to receive the next parallel input word,
PISO shift registers are used in a variety of applica. -
tions, such as data transmission, data conversion, and dat, ee
storage. "
The following table shows the state transition table for
the PISO shift register:
Current state | Next state
0000 DOD1D2D3
DODID2D3 DID2D3Q0
D1D2D3Q0 | D2D3Q0Q1
D23Q0Q1 | N3IQNQ : : =
D3Q0Q1Q2 ee |
ty
explain its working. :
ists of a comparator for each possible
comparators are connected to a voltage’
produces a set of reference voltages. The
e is compared to each reference voltage in turn. *
The comparator output with the highest voltage is the
output code of the converter. 5
Working: s f
The input voltage (Vin) is applied to the voltage divider
The voltage divider produces a set of reference voltages
which are connected to the inputs of the comparators. The
output of each comparator is a digital signal, which is Vy
the input voltage is greater than the reference voltage «™°
O if the input voltage is less than or equal to the referen®
voltage. i 7 ‘
The outputs of the comparators are connected to 4 prior
ity encoder. The priority encoder selects the highest”
der comparator output and generates the.output cof?"
output code. ‘pigital Electronica [49]
the converter.
The following circuit dingram shows a parallel A/D con-
vortor, also known nea flash A/D converter:
Technical Series
Binary
Output
The following table shows the truth table for the parallel.
AID converter:
Vin- Comparator outputs | Priority encoder output
