Tutorial Feb 20
Tutorial Feb 20
2/23/2024 2
Numerical 3
• A CS amplifier using an NMOS transistor is biased as shown below, for which gm =
2mA/V is found to have an overall voltage Gv of -16 V/V. What value should a
resistance Rs inserted in the source lead to have to reduce the voltage gain by a
factor of 4?
2/23/2024 3
Numerical 4
• For the NMOS amplifier in Fig. P4.74,
replace the transistor with its T equivalent
circuit of Fig. 4.39(d). Derive expressions
for the voltage gains vs /vt and vd /vi