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Inputs For PD

The input files for physical design include the netlist, SDC, technology file, TLU Plus files, logical libraries, and physical libraries. The netlist contains the connectivity of all cells and macros. The SDC contains timing constraints. The technology file contains layer properties. TLU Plus files contain parasitic RC information used for timing analysis. Logical libraries contain timing and power information for standard cells. Physical libraries contain placement rules and routing restrictions.

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Balakumaran Durairaj
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17 views

Inputs For PD

The input files for physical design include the netlist, SDC, technology file, TLU Plus files, logical libraries, and physical libraries. The netlist contains the connectivity of all cells and macros. The SDC contains timing constraints. The technology file contains layer properties. TLU Plus files contain parasitic RC information used for timing analysis. Logical libraries contain timing and power information for standard cells. Physical libraries contain placement rules and routing restrictions.

Uploaded by

Balakumaran Durairaj
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Input Files For

Physical Design

https://www.linkedin.com/in/vivek-arya-532558143
Netlist
-
all
connectivity of
↳ It contains logical
cells Macros
cells (standard ,

the
↳ Used in the design for knowing
lines
connectivity by using fly .

( V)
.
Netlists are
often generated
in Verilog .

SDC (Timing Data)


--

↳ create clock period

↳ Generated clock definition


↳ Disable timing arc

constraints
↳ Timing
Path
,
Exceptions (multicycle
↳ Timing
Half cycle path ,
false path)
max
↳ Input day ,
output clay ,

day ,
min day .
file
nology
↳ color and pattern

↳ Unit and precision


number and conventions of the
↳ Name ,

and vias
layers .

& electrical chara-


↳ Physical
steritics of layers and via.

and
↳ kitch s width
spacing .

TLU Plus
-

↳ RC parasitics of metal

per unit -
↳ rif not available
, Wil

can give · ITF file .

↳ To load that fils we

need man TLU , min TLU and

Map files .

↳ Map file-maps the off


and off file of the

layer and via names .

↳ RC parasitics are used

for calculating not


delays .

↳ That is more accurate .

https://www.linkedin.com/in/vivek-arya-532558143
libraries
gical
↳
contain timing information
↳ It

of std cells , soft macros


,

hard macros .

↳ Functionality of Sta cells


,

soft macros .

↳ contain power inform-


ation .

power , output
↳ Leakage
Voltage and input voltage
also defined
for Sta
each
cell .

https://www.linkedin.com/in/vivek-arya-532558143
https://www.linkedin.com/in/vivek-arya-532558143
4 Design rubs-max trans ,

max cap and max fanout .

↳ there are different logical


for PUT
files different
corners
.

Physical
-
Libraries

physical information
↳It contain
cells macros , pads -

of std ,

↳ unit tile information

Height of placement rows


↳
↳ bin information

https://www.linkedin.com/in/vivek-arya-532558143
Antenna roles
↳
↳ routing blockages
↳ contain preferred routing
width
directions ,
minimum of

the resolution
.

https://www.linkedin.com/in/vivek-arya-532558143

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