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For CL Verilog

This document discusses Verilog code for combinational circuits. It begins with an agenda that includes Verilog structure, data types, system tasks, and code examples for all gates, multiplexers, half adders, full adders, encoders, and decoders. It then provides details on Verilog structure and syntax, data types including wires and regs, and system tasks like $display, $monitor, $stop, and $finish. Examples of Verilog code are provided for all gates, multiplexers using ternary operators, half adders, and full adders. The document concludes with an overview of encoder and decoder Verilog code.

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nikhidad06289
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41 views

For CL Verilog

This document discusses Verilog code for combinational circuits. It begins with an agenda that includes Verilog structure, data types, system tasks, and code examples for all gates, multiplexers, half adders, full adders, encoders, and decoders. It then provides details on Verilog structure and syntax, data types including wires and regs, and system tasks like $display, $monitor, $stop, and $finish. Examples of Verilog code are provided for all gates, multiplexers using ternary operators, half adders, and full adders. The document concludes with an overview of encoder and decoder Verilog code.

Uploaded by

nikhidad06289
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Combinational Circuits Using Verilog code

Agenda
Verilog Structure
Data Types
System Tasks
All Gate Verilog code
Mux Verilog code
Half Adder Verilog code
Full Adder Verilog code
Encoder Verilog code
Decoder Verilog code
What is Verilog why veriog
Verilog is a Hardware Description Language; a textual format for describing electronic circuits
and systems. Applied to electronic design, Verilog is intended to be used for verification through
simulation, for timing analysis, for test analysis (testability analysis and fault grading) and for
logic synthesis.
Verilog is used to describe digital circuits and systems, while C and Java are used to write
software programs that run on computers. Syntax: Verilog has a different syntax than C and Java,
as it is designed to describe the behavior of digital circuits rather than the execution of software
instructions
Verilog Structure:
Verilog Module Syntax

module module_name (module_terminal_list);

---------------------
--------------------

<module internals>

------------------------
------------------------
endmodule
Data Types
➢Wire
wire doesn’t hold a vale it just pass a value
Default value of wire is “Z”
syntax:-
wire a; // Declare net a for the circuit
wire a,b //Declare two wires b,c for the circuit
wire d= 1’b0; // Net D is fixed to logic value 0 at declaration
➢Reg
Reg hold a value until another value is placed onto them
Default Value of Reg is “X”
Syntax:-
reg q;
reg clock;
reg[0:2] s;
System Tasks
$Display is the main system task for displaying values of variables or strings or expressions.

Syntax:-

$display($time=%t,a=%b,b=%b,a,b);

$Monitor Monitors change in the value of signal. Signal can be variable, strings or expression.

Syntax:-

$moitor($time=%t,a=%b,b=%b,a,b);

$strobe:-
It is a synchronization mechanism in which data is displayed only after all other statements are executed unlike
$display in which execution order could be nondeterministic.
Conti..
$stop
The $stop task puts the simulation in an interactive mode.The $stop task is used whenever the designer wants to suspend the simulation and
examine the value of signals in the design.

$finish
The $finish task terminate the simulation.

Syntax:-
initial
begin
clock=o
reset=1;
#100 $stop;// This will suspend the simulation at time =100
#900 $finish;// this will terminate the simulation at time =1000
end
ALL gates Verilog Code
Mux Verilog code using Ternary Operator
Half Adder Verilog code
Full Adder Verilog code
Encoder Verilog Code
Decoder Verilog code
THANK YOU
PRESENTED BY :
MOUNIKA
Y SURYA

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