SiC533

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Vishay Siliconix
35 A VRPower® Integrated Power Stage
DESCRIPTION FEATURES
The SiC533 is an integrated power stage solution optimized • Thermally enhanced PowerPAK® MLP4535-22L
for synchronous buck applications to offer high current, high package
efficiency, and high power density performance. Packaged • Vishay’s Gen IV MOSFET technology and a
in Vishay’s proprietary 4.5 mm x 3.5 mm MLP package, low-side MOSFET with integrated Schottky
SiC533 enables voltage regulator designs to deliver up to diode
35 A continuous current per phase.
• Delivers up to 35 A continuous current, 40 A at 10 ms peak
The internal power MOSFETs utilize Vishay’s current
state-of-the-art Gen IV TrenchFET® technology that delivers
• High efficiency performance
industry benchmark performance to significantly reduce
switching and conduction losses. • High frequency operation up to 2 MHz
The SiC533 incorporates an advanced MOSFET gate driver • Power on reset
IC that features high current driving capability, adaptive • 5 V PWM logic with tri-state and hold-off
dead-time control, an integrated bootstrap Schottky diode, • Supports PS4 mode light load requirement for IMVP8 with
and zero current detection to improve light load efficiency. low shutdown supply current (5 V, 3 μA)
The driver is also compatible with a wide range of PWM
controllers, supports tri-state PWM, and 5 V PWM logic. • Under voltage lockout for VCIN

A user selectable diode emulation mode (ZCD_EN#) is • Material categorization: for definitions of compliance
included to improve the light load performance. The device please see www.vishay.com/doc?99912
also supports PS4 mode to reduce power consumption
when system operates in standby state. APPLICATIONS
• Multi-phase VRDs for computing, graphics card and
memory
• Intel IMVP-8 VRPower delivery
- VCORE, VGRAPHICS, VSYSTEM AGENT Skylake, Kabylake
platforms
- VCCGI for Apollo Lake platforms
• Up to 24 V rail input DC/DC VR modules

TYPICAL APPLICATION DIAGRAM

5V VIN
VDRV

VIN

BOOT

VCIN PHASE

ZCD_EN#
VSWH
Gate VOUT
PWM
controller PWM driver
PGND
CGND

GL

Fig. 1 - SiC533 Typical Application Diagram

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PINOUT CONFIGURATION

PGND

PGND

PGND

VIN

VIN

VIN
11 10 9 8 7 6

25
VSWH 12 5 PHASE
VIN
26
VSWH 13 PGND 4 BOOT

VSWH 14 3 N.C.
23
VSWH 15 CGND 2 VCIN

VSWH 16 24 1 ZCD_EN#
GL

17 18 19 20 21 22
PGND

PGND

GL

PGND

VDRV

PWM
Fig. 2 - SiC533 Pin Configuration

PIN DESCRIPTION
PIN NUMBER NAME FUNCTION
The ZCD_EN# pin enables or disables Diode Emulation. When ZCD_EN# is LOW, diode
emulation is allowed. When ZCD_EN# is HIGH, continuous conduction mode is forced.
1 ZCD_EN# ZCD_EN# can also be put in a high impedance mode by floating the pin. If both ZCD_EN#
and PWM are floating, the device shuts down and consumes typically 3 μA (9 μA max.)
current
2 VCIN Supply voltage for internal logic circuitry
23 CGND Analog ground for the driver IC
This pin can be either left floating or connected to CGND.
Internally it is either connected to GND or not internally P/N P/N

3 N.C. connected depending on manufacturing location. LL LL

Factory code “G” on line 3, pin 3 = CGND GYWW TYWW

Factory code “T” on line 3, pin 3 = not internally connected
4 BOOT High-side driver bootstrap voltage
5 PHASE Return path of high-side gate driver
6 to 8, 25 VIN Power stage input voltage. Drain of high-side MOSFET
9 to 11, 17, 18, 20, 26 PGND Power ground
12 to 16 VSWH Switch node of the power stage
19, 24 GL Low-side gate signal
21 VDRV Supply voltage for internal gate driver
22 PWM PWM control input

ORDERING INFORMATION
PART NUMBER PACKAGE MARKING CODE
SiC533CD-T1-GE3 PowerPAK® MLP4535-22L SiC533 5 V PWM optimized
SiC533DB Reference board

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PART MARKING INFORMATION

= pin 1 indicator

P/N = part number code

P/N = Siliconix logo
= ESD symbol
LL F = assembly factory code
Y = year code
FYWW WW = week code
LL = lot code

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL PARAMETER CONDITIONS LIMIT UNIT
Input voltage VIN -0.3 to +28
Control logic supply voltage VCIN -0.3 to +7
Drive supply voltage VDRV -0.3 to +7
Switch node (DC voltage) -0.3 to +28
VSWH
Switch node (AC voltage) (1) -8 to +35
BOOT voltage (DC voltage) 33 V
VBOOT
BOOT voltage (AC voltage) (2) 40
BOOT to PHASE (DC voltage) -0.3 to +7
VBOOT- PHASE
BOOT to PHASE (AC voltage) (3) -0.3 to +8
All logic inputs and outputs
-0.3 to VCIN + 0.3
(PWM and ZCD_EN#)
Max. operating junction temperature TJ 150
Ambient temperature TA -40 to +125 °C
Storage temperature Tstg -65 to +150
Human body model, JESD22-A114 2000
Electrostatic discharge protection V
Charged device model, JESD22-C101 1000
Note
• Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
(1) The specification values indicated “AC” is V
SWH to PGND, -8 V (< 20 ns, 10 μJ), min. and 35 V (< 50 ns), max.
(2) The specification value indicates “AC voltage” is V
BOOT to PGND, 40 V (< 50 ns) max.
(3) The specification value indicates “AC voltage” is V
BOOT to VPHASE, 8 V (< 50 ns) max.

RECOMMENDED OPERATING RANGE

ELECTRICAL PARAMETER MINIMUM TYPICAL MAXIMUM UNIT
Input voltage (VIN) 4.5 - 24
Drive supply voltage (VDRV) 4.5 5 5.5
V
Control logic supply voltage (VCIN) 4.5 5 5.5
BOOT to PHASE (VBOOT-PHASE, DC voltage) 4 4.5 5.5
Thermal resistance from junction to PCB - 5 -
°C/W
Thermal resistance from junction to case - 2.5 -

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ELECTRICAL SPECIFICATIONS
(ZCD_EN# = 5 V, VIN = 12 V, VDRV and VCIN = 5 V, TA = 25 °C, unless otherwise stated)
LIMITS
PARAMETER SYMBOL TEST CONDITION UNIT
MIN. TYP. MAX.
POWER SUPPLY
VPWM = FLOAT - 80 -
Control logic supply current IVCIN VPWM = FLOAT, VZCD_EN# = 0 V - 120 - μA
fS = 300 kHz, D = 0.1 - 300 -
fS = 300 kHz, D = 0.1 - 7.5 12
Drive supply current IVDRV mA
fS = 1 MHz, D = 0.1 - 25 -
VPWM = VZCD_EN# = FLOAT,
PS4 mode supply current IVCIN + IVDRV - 3 9 μA
TA = -10 °C to +100 °C
BOOTSTRAP SUPPLY
Bootstrap diode forward voltage VF IF = 2 mA - - 0.65 V
PWM CONTROL INPUT
Rising threshold VTH_PWM_R 3.6 3.9 4.2
Falling threshold VTH_PWM_F 0.72 1 1.3
Tri-state voltage VTRI VPWM = FLOAT - 2.5 - V
Tri-state rising threshold VTRI_TH_R 1.1 1.35 1.6
Tri-state falling threshold VTRI_TH_F 3.4 3.7 4
Tri-state rising threshold hysteresis VHYS_TRI_R - 325 -
mV
Tri-state falling threshold hysteresis VHYS_TRI_F - 250 -
VPWM = 5 V - - 350
PWM input current IPWM μA
VPWM = 0 V - - -350
ZCD_EN# CONTROL INPUT
Rising threshold VTH_ZCD_EN#_R 3.3 3.6 3.9
Falling threshold VTH_ZCD_EN#_F 1.1 1.4 1.7
Tri-state voltage VTRI_ZCD_EN# VZCD_EN# = FLOAT - 2.5 - V
Tri-state rising threshold VTRI_ZCD_EN#_R 1.5 1.8 2.1
Tri-state falling threshold VTRI_ZCD_EN#_F 2.9 3.15 3.4
Tri-state rising threshold hysteresis VHYS_TRI_ZCD#_R - 375 -
mV
Tri-state falling threshold hysteresis VHYS_TRI_ZCD#_F - 450 -
VZCD_EN# = 5 V - - 100
ZCD_EN# input current IZCD_EN# μA
VZCD_EN# = 0 V - - -100
PS4 exit latency tPS4EXIT - - 5 μs
TIMING SPECIFICATIONS
Tri-state to GH/GL rising
tPD_TRI_R - 20 -
propagation delay
Tri-state hold-off time tTSHO - 150 -
GH - turn off propagation delay tPD_OFF_GH - 20 -
GH - turn on propagation delay
tPD_ON_GH No load, see Fig. 4 - 20 - ns
(dead time rising)
GL - turn off propagation delay tPD_OFF_GL - 20 -
GL - turn on propagation delay
tPD_ON_GL - 20 -
(dead time falling)
PWM minimum on-time TPWM_ON_MIN 30 - -
PROTECTION
VCIN rising, on threshold - 3.4 3.9
Under voltage lockout VUVLO V
VCIN falling, off threshold 2.4 2.9 -
Under voltage lockout hysteresis VUVLO_HYST - 500 - mV
Notes
(1) Typical limits are established by characterization and are not production tested
(2) Guaranteed by design

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DETAILED OPERATIONAL DESCRIPTION
PWM Input with Tri-State Function Switch Node (VSWH and PHASE)
The PWM input receives the PWM control signal from the VR The switch node, VSWH, is the circuit power stage output.
controller IC. The PWM input is designed to be compatible This is the output applied to the power inductor and output
with standard controllers using two state logic (H and L) and filter to deliver the output for the buck converter. The PHASE
advanced controllers that incorporate tri-state logic (H, L pin is internally connected to the switch node, VSWH. This pin
and tri-state) on the PWM output. For two state logic, the is to be used exclusively as the return pin for the BOOT
PWM input operates as follows. When PWM is driven above capacitor.
VPWM_TH_R the low-side is turned off and the high-side is
Ground Connections (CGND and PGND)
turned on. When PWM input is driven below VPWM_TH_F the
high-side is turned off and the low-side is turned on. For PGND (power ground) should be externally connected to
tri-state logic, the PWM input operates as previously stated CGND (control signal ground). The layout of the printed circuit
for driving the MOSFETs when PWM is logic high and logic board should be such that the inductance separating CGND
low. However, there is a third state that is entered as the and PGND is minimized. Transient differences due to
PWM output of tri-state compatible controller enters its high inductance effects between these two pins should not
impedance state during shut-down. The high impedance exceed 0.5 V.
state of the controller’s PWM output allows the SiC533 to Control and Drive Supply Voltage Input (VDRV, VCIN)
pull the PWM input into the tri-state region (see definition of
VCIN is the bias supply for the gate drive control IC. VDRV is
PWM logic and tri-state, Fig. 4). If the PWM input stays in
the bias supply for the gate drivers. It is recommended to
this region for the tri-state hold-off period, tTSHO, both
separate these pins through a resistor. This creates a low
high-side and low-side MOSFETs are turned off. The
pass filtering effect to avoid coupling of high frequency gate
function allows the VR phase to be disabled without
drive noise into the IC.
negative output voltage swing caused by inductor ringing
and saves a Schottky diode clamp. The PWM and tri-state Bootstrap Circuit (BOOT)
regions are separated by hysteresis to prevent false The internal bootstrap diode and an external bootstrap
triggering. The SiC533 incorporates PWM voltage capacitor form a charge pump that supplies voltage to the
thresholds that are compatible with 5 V logic. BOOT pin. An integrated bootstrap diode is incorporated so
Diode Emulation Mode and PS4 Mode (ZCD_EN#) that only an external capacitor is necessary to complete the
bootstrap circuit. Connect a boot strap capacitor with one
The ZCD_EN# pin enables or disables diode emulation
leg tied to BOOT pin and the other tied to PHASE pin.
mode. When ZCD_EN# is driven below VTH_ZCD_EN#_F, diode
emulation is allowed. When ZCD_EN# is driven above Shoot-Through Protection and Adaptive Dead Time
VTH_ZCD_EN#_R, continuous conduction mode is forced. The SiC533 has an internal adaptive logic to avoid shoot
Diode emulation mode allows for higher converter efficiency through and optimize dead time. The shoot through
under light load situations. With diode emulation active, the protection ensures that both high-side and low-side
SiC533 will detect the zero current crossing of the output MOSFETs are not turned on at the same time. The adaptive
inductor and turn off the low-side MOSFET. This ensures dead time control operates as follows. The high-side and
that discontinuous conduction mode (DCM) is achieved. low-side gate voltages are monitored to prevent the
Diode emulation is asynchronous to the PWM signal, MOSFET turning on from tuning on until the other
therefore, the SiC533 will respond to the ZCD_EN# input MOSFET’s gate voltage is sufficiently low (< 1 V). Built in
immediately after it changes state. delays also ensure that one power MOSFET is completely
The ZCD_EN# pin can be floated resulting in a high off, before the other can be turned on. This feature helps to
impedance state. High impedance on the input of ZCD_EN# adjust dead time as gate transitions change with respect to
combined with a tri-stated PWM output will shut down the output current and temperature.
SiC533, reducing current consumption to typically 5 μA. Under Voltage Lockout (UVLO)
This is an important feature in achieving the low standby
current requirements required in the PS4 state in ultrabooks During the start up cycle, the UVLO disables the gate
and notebooks. drive, holding high-side and low-side MOSFET gates low,
until the supply voltage rail has reached a point at which
Voltage Input (VIN) the logic circuitry can be safely activated. The SiC533 also
This is the power input to the drain of the high-side power incorporates logic to clamp the gate drive signals to zero
MOSFET. This pin is connected to the high power when the UVLO falling edge triggers the shutdown of the
intermediate BUS rail. device.





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FUNCTIONAL BLOCK DIAGRAM

BOOT V IN

VDRV

VCIN UVLO

ZCD_EN#
VCIN
-
+ PHASE
PWM logic Anti-cross
control & conduction GL
PWM state control VSWH
machine logic -
+
VDRV

CGND

GL PGND

Fig. 3 - SiC533 Functional Block Diagram

DEVICE TRUTH TABLE

ZCD_EN# PWM GH GL
Hi-Z (PS4 mode) X L L
H, IL > 0 A
L L L
L, IL < 0 A
L H H L
L Hi-Z L L
H L L H
H H H L
H Hi-Z L L

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PWM TIMING DIAGRAM

VTH_PWM_R
VTH_TRI_F
VTH_TRI_R
VTH_PWM_F
PWM
tPD_OFF_GL
tTSHO

GL
tPD_ON_GL
tPD_TRI_R

tTSHO
tPD_ON_GH tPD_OFF_GH

tPD_TRI_R

GH

Fig. 4 - Definition of PWM Logic and Tri-State


ZCD_EN# - PS4 EXIT TIMING

5V

PWM
tPS4EXIT

VSWH

5V

ZCD_EN#
2.5 V

Fig. 5 - ZCD_EN# - PS4 Exit Timing

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ELECTRICAL CHARACTERISTICS
Test condition: VIN = 12 V, VDRV = VCIN = 5 V, ZCD_EN# = 5 V, VOUT = 1 V, LOUT = 250 nH, (DCR = 0.32 m), TA = 25 °C
(All power loss and normalized power loss curves show SiC533 losses only unless otherwise stated)

94 40

90 35

86 30
500 kHz

Output Current, IOUT (A)

82 25
Efficiency (%)

750 kHz 1 MHz

1 MHz 1 MHz
78 20

74 500 kHz
15

70 10
Complete converter efficiency
66 PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)] 5
POUT = VOUT x IOUT, measured at output capacitor
62 0
0 5 10 15 20 25 30 35 0 15 30 45 60 75 90 105 120 135 150
Output Current, IOUT (A) PCB Temperature, TPCB (°C)

Fig. 6 - Efficiency vs. Output Current (VIN = 12 V) Fig. 9 - Safe Operating Area (VIN = 12 V)

5.0 16.0

4.5 IOUT = 25 A 14.0

Power Loss, PL (W)
Power Loss, PL (W)

4.0 12.0

3.5 10.0

3.0 8.0 1 MHz

2.5 6.0
750 kHz
2.0 4.0

1.5 2.0
500 kHz
1.0 0.0
200 300 400 500 600 700 800 900 1000 1100 0 5 10 15 20 25 30 35

Switching Frequency, fs (KHz) Output Current, IOUT (A)

Fig. 7 - Power Loss vs. Switching Frequency (VIN = 12 V) Fig. 10 - Power Loss vs. Output Current (VIN = 12 V)

94 94
500 kHz
90 90

86 86
500 kHz
82 82
Efficiency (%)
Efficiency (%)

750 kHz 1 MHz

750 kHz
1 MHz
78 78

74 74

70 70
Complete converter efficiency Complete converter efficiency
66 PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)] 66 PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)]
POUT = VOUT x IOUT, measured at output capacitor POUT = VOUT x IOUT, measured at output capacitor
62 62
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
Output Current, IOUT (A) Output Current, IOUT (A)

Fig. 8 - Efficiency vs. Output Current (VIN = 9 V) Fig. 11 - Efficiency vs. Output Current (VIN = 19 V)

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ELECTRICAL CHARACTERISTICS
Test condition: VIN = 12 V, VDRV = VCIN = 5 V, ZCD_EN# = 5 V, VOUT = 1 V, LOUT = 250 nH, (DCR = 0.32 m), TA = 25 °C
(All power loss and normalized power loss curves show SiC533 losses only unless otherwise stated)

4.2 1.8

4.0 1.6

Normalized PS4 Exit Latency, tPS4EXIT

Control Logic Supply Voltage, VCIN (V)

3.8 1.4

3.6 1.2
VUVLO_RISING
3.4 1.0

3.2 0.8
VUVLO_FALLING
3.0 0.6

2.8 0.4

2.6 0.2
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)
Fig. 12 - UVLO Threshold vs. Temperature Fig. 15 - PS4 Exit Latency vs. Temperature

0.80 11

0.75 10
BOOT Diode Forward Voltage, VF (V)

Driver Supply Current, IVDRV (mA)

IF = 2 mA fPWM = 300 kHz

0.70 9

0.65 8

0.60 7

0.55 6

0.50 5

0.45 4

0.40 3
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)
Fig. 13 - BOOT Diode Forward Voltage vs. Temperature Fig. 16 - Driver Supply Current vs. Temperature

4.8 4.8
ZCD_EN# Threshold Voltage, VZCD_EN# (V)

4.2 VTH_PWM_R 4.2

PWM Threshold Voltage, VPWM (V)

VTH_ZCD_EN#_R
3.6 3.6
VTRI_TH_F
3.0 3.0
VTRI_ZCD_EN#_F
2.4 2.4
VTRI VTRI_ZCD_EN#_R
1.8 1.8
VTRI_TH_R
1.2 1.2
VTH_ZCD_EN#_F
VTH_PWM_F
0.6 0.6

0.0 0.0
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)
Fig. 14 - PWM Threshold vs. Temperature Fig. 17 - ZCD_EN# Threshold vs. Temperature

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PCB LAYOUT RECOMMENDATIONS
Step 1: VIN / PGND Planes and Decoupling Step 3: VCIN / VDRV Input Filter

Cvdrv
VIN Plane

VIN PGND

Cvcin
VSWH AGND

PGND

PGND Plane

1. Layout VIN and PGND planes as shown above. 1. The VCIN / VDRV input filter ceramic cap should be placed
2. Ceramic capacitors should be placed directly between as close as possible to the IC. It is recommended to
VIN and PGND, and close to the device for best connect two capacitors separately.
decoupling effect. 2. VCIN capacitor should be placed between pin 2 (VCIN)
3. Different values / packages of ceramic capacitors should and pin 3 (AGND of driver IC) to achieve best noise
be used to cover entire decoupling spectrum e.g. 1210, filtering.
0805, 0603, 0402. 3. VDRV capacitor should be placed between pin 20
4. Smaller capacitance values, placed closer to the (PGND of driver IC) and pin 21 (VDRV) to provide maximum
device’s VIN pin(s), results in better high frequency noise instantaneous driver current for low side MOSFET during
absorbing. switching cycle.
4. For connecting VCIN to AGND, it is recommended to use
Step 2: VSWH Plane a large plane to reduce parasitic inductance.

Step 4: BOOT Resistor and Capacitor Placement

VSWH

Cboot
Snubber

PGND Plane
Rboot
1. Connect output inductor to IC with large plane to lower
resistance.
1. The components need to be placed as close as possible
2. VSWH plane also serves as a heat-sink for low-side to IC, directly between PHASE (pin 5) and BOOT (pin 4).
MOSFET. Make the plane wide and short to achieve the
2. To reduce parasitic inductance, chip size 0402 can be
best thermal path.
used.
3. If a snubber network is required, place the components
as shown above, the network can be placed at bottom.

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Step 5: Signal Routing Step 7: Ground Connection

AGND

AGND AGND
VSWH

PGND
PGND

1. Route the PWM and ZCD_EN# signal traces out of the 1. It is recommended to make a single connection between
top left corner next to pin 1. AGND and PGND which can be made on the top layer.
2. The PWM signal is an important signal, both signal and 2. It is recommended to make the entire first inner layer
return traces should not cross any power nodes on any (below top layer) the ground plane and separate them
layer. into AGND and PGND planes.
3. It is best to “shield” these traces from power switching 3. These ground planes provide shielding between noise
nodes, e.g. VSWH, with a GND island to improve signal sources on top layer and signal traces on bottom layer.
integrity. 
4. GL (pin 19) has been connected with GL pad (pin 24) 
internally. 
 
Step 6: Adding Thermal Relief Vias 





VSWH 

AGND 
PGND


VIN 


PGND Plane 

VIN Plane 

1. Thermal relief vias can be added on the VIN and AGND 
pads to utilize inner layers for high-current and thermal 
dissipation. 
2. To achieve better thermal performance, additional vias 
can be placed on VIN plane and PGND plane. 
3. VSWH pad is a noise source, it is not recommended to 
place vias on this pad. 
4. 8 mil vias for pads and 10 mils vias for planes are the
optimal via sizes. Vias on pad may drain solder during
assembly and cause assembly issues. Consult with the
assembly house for guidelines.

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 SiC533
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Vishay Siliconix

PRODUCT SUMMARY
Part number SiC533
Description 35 A power stage, 4.5 VIN to 24 VIN, 5 V PWM with ZCD, PS4 mode
Input voltage min. (V) 4.5
Input voltage max. (V) 24
Continuous current rating max. (A) 35
Switch frequency max. (kHz) 2000
Enable (yes / no) No
Monitoring features -
Protection UVLO, THDN
Light load mode ZCD, PS4
Pulse-width modulation (V) 5
Package type PowerPAK MLP4535-22L
Package size (W, L, H) (mm) 4.5 x 3.5 x 0.75
Status code 2
Product type VRPower (DrMOS)
Applications Computer, industrial, networking

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?75010.

S20-0485-Rev. C, 29-Jun-2020 12 Document Number: 75010

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 Package Information
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Vishay Siliconix
MLP 4.5 x 3.5-22L BWL Case Outline
2x A 0.08 C K1 D2-1
0.1 C A K4
D A1 D1-2
A D2-4
D1-1
5 6 A2
22 21 20 19 18 17 17 18 19 20 21 22
Pin 1 dot
by marking
2x
0.1 C B 1 16 16 1

E1-5

E2-2
2 15 15 K3 2

E2-4
E2-1
3 14 14 3

E1-3

E1-2
e
K2

E1-4
4 13 13 4

E2-3
5 5

E1-1
12 12

b
B

6 7 8 9 10 11 11 10 9 8 7 6
C L
D2-3 D2-2

MILLIMETERS INCHES
DIM.
MIN. NOM. MAX. MIN. NOM. MAX.
A (8) 0.70 0.75 0.80 0.027 0.0029 0.031
A1 0.00 - 0.05 0.000 - 0.002
A2 0.20 ref. 0.008 ref.
b (4) 0.20 0.25 0.30 0.0078 0.0098 0.0110
D 4.50 BSC 0.177 BSC
e 0.50 BSC 0.019 BSC
E 3.50 BSC 0.137 BSC
L 0.35 0.40 0.45 0.013 0.015 0.017
N (3) 22 22
Nd (3) 6 6
Ne (3) 5 5
D1-1 0.35 0.40 0.45 0.013 0.015 0.017
D1-2 0.15 0.20 0.25 0.005 0.007 0.009
D2-1 1.02 1.07 1.12 0.040 0.042 0.044
D2-2 1.02 1.07 1.12 0.040 0.042 0.044
D2-3 1.47 1.52 1.57 0.057 0.059 0.061
D2-4 0.25 0.30 0.35 0.009 0.011 0.013
E1-1 1.095 1.145 1.195 0.043 0.045 0.047
E1-2 2.67 2.72 2.77 0.105 0.107 0.109
E1-3 0.35 0.40 0.45 0.013 0.015 0.017
E1-4 1.85 1.90 1.95 0.072 0.074 0.076
E1-5 0.095 0.145 0.195 0.0037 0.0057 0.0076
E2-1 3.05 3.10 3.15 0.120 0.122 0.124
E2-2 1.065 1.115 1.165 0.0419 0.0438 0.0458
E2-3 0.695 0.745 0.795 0.027 0.029 0.031
E2-4 0.40 0.45 0.50 0.015 0.017 0.019
K1 0.40 BSC 0.015 BSC
K2 0.07 BSC 0.002 BSC
K3 0.05 BSC 0.001 BSC
K4 0.40 BSC 0.015 BSC

Revision: 20-Oct-14 1 Document Number: 67234

For technical questions, contact: [email protected]
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 Package Information
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Vishay Siliconix
Notes
1. Use millimeters as the primary measurement
2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994
3. N is the number of terminals,
Nd is the number of terminals in X-direction and
Ne is the number of terminals in Y-direction.
4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip
5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body
6. Exact shape and size of this feature is optional
7. Package warpage max. 0.08 mm
8. Applied only for terminals

T14-0626-Rev. A, 20-Oct-14
DWG: 6028

Revision: 20-Oct-14 2 Document Number: 67234

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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 PAD Pattern
www.vishay.com
Vishay Siliconix
Recommended Land Pattern PowerPAK® MLP4535-22L

Package outline top view, transparent Land pattern

(not bottom view)

4.5
(D2-4) (K4) (D1-2)
0.3 0.4 0.2 4.5
(D2-1) (K1) (D1-1) 0.75 0.5 x 3 = 1.5 1 0.75
1.07 0.4 0.3 0.5 0.3
0.4

0.3
0.45 22 21 20 19 18 17 0.45
22 21 20 19 18 17

0.74

0.55 0.5
0.75

0.75
0.31

0.3
(E2-4)
1 0.45 16 1 16
0.14
(D1-5)
0.14

(K3)
(E2-2)

0.8 0.3

0.29
2 0.36 0.4 0.3
1.11

15 2 15

0.5 x 4 = 2

0.5 x 4 = 2
1.2
0.05
0.29

(E2-1)
(E1-3)

3.5

3.5
3

3.1
14 1.16 0.25
0.4

14

0.29
3

3.05
1.61
(E1-2)

0.21
2.72

0.25

0.37
(K2)

(b)
4
(E1-4)

0.07 4 13

2.05
13
1.9
0.5
(E2-3)
(e)
0.75

0.9
(E1-1)

12 5 12
1.15

0.75

0.75
0.59
0.37
6 7 8 9 10 11

0.1
0.3
6 7 8 9 10 11

0.3
(L) (D2-2) (D2-3)
1.07 1.52 0.75 0.5 x 2 0.5 x 2 0.75
0.4 1

3
0.
=1 =1

22 21 20 19 18 17

1 16

2 15 All dimensions in millimeters

3 14

4 13

5 12

6 7 8 9 10 11

Revision: 05-Nov-14 1 Document Number: 66914

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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 Legal Disclaimer Notice
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Vishay
Disclaimer

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Revision: 01-Jan-2024 1 Document Number: 91000

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