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Multiplexer in HDL

This document discusses multiplexers in HDL and their gate level modeling. It begins with defining a multiplexer as a circuit with multiple inputs and a single output, where control lines determine which input is passed to the output. It then explains that HDLs like Verilog allow designing of digital circuits through textual descriptions. The document shows an example Verilog code modeling a 4-input multiplexer and its gate-level equivalent using AND and OR gates, where the selection lines choose one input to pass to the output. It concludes by listing references on Verilog, multiplexers, and their implementation.

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andrievillamor09
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113 views

Multiplexer in HDL

This document discusses multiplexers in HDL and their gate level modeling. It begins with defining a multiplexer as a circuit with multiple inputs and a single output, where control lines determine which input is passed to the output. It then explains that HDLs like Verilog allow designing of digital circuits through textual descriptions. The document shows an example Verilog code modeling a 4-input multiplexer and its gate-level equivalent using AND and OR gates, where the selection lines choose one input to pass to the output. It concludes by listing references on Verilog, multiplexers, and their implementation.

Uploaded by

andrievillamor09
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
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INTRODUCTION IN HDL

Multiplexer in HDL
and its Gate Level Modelling.

Presented by: Andrie John G. Rosales


What is a Multiplexer?
A multiplexer (shortened to “MUX”) is also referred to as
many to one circuit. It is a circuit that has multiple inputs
(sources) and a single output (destination).

A multiplexer has several input lines, typically labeled as D0,


D1, D2, ..., Dn-1, where n is the number of inputs. It also has
control lines, often labeled as "select lines" or "control
inputs", which determine which input signal is passed through
to the output.
What is HDL?
Hardware Description Languages (HDLs) work by allowing
designers to specify the behavior and structure of digital
circuits using a textual description.

.HDLs provide a structured and systematic approach to


designing digital circuits, allowing designers to efficiently
specify, simulate, and implement complex digital systems.
They play a crucial role in the development of modern
electronics, enabling the design of everything from
microprocessors and memory chips to specialized
application-specific circuits.
Verilog
Verilog is a hardware description language (HDL) used to
model electronic systems. It is widely used in digital design
and is particularly popular for describing complex digital
systems, such as integrated circuits (ICs), field-
programmable gate arrays (FPGAs), and application-
specific integrated circuits (ASICs).

Verilog allows designers to specify the behavior and


structure of digital circuits using a syntax similar to
programming languages like C and C++. It supports various
levels of abstraction, from high-level behavioral
descriptions down to detailed gate-level representations.
Performing Multiplexer in HDL
WITH THE USE OF VERILOG
Performing Multiplexer in HDL
WITH THE USE OF VERILOG

In the sample code shown, using a Verilog as the HDL to model


an example of a Multiplexer where there are multiple inputs
and a single output. The code shows that there are input lines
and select lines where input lines are the input itself and select
lines that determine the input that should be connected to the
output.

The main process is in the case statement where the value of


bits decides what will be the output. That is why it behaves like
a Multiplexer.
Gate Level Modeling
MULTIPLEXER BASED ON THE LOGIC GATES

Using a series of AND gates and an OR gate, the


behavior of a Multiplexer is copied. The in0, in1,in2,
in3, are the inputs and one of them are chosen depends
on the input of s0 and s1 which is the selection inputs
that determines which among the inputs is chosen to
be the output, in this level, you cant be certain what
input is chosen because it is only producing 1s and 0s
as output but you can identify it by looking at the AND
Gates. If one of the AND Gates produces 1 or high
output that means it is the chosen input to be the
output because among the said gates, only 1 is
expected to produce high output.
References
Admin. (2023). Verilog. Retrieved March 6, 2024, from ChipVerify website:
https://www.chipverify.com/tutorials/verilog
‌
Storr, W. (2013, August). Multiplexer (MUX) and Multiplexing Tutorial. Retrieved March 6,
2024, from Basic Electronics Tutorials website: https://www.electronics-
tutorials.ws/combination/comb_2.html
‌
GfG. (2017, March 21). Multiplexers in Digital Logic. Retrieved March 6, 2024, from
GeeksforGeeks website: https://www.geeksforgeeks.org/multiplexers-in-digital-logic/
‌
WIT. (2020). Implementation of 4:1 Multiplexer Circuit using Verilog HDL [YouTube
Video]. Retrieved from https://www.youtube.com/watch?v=R_DPCKsgRLg
‌
END
Thank you!!

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