Computer Organization and Architecture

Objective:
After completing this chapter, you will be able to understand:
 Instruction codes
 Computer registers and their application
 Computer instructions
 Timing and control
 The instruction cycle
 Memory-reference instructions
 Input and output interrupt
 Design of basic computer

The internal organization of a digital system is defined by the sequence of micro-operations it performs
on data stored in its registers. The general purpose digital computer is capable of executing various
micro-operations and, in addition, can be instructed as to what specific sequence of operations it must
perform. The user of the computer can control the process by means of a program. A program is a set of
instructions that specify the operations, operands, and the sequence by which processing has to occur.

Depending on the complexity and the functions that the computer performs, a computer may be
classified as:

 A Special Purpose Computer is constructed to perform one or very few functions.

 A General Purpose Computer is constructed to perform many different functions.
 A program is a set of instructions that specify the operations, operands, and the sequence by
which processing has to occur.
 A computer instruction is a binary code that specifies a sequence of micro-operations for the

computer.

Instruction codes together with the data are stored in memory. The computer reads each instruction from
memory and places it in a control register. The control then interprets the binary code of the instruction
and proceeds to execute it by issuing a sequence of micro-operations.

An Instruction Code is a group of bits that instructs the computer to perform a specific operation. It is
usually divided into parts, each having its own particular interpretation. The most basic part of an
instruction code is its operation part.

The operation code of an instruction is a group of bits that defines such operations as Add, Subtract,
Multiply, Shift and Complement.

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The operation part of an instruction code specifies the operation to be performed. This operation must be
performed on some data stored in processor registers or in memory.An instruction must specify not
only the operation but also the registers or the memory words where the operands are to be found.

Note: The number of bits required for the operation code of an instruction depends on the total number
of operations available in the computer.

The simplest way to organize a computer is to have one processor register and an instruction code
format with two parts. The first specifies the operation to be performed and the second specifies an
address. The memory address tells the control where to find an operand in memory. This operand is read
from memory and used as the data to be operated on together with the data stored in processor register.
Instructions are stored in one section of memory and data in another. The operation is performed with
memory operands and the content of AC. Figure 4-1 below depicts this type of organization.

Figure 4-1: Stored program organization

Note: Computers that have a single processor register usually assign to the term Accumulator (AC).

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Example: For a memory unit with 4096 words we need 12 bits to specify an address (Since 2 12 = 4096).
If we store each instruction in one 16 bit memory word, we have available 4-bits for the operation code
OP-Code. To specify one out of 16 possible operations and 12 bits specify the address of an operand.
The control reads a 16-bit instruction from the program portion of memory. It uses the 12-bit address
part of the instruction to read 16-bit operand from the data portion of memory. It then executes the
operation specified by the operation code.

It is sometimes convenient to use the address bits of an instruction code not as an address but as an
actual operand. When the second part of an instruction code specifies an operand, the instruction is said
to have an immediate operand. When the second part specifies the address of an operand, the instruction
is said to have direct address. This is in contrast to a third possibility called indirect address, where
the bits in the second part of the instruction designate an address of memory word in which the address
of the operand is found.

Figure 4-2 illustrates the direct and indirect addressing modes. Note that one bit of the instruction code
is used to distinguish between a direct and an indirect address.

Figure 4-2: Direct and indirect addressing modes

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Computer instructions are usually stored in consecutive memory locations and executed sequentially one
at a time. The control reads an instruction from specific address in memory and executes it. It then
continues by reading the next instruction in sequence and executes it and so on. This type of instruction
sequencing needs a counter to calculate the address of the next instruction after execution of the current
instruction is completed. It is also necessary to provide a register in a control unit for storing the
instruction code after it is read from the memory. The computer needs processor registers for
manipulating data and a register for holding a memory address. These requirements dictate the register
configuration shown in Figure 4-3. The registers are also listed in Table 4-1.

The memory word has a capacity of 4096 words and each word contains 16 bits. 12 bits of an instruction
word are needed to specify the address of the operand. This leaves three bits for the operation part of the
instruction and a bit to specify a direct or indirect address. The data register (DR) holds the operand read
from memory. The accumulator (AC) register is a general purpose processing register. The instructions
read from memory are placed in instruction register (IR). The temporary register (TR) is used for
holding temporary data during the processing.

Table 4-1: List of registers for the basic computer

Register Number of Register Name Function
Symbol Bits
DR 16 Data register Holds memory operand
AR 12 Address Register Holds address of memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds Output character

The memory address register (AR) has 12 bits since this is the width of a memory address. The program
counter (PC) also has 12 bits and it holds the address of the next instruction to read from memory after
the current instruction is executed. The PC goes through a counting sequence and causes the computer to
read sequential instructions previously stored in memory. Instruction words are read and executed in
sequence unless a branch instruction is encountered. A branch instruction calls for a transfer to a
nonconsecutive instruction in the program. The address part of a branch instruction is transferred to PC
to become the address of the next instruction. To read an instruction, the content of PC is taken as the
address for memory and memory read cycle is initiated. PC is then incremented by one, so it holds the
address of the next instruction in sequence.

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Figure 4-3: Basic Computer Registers and Memory

Common Bus Systems

The basic computer has eight registers, a memory unit, and a control unit. Paths must be provided to
transfer information from one register to another and between memory and registers. Path between each
and every register would cause too many wires running around the registers. A better solution is the use
a common bus. A bus is a set of common lines, one for each bit

Control signals determine which register is connected to the bus at a given time. The connection of the
registers and memory of the basic computer to a common bus system is illustrated in Figure 4-4.

In Figure 4-4, the output of seven registers and memory are connected to a common bus. The specific
output that is selected for the bus lines at any given time is determined from the binary value of the
selection variables S2, S1, and S0. The number along each output shows the decimal equivalent of the
required binary selection. For example, the number along the output DR is 3. The 16-bit output of DR
are placed on the bus line when S2S1S0=011 since this is the binary value of decimal number 3. The lines
from the common bus are connected to the inputs of each register and the data inputs of the memory.
The particular register whose LD (load) in put is enabled receives the data from the bus during the next
clock pulse transition. The memory receives the content of the bus when its write input is activated. The
memory places its 16-bit output onto the bus when the read input is activated and S 2S1S0=111.
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 Computer Organization and Architecture

1 Bus
0

Memory unit
7
4096×16 Address

Write Read
AR
1

LD CLR

LD CLR

LD INR CLR

Adder E
and AC 4
logic
CLR

6
CLR

Clock

16-bit common bus

Figure 4-4: Basic computers connected to a common bus

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 Computer Organization and Architecture

The basic computer has three instruction code formats, as shown in Figure 4-5 below. Each format has
16 bits. The operation code (opcode) part of the instruction contains three bits and the meaning of the
remaining depends on the operation code encountered. A memory-reference instruction uses 12 bits to
specify an address and one bit to specify the addressing mode I (I = 0 for direct address and I = 1 for
Indirect address).The register-reference instructions are recognized by the operation code 111 with a 0 in
the left most bit (bit 15) of the instruction. A register-reference instruction specifies an operation on or a
test of the AC register. Input-output instructions do not need to refer to the memory and are recognized
by operation code 111 with a 1 in the leftmost bit of the instruction. The remaining 12 bits are used to
specify the type of input-output operations or test performed.

Figure 4-5: Instruction format

The instructions for the basic computer are listed in Table 4-2. The symbol designation is a three-letter
word and represents an abbreviation intended for programmers.

Instruction Set Completeness

Before investigating the operations performed by the instructions let us discuss the types of instructions
that must be included in a computer. A computer should have a set of instructions so that the user can
construct machine language program to evaluate any function that is known to be computable. The set of
instructions are said to be complete if the computer includes a sufficient number of instructions in each
of the following categories:

1. Arithmetic, Logical and Shift Instructions.

2. Arithmetic, Logic and Shift instructions provide computational capability of processing data.
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 Computer Organization and Architecture

3. Instruction for moving information to and from memory and processor registers. Program control
instructions together with instructions that check status conditions.

4. Input and Output Instructions

Table 4-2: Basic computer instructions

Hexadecimal Code
Symbol I =0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load memory word to AC
STA 3xxx Bxxx Store content of AC in memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero
CLA 7800 Clear AC
CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instruction if AC positive
SNA 7008 Skip next instruction if AC negative
SZA 7004 Skip next instruction if AC zero
SZE 7002 Skip next instruction if E is 0
HLT 7001 Halt computer
INP F800 Input character to AC
OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off

Arithmetic, logical and shift instructions provide computational capabilities for processing the type of
data that the user may wish to employ. The bulk of the binary information in a digital computer is stored
in memory, but all computations are done in processor registers. Therefore, the user must have the
capability of moving information between these two units

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Remark: Although the set of instruction for basic computer is complete, it is not sufficient because
frequently used operations are not performed rapidly. An efficient set of instructions must include such
instructions as subtraction, OR, and XOR.

Note: These operations must be programmed in basic computer.

In order to control the steps of the instruction cycle, it is necessary to introduce a counter, whose output
is used as input to the control logic. We will utilize a Sequence Counter Register (SC). This is a register
that holds a count value, can be reset/cleared to zero and can be incremented (or decremented) by one

Each instruction will require a specified number of time steps to complete a sequence of micro-
operations. Each step of the sequence is marked by a count value in SC. The SC outputs a string of bits
whose value is in the range from 0 to 2 L-1. Eg. for L=3, from 0 to 7. We need a way of converting the
bit string value to single bit valued outputs labeled T0, T1, T2, T3, and so on, up to Tx (where x = 2 L-1).
A decoder serves our purpose, recalling that the output from the DEC is a 1 only on one line (the rest are
0`s)

The timing and control unit is the component that determines what the ALU should do at a given instant.
There are two kinds of control organization:

1. Hardwired control
2. Microprogrammed control

Hardwired control: The control logic is implemented with digital circuits (decoders, flip flops, etc.) It
has the advantage that it can be optimized to produce a fast mode of operation but requires changes in
the wiring among the various components if the design has to be modified or changed.

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 Computer Organization and Architecture

Microprogrammed control: Control information is stored in a control memory. Required

modifications can be done by updating the micro-program in control memory. Suppose we need to
implement the following:
XY: R1 ← R2
X′Y: R1 ← R1 + 1
XY′: R2 ← 0

X and Y are control variables. The load, clear and increment lines of the registers are a function of these
variables.

LD (R1) = XY (can also be further reduced),

INR(R1) = X′Y, CLR(R2) = XY′, bus-select = XY

Figure 4-6: Timing and control

Similarly, for the basic computer

a. The control inputs of the registers LD, INR, CLR must be known
b. The bus system must have control inputs to determine which component to select
c. The current instruction must be decoded to determine what is to be done.

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 Computer Organization and Architecture

A program residing in the memory unit of the computer consists of a sequence of instructions. The
program is executed by going through a cycle for each instruction; the so called fetch-decode-execute
cycle. Each instruction cycle in turn is subdivided into a sequence of phases. In the basic computer each
instruction cycle consists of the following phases:

Fetch an instruction from memory

Decode the instruction
Read the effective address from memory if the instruction has an indirect address
Execute the instruction

Upon the completion of step 4, the control goes back to step 1 to fetch, decode and execute the next
instruction. This process continues indefinitely unless a HALT instruction is encountered.

I. Fetch the instruction

Initially, the program counter PC is loaded with the address of the first instruction in the program and
SC is cleared to 0, providing a decoded timing signal T0. After each clock pulse, SC is incremented by
one, so that the timing signals go through a sequence T0, T1, T2 and so on. Since the address lines of the
memory unit are hardwired to AR, address of the instruction to be fetched must first be placed in AR.
Thus the first register transfer in an instruction cycle should be transferring the content of PC (address of
the instruction to be brought in for execution) to AR

T0: AR ← PC

Bus selects PC, LD(AR) = 1. Next the current instruction is brought from memory into IR and PC is
incremented

T1: IR ← M[AR], PC ← PC + 1. Bus selects RAM, Memory read is set, LD(IR) = 1, INR(PC) = 1

II. Decode the instruction

T2: D0, ... , D7 ← Decode IR(12-14), AR ← IR(0-11), I ← IR(15)

Therefore, micro-operations for the fetch and decode phases can be specified by the following register
transfer statements.
T0: AR ← PC
T1: IR ← M[AR], PC ← PC + 1
T2: D0, …, D7 ← Decode IR(12-14), AR ← IR(0-11), I ← IR(15)

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 Computer Organization and Architecture

In order to specify the micro-operations needed for the execution of each instruction, it is necessary that
the function they are intended to perform be defined precisely. Table 4-3 lists the seven memory-
reference instructions. The decoded output Di for i = 0, 1, 2, 3, 4, 5, and 6 from the operation.

Decoder that belongs to each instruction is included in the table. The effective address of the instruction
is in the address register AR and was placed there during timing signal T 2 when I = 0, or during timing
signal T3 when I=1. The execution of the memory-reference instruction starts with timing signal T 4. The
symbolic description of each is specified in the table in terms of register transfer notation. The actual
execution of the instruction in the bus system will require s sequence of micro-operations. This is
because data stored in memory cannot be processed directly. The data must be read from memory to a
register where they can be operated on with logic circuits.

Table 4-3: Memory-reference instructions

Symbol Operation Symbolic Description
Decoder

AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout

LDA D2 AC  M[AR]

STA D3 M[AR]  AC

BUN D4 PC  AR

BSA D5 M[AR]  PC, PC  AR + 1

ISZ D6 If (M[AR] + 1= 0) then PC  PC + 1

AND to AC: This is an instruction that performs the AND logic operation on pairs of bits in AC and the
memory word specified by the effective address. The result of the operation is transferred to AC. The
micro-operations that execute this instruction are:

D0T4: DR  M[AR]
D0T5: AC  AC  DR, SC  0

The control function for this instruction uses the operation decoder D0 since this output of the decoder is
active when the instruction has an AND operation whose binary code value is 000.
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 Computer Organization and Architecture

ADD to AC: This instruction adds the content of the memory word specified by effective address to the
value of AC. The sum is transferred into AC and the output carry Cout is transferred into E (extended
accumulator) flip-flop.

D1T4: DR  M[AR]

D1T5: AC  AC + DR, E  Cout, SC  0

LDA: Load to AC: This instruction transfers the memory word specified by effective address to AC.

D2T4: DR  M[AR]

D2T5: AC  DR, SC  0

STA: Store AC: this instruction stores the content of AC into the memory word specified by the
effective address. Since the output of AC is applied to the bus and the data input of memory is connected
to the bus, we can execute this instruction with one microoperation.

D3T4: M[AR]  AC, SC  0

BUN: Branch Unconditionally: This instruction transfers the program to the instruction specified by
the effective address. Remember that PC holds the address of the instruction to be read from memory in
the next instruction cycle. PC is incremented at T1 to prepare it for the address of the next instruction in
the program sequence. The BUN instruction allows the programmer to specify an instruction out of
sequence and we say that the program branches (jumps) unconditionally. The instruction is executed
with one microoperation:

D4T4: PC  AR, SC  0

The effective address from AR is transferred through the common bus to PC. Resetting SC to 0 transfers
control to T 0. The next instruction is then fetched and executed from the memory address given by the
new value in PC.

BSA: Branch and save Return Address: This instruction is useful for branching to a portion of the
program called subroutine or procedure. When executed, the BSA instruction stores the address of the
next instruction in sequence (which is available in PC) into a memory location specified by the
effective-address. The effective address plus one is then transferred to PC to serve as the address of the
first instruction in the subroutine.

D5T4: M[AR]  PC, AR  AR + 1

D5T5: PC  AR, SC  0
Timing signal T 4 initiates a memory write operation, places the content of PC onto the bus, and enables
the INR input of AR. The memory write operation is completed and AR is incremented by the time the
next clock transition occurs. The bus is used at T5 to transfer the content of AR to PC.

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 Computer Organization and Architecture

ISZ: Increment and Skip if Zero: This instruction increments the word specified by the effective
address, and if the incremented value is equal to 0, PC is incremented by 1. Since it is not possible to
increment a word inside the memory, it is necessary to read the word into DR, increment DR, and store
the word back into memory. This is done with the following sequence of micro-operations:

D6T4: DR  M[AR]
D6T5: DR  DR + 1

D6T6: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0

A computer instruction can serve no useful purpose unless it communicates with the external
environment. Instructions and data stored in memory must come from some input device. Computational
results must be transmitted to the user through some output device.

Input-Output Configuration
The terminal sends and receives serial information. Each quantity of information has eight bits of an
alphanumeric code. The serial information from the keyboard is shifted into the input register INPR. The
serial information for the printer is stored in the output register OUTR. These two register communicate
with a communication interface serially and with the AC in parallel. The input-output configuration is
shown in Figure 4-7.

Figure 4-7: Input-Output Configurations

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 Computer Organization and Architecture

The input register INPR consists of eight bits and holds alphanumeric input information. The 1-bit input
flag FGI is a control flip-flop. The flag bit is set to 1 when the new information is available in the input
device and is cleared to 0 when the information is accepted by the computer. The flag is needed to
synchronize the timing rate difference between the input devices and the computer. The process of
information transfer is as follows. Initially, the input flag (FGI) is cleared to 0. When a key is struck in
the keyboard, an 8-bit alphanumeric code is shifted into INPR and FGI is set to 1. As long as the flag is
set, the information in INPR cannot be changed by striking another key. The computer checks the flag
bit; if it is 1, the information from INPR is transferred in parallel into AC and FGI is cleared to 0. Once
the flag is cleared, new information can be shifted into INPR by striking another key. The output register
OUTR works similarly but the direction of information flow is reversed.

Input-output Instructions
Input and output instructions are needed for transferring information to and from AC register, for
checking the flag bits, and for controlling the interrupt facility. Input-output instructions have an
operation code 1111 and are recognized by the control when D7 = 1 and I = 1. The remaining bits of the
instruction specify the particular operation. The control functions and micro-operations for the input-
output instructions are listed in Table 4-4. These signals are executed with the clock transition associated
with timing signal T3. Each control function needs a Boolean relation D 7IT3, which we designate for
convenience by the symbol p. The control function is distinguished by one of the bits in IR(6-11). By
assigning the symbol Bi to bit i of IR, all control functions can be denoted by pB i where Bi represents
bits in IR, for i = 6 through 11.

Table 4-4: Input-output instructions

D7IT3 = p (common to all input-output instructions)

IR(i) = Bi [bit in IR(6-11) that specifies the instruction]

p SC  0 Clear sequence counter (SC)

INP pB11 AC(0-7)  INPR, FGI  0 Transfer input from INPR into the eight least

significant bits of AC and clear GFI

OUT pB10 OUTR  AC(0-7), FGO  0 Transfer the eight least significant bits of AC

to OUTR and clear FGO

SKI pB9 If (FGI = 1) then (PC  PC + 1) Check if input flag (FGI) is set. If so, skip to

the next instruction

SKO pB8 If (FGO = 1) then (PC  PC + 1) Check if output flag (FGO) is set. If so, skip

to the next instruction

ION pB7 IEN  1 Set the interrupt enable flag (IEN) on

IOF pB6 IEN  0 Set the interrupt enable flag (IEN) off
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The input-output communication described above is known as programmed control transfer. Because of
the difference in the rate of information flow between I/O devices and the computer, this type of transfer
is inefficient. An alternative to programmed control is to let the interrupt facility. In the alternative,
while the computer is running a program, it does not check the status of flags. Instead, when a flag is set,
the computer is momentarily interrupted from proceeding with the current program and is informed of
the fact that a flag has been set. The computer deviates momentarily from what it is doing to take care of
the input or output transfer. Once serving the interrupt, the computer returns to the task it was doing
before the interrupt arrives.

When the interrupt enable flip-flop IEN is cleared to 0 by the IOF instruction, the flags cannot interrupt
the computer. When IEN is set to 1 by the ION instruction, the computer can be interrupted. The
interrupt operation is done through the branch and save return address operation. The return address
available in PC is stored in a specific location where it can be found later when the program returns to
the instruction at which it was interrupted. This location can be a processor register, a memory stack, or
a specific memory address.

The interrupt cycle is initiated if the interrupt flip-flop R is equal to 1 after the last execute phase. This
flip-flop is set to 1 if IEN = 1 and either FGI or FGO are equal to 1. This can happen with any clock
transition except when timing signals T 0, T1, or T2 are active. The condition for setting flip-flop R to 1
can be expressed with the following register transfer statement:

T′0T′1T′4 (IEN)(FGI + FGO): R  1

The basic computer consists of the following hardware components;

 A memory unit with 4096 words of 16-bits each
 Nine registers: AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
 Seven flip-flops: I, S, E, R, IEN, FGI, and FGO
 Two decoders: a 3x8 operation decoder and a 4x 16 timing decoder
 A 16-bit common bus
 Control logic gates
 Adder and logic circuit connected to the input of AC.

The memory unit is the standard component that can be obtained readily from a commercial source. The
registers are of the types shown in the previous lesson.

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A computer uses a memory unit with 256k words of 32-bit each. A binary instruction code is stored in
one word of memory. The instruction has four parts: an indirect bit, and operation code, a register code
part to specify one of 64-registers and an address part.
A. How many bits are there in the operation code, the register code part, and the address part?
B. Draw the instruction word format and indicate the number of bits in each part.
C. How many bits are there in the data and address inputs of the memory?

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Objective:
After completing this chapter, you will be able to understand:
 General register organization
 Stack organization
 Instruction format
 Addressing modes
 Data transfer and manipulations
 Program control
 Reduced instruction set computers

The part of the computer that performs the bulk of data processing operations is called the Central
processing unit and is referred to as the CPU. The CPU is made up of three major parts, as shown in
Figure 5-1. The register set stores intermediate data used during the execution of the instructions. The
Arithmetic and Logic unit (ALU) performs the required micro-operations for executing the instructions.
The control unit supervises the transfer of information among the registers and instructs the arithmetic
and logic units as to which operation to perform.

The CPU performs a variety of functions dictated by the type of instructions that are incorporated in the
computer. Computer architecture is some times defined as the computer structure and behavior as seen
by the programmer that uses machine language instructions. This includes the instruction formats,
addressing modes, the instruction sets and the general organizations of the CPU registers.

One boundary where the computer designer and the computer programmer see the same machine is the
part of the CPU associated with the set of the instruction. From the designers‟ point of view, the
computer instruction set provides the specifications for the design of the CPU.

Figure 5-1: Major components of CPU

The design of a CPU is a task that in large part involves choosing the hard ware for implementing the
machine instructions .The user who programs the computer in machine or assembly language must be

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