Interrupt Processing
Interrupt Processing
Today, almost all computing systems are interrupt-driven. What this means is
that they follow the list of computer instructions in a program and run the
instructions until they get to the end or until they sense an interrupt signal. If the
latter event happens, the computer either resumes running the current program
or begins running another program. In either case, it must stop operations while
deciding on the next action. To do this and to work on other programs, the OS
uses pauses in operations.
When the device processor handles interrupts, it informs the device sending the
signal that the interrupt request (IRQ) has been recognized. Then the device
stops sending the IRQ signal.
When an interrupt occurs, the associated service may not start immediately. The
time interval between the time the interrupt occurs and the time when ISR
execution starts is called interrupt latency.
Types of interrupts
Interrupts are classified into two types:
I. Hardware interrupt
A hardware interrupt is an electronic signal from an external hardware device that
indicates it needs attention from the OS. One example of this is moving a mouse or
pressing a keyboard key. In these examples of interrupts, the processor must stop to read
the mouse position or keystroke at that instant.
In this type of interrupt, all devices are connected to the Interrupt Request Line (IRL).
Typically, a hardware IRQ has a value that associates it with a particular device. This
makes it possible for the processor to determine which device is requesting service by
raising the IRQ, and then provide service accordingly.
Maskable interrupts
Non-maskable interrupts
In some cases, the interrupt mask cannot be disabled so it does not affect some interrupt
signals. These are non-maskable interrupts and are usually high-priority events that
cannot be ignored.
Spurious interrupts
It has lowest priority than software It has highest priority among all
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interrupts interrupts.
However, because the microcontroller uses all its processing time for polling, it cannot
carry out simultaneous operation. Also, a lot of time is wasted by interrogating the IRQ
bit of all devices. Interrupts provide a solution to this problem. With interrupts,
the controller does not need to regularly monitor the status of devices. Instead, it responds
only when an interrupt occurs. So, when there is an interrupt, the controller is notified
that it needs service.
What is an ISR?
An ISR is present for every interrupt. The address of each ISR is stored in a fixed
location in memory. An ISR can call for asynchronous interrupts and handle both
maskable and non-maskable interrupts.
When an interrupt occurs, the microcontroller runs the ISR. At the start of execution, the
ISR disables the interrupt services of all other devices, stopping the instruction that's
currently processing and saving its configuration in a register. Then it will load the
interrupt's program counter from a location given by the interrupt vector table. Once ISR
execution is complete, it will reinitialize all interrupt services.
First-level interrupt handler (FLIH). A hard or fast interrupt handler that handles
maskable interrupts and has jitter during process execution
Second-level interrupt handler (SLIH). A slow and soft interrupt handler with less
jitter than FLIH
Interrupt vector
Interrupt processing
Step 1 − First device issues interrupt to CPU.
Step 2 − Then, the CPU finishes execution of current instruction.
Step 3 − CPU tests for pending interrupt request. If there is one, it sends an
acknowledgment to the device which removes its interrupt signal.
Step 4 − CPU saves program status word onto control stack.
Step 5 − CPU loads the location of the interrupt handler into the PC register.
Step 6 − Save the contents of all registers from the control stack into memory.
Step 7 − Find out the cause of interrupt, or interrupt type or invokes
appropriate routine.
Step 8 − Restore saved registers from the stack.
Step 9 − Restore PC to dispatch the original process.