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Week 1 DS

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15 views

Week 1 DS

Uploaded by

singhlucky7104
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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% Lokendra Singh Shekhawat 22104006

a=[0;0;1;1];
b=[0;1;0;1];
a1=[0;1];
aANDb=a&b;
%and gate
disp("TRUTH TABLE FOR AND GATE");
disp(".........................");
disp(" a b a.b");
disp(".........................");
disp([a b aANDb]);
% OR GATE
aORb=a|b;
disp("TRUTH TABLE FOR OR GATE");
disp(".........................");
disp(" a b a|b");
disp(".........................");
disp([a b aORb]);
% Not gate
aNOT=~a1;
disp("TRUTH TABLE FOR NOT GATE");
disp(".........................");
disp(" a ~a");
disp(".........................");
disp([a1 aNOT]);
%XOR gate
nota=~a;
notb=~b;
y1=a&notb;
y2=nota&b;
y3=y1|y2;
disp("TRUTH TABLE FOR XOR GATE");
disp(".........................");
disp(" a b aXORb");
disp(".........................");
disp([a b y3]);

%XNOR gate
y4=~y3;
disp("TRUTH TABLE FOR XOR GATE");
disp(".........................");
disp(" a b aXNORb");
disp(".........................");
disp([a b y4]);
% NAND GATE
aNANDb=nand(a,b);
disp("TRUTH TABLE FOR NAND GATE");
disp(".........................");
disp(" a b aNANDb");
disp(".........................");
disp([a b aNANDb]);
% NOR GATE

1
anorb=nor(a,b);
disp("TRUTH TABLE FOR NOR GATE");
disp(".........................");
disp(" a b aNORb");
disp(".........................");
disp([a b anorb]);

%LOGIC GATE USING NAND GATES


% AND using NAND gate
y1=nand(a,b);
y2=nand(y1,y1);
disp("TRUTH TABLE FOR AND using NAND gate");
disp(".........................");
disp(" a b aANDb");
disp(".........................");
disp([a b y2]);

% OR using NAND gate


y3=nand(a,a);
y4=nand(b,b);
y5=nand(y3,y4);
disp("TRUTH TABLE FOR OR using NAND gate");
disp(".........................");
disp(" a b aORb");
disp(".........................");
disp([a b y5]);

%NOT using NAND gate


y6=nand(a1,a1);
disp("TRUTH TABLE FOR NOT using NAND gate");
disp(".........................");
disp(" a ~a");
disp(".........................");
disp([a1 y6]);

%XOR using NAND GATE


y7=nand(a,b);
y8=nand(a,y7);
y9=nand(y7,b);
y10=nand(y8,y9);
disp("TRUTH TABLE FOR XOR using NAND gate");
disp(".........................");
disp(" a b aXORb");
disp(".........................");
disp([a b y10]);

%XNOR using NAND GATE


y11=~y10;
disp("TRUTH TABLE FOR XNOR using NAND gate");
disp(".........................");
disp(" a b aXNORb");
disp(".........................");
disp([a b y11]);

2
%LOGIC GATE USING NOR GATES
% OR using NOR gate
y1=nor(a,b);
y2=nor(y1,y1);
disp("TRUTH TABLE FOR OR using NOR gate");
disp(".........................");
disp(" a b aORb");
disp(".........................");
disp([a b y2]);

% AND using NAND gate


y3=nor(a,a);
y4=nor(b,b);
y5=nor(y3,y4);
disp("TRUTH TABLE FOR AND using NOR gate");
disp(".........................");
disp(" a b aANDb");
disp(".........................");
disp([a b y5]);

%NOT using NOR gate


y6=nor(a1,a1);
disp("TRUTH TABLE FOR NOT using NOR gate");
disp(".........................");
disp(" a ~a");
disp(".........................");
disp([a1 y6]);

%XOR using NOR GATE


y7=nor(a,b);
y8=nor(a,y7);
y9=nor(y7,b);
y10=nor(y8,y9);
y11=nor(y10,y10);
disp("TRUTH TABLE FOR XOR using NOR gate");
disp(".........................");
disp(" a b aXORb");
disp(".........................");
disp([a b y11]);

%XNOR using NOR GATE


y11=y10;
disp("TRUTH TABLE FOR XNOR using NOR gate");
disp(".........................");
disp(" a b aXNORb");
disp(".........................");
disp([a b y11]);

TRUTH TABLE FOR AND GATE


.........................
a b a.b
.........................
0 0 0
0 1 0

3
1 0 0
1 1 1

TRUTH TABLE FOR OR GATE


.........................
a b a|b
.........................
0 0 0
0 1 1
1 0 1
1 1 1

TRUTH TABLE FOR NOT GATE


.........................
a ~a
.........................
0 1
1 0

TRUTH TABLE FOR XOR GATE


.........................
a b aXORb
.........................
0 0 0
0 1 1
1 0 1
1 1 0

TRUTH TABLE FOR XOR GATE


.........................
a b aXNORb
.........................
0 0 1
0 1 0
1 0 0
1 1 1

TRUTH TABLE FOR NAND GATE


.........................
a b aNANDb
.........................
0 0 1
0 1 1
1 0 1
1 1 0

TRUTH TABLE FOR NOR GATE


.........................
a b aNORb
.........................
0 0 1
0 1 0
1 0 0
1 1 0

4
TRUTH TABLE FOR AND using NAND gate
.........................
a b aANDb
.........................
0 0 0
0 1 0
1 0 0
1 1 1

TRUTH TABLE FOR OR using NAND gate


.........................
a b aORb
.........................
0 0 0
0 1 1
1 0 1
1 1 1

TRUTH TABLE FOR NOT using NAND gate


.........................
a ~a
.........................
0 1
1 0

TRUTH TABLE FOR XOR using NAND gate


.........................
a b aXORb
.........................
0 0 0
0 1 1
1 0 1
1 1 0

TRUTH TABLE FOR XNOR using NAND gate


.........................
a b aXNORb
.........................
0 0 1
0 1 0
1 0 0
1 1 1

TRUTH TABLE FOR OR using NOR gate


.........................
a b aORb
.........................
0 0 0
0 1 1
1 0 1
1 1 1

TRUTH TABLE FOR AND using NOR gate

5
.........................
a b aANDb
.........................
0 0 0
0 1 0
1 0 0
1 1 1

TRUTH TABLE FOR NOT using NOR gate


.........................
a ~a
.........................
0 1
1 0

TRUTH TABLE FOR XOR using NOR gate


.........................
a b aXORb
.........................
0 0 0
0 1 1
1 0 1
1 1 0

TRUTH TABLE FOR XNOR using NOR gate


.........................
a b aXNORb
.........................
0 0 1
0 1 0
1 0 0
1 1 1

Published with MATLAB® R2023b

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