ECEN474: (Analog) VLSI Circuit Design

Fall 2012

Lecture 4: MOS Transistor Modeling

Sam Palermo
Analog & Mixed-Signal Center
Texas A&M University
Agenda
• MOS Transistor Modeling
• MOS Spice Models
• MOS High-Order Effects

• Current Reading
• Razavi Chapters 2 & 16

2
Why Do We Need MOS Spice Models?
• Analog circuits are sensitive to detailed transistor
behavior
• Bias conditions set operation mode, gain, bandwidth, …
• Can’t simply use logical modeling methods, as in digital
design flows

• Spice simulations allow us to predict the

performance of complex analog circuits with models
that capture high-order device operation
• Much easier and cheaper than actually fabricating the
circuit and performing physical measurements

3
MOS Level 1 Model
• Closely follows derived “Square-Law” Model
µ nCOX (VGS − VTn − 0.5VDS )VDS (1 + λVDS )
W
I DS = (Triode)
L − 2 LD

I DS =
1
µ nCOX
W
(VGS − VTn )2 (1 + λVDS ) (Saturation)
2 L − 2 LD

VT = VT 0 + γ [ 2φF + VSB − 2φF ]

• Note, extra 1+λVDS term in triode equation is to have
continuity between triode and saturation regions
• Reasonably accurate I/V characteristics for devices with L ≥
4µm, but models output resistance poorly
• Neglects subthreshold conduction and many high-order
effects in shorter-channel length devices
4
MOS Level 1 Model Parameters
[Razavi]

5
MOS Level 2 Model
• Improves upon the Level 1 model by modeling
• VT variation along the channel
• λ(VDS)
• Output conductance increases as VDS increases
• Mobility degradation due to vertical field and velocity saturation
• Subthreshold Behavior
• VT dependencies on transistor W & L

• Contains 5-10 more parameters than level 1 model

• Reasonably accurate I/V characteristics for devices
with L ≥ 0.7µm, but still poorly models output
resistance and transition point between saturation
and triode
6
MOS Level 3 Model
• Similar in complexity to the level 2 model,
but computationally more efficient

• Adds Drain-Induced Barrier Lowering effect

• VDS can lower effective VT

• Different model for mobility degradation

7
Velocity Saturation
• Square-law model assumes [Gray]
carrier drift velocity is
proportional to lateral E-field
vd = µE

• However, near critical

electric field Ec, carrier
velocity in silicon saturates
due to scattering
µE
vscl ≈ 105 m s vd ( E ) ≅ ≅ µEc = vscl for E >> Ec
E
1+
• Causes reduction in ID Ec
relative to square-law model =
vscl
for E = Ec
2
I D ∝ (VGS − VT ) (fully velocity saturated)

8
Mobility Degradation
• Carrier mobility is degraded by lateral E-field induced
velocity saturation AND vertical electric field strength

• Vertical field attracts carriers closer to silicon surface where

surface imperfections impede movement
Level 2 Model Level 3 Model

ε
U EXP
 µ eff
µ = µ 0  si
U CRIT
 µ=
µ eff VDS
 Cox VGS − VT − U TRAVDS  1+
vmax L
U CRIT = Gate - Channel Critical Field
µ0
U TRA = Fitting Parameter (0 - 0.5) µ eff =
1 + θ (VGS − VT )
U EXP = Exponent (~ 0.15)
vmax = Max Carrier Velocity
θ = Mobility Modulation Parameter (0.1 - 0.4 V -1 )

9
TAMU-474-08 J. Silva-Martinez

SPICE LEVEL2: Threshold Voltage is affected by many other effects!

For example: Channel width factor (DELTA), Charge in the channel

controlled by source and drain
W

D
L

L
XD
πX D 2
Q DW = LN sub q
4 S
Depletion region

VTT
Important effects on the threshold voltage

delta 2Q DW VT
VTT=VT+
8 WLCOX
W

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TAMU-474-08 J. Silva-Martinez

MOS Transistor: Threshold Voltage vs. L

L
Saturation REGION

Thin oxide Thick oxide

B S G D

S D

W
N+ P+ P+

substrate N

P-channel Depletion Controlled by Drain

VT
Controlled by Source region

Usually VT decreases when L is very small

L
< 2 um

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TAMU-474-08 J. Silva-Martinez

SPICE LEVEL3 (NON-LINEAR OUTPUT RESISTANCE)

KAPPA IS USED FOR THE COMPUTATION OF THE CHANNEL LENGTH MODULATION:

COMPUTATION OF ∆L IS MORE COMPLEX BUT MORE PRECISE:

2
 EPXD2  2
∆L =   + KX D 2 (VDS − Vdsat ) − P D
E X
 2  2
 

Notice that ∆L is funtion of:

• XD (technology parameter)
• VGS-VT (Saturation voltage) Design parameter.
• Output resistance is function of L, ID and VDSAT!! R~ ∆L/ID

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TAMU-474-08 J. Silva-Martinez

Design Example: Constant current

m1 vd1 vd1 0 0 l=0.8u w=10u ad=20p ps=30u pd=30u
m2 vd2 vd2 0 0 l=1.6u w=20u ad=40p ps=40u pd=40u
m3 vd3 vd3 0 0 l=2.4u w=30u ad=60p ps=50u pd=50u
m4 vd4 vd4 0 0 l=3.2u w=40u ad=60p ps=50u pd=50u
m5 vd5 vd5 0 0 l=4u w=50u ad=60p ps=50u pd=50u
20 µA
element 0:m1 0:m2 0:m3 0:m4 0:m5
id 20.0000u 20.0000u 20.0000u 20.0000u 20.0000u
vgs 886.9381m 969.8944m 995.7306m 1.0083 1.0158
vds 886.9381m 969.8944m 995.7306m 1.0083 1.0158
vth 666.2501m 736.9148m 758.7246m 769.3286m 775.5978m
vdsat 154.8212m 165.3264m 168.8038m 170.5361m 171.5733m
beta 1.0881m 1.0045m 979.6687u 967.7676u 960.7872u
gam eff 571.2190m 652.2787m 677.2968m 689.4607m 696.6521m
gm 179.7789u 171.7391u 169.1462u 167.8681u 167.1073u
gds 4.6916u 2.0549u 1.3150u 966.8425n 764.4227n
gmb 47.5488u 57.1768u 59.8797u 61.1497u 61.8872u
cdtot 14.6665f 24.6840f 34.7712f 37.7241f 40.7319f
cgtot 12.3872f 40.7364f 85.1087f 145.5042f 221.9229f
cstot 23.4292f 57.2574f 106.5620f 162.0429f 233.0002f
cbtot 26.4024f 43.6549f 61.4591f 63.3113f 65.7005f
cgs 9.1292f 33.6574f 73.6620f 129.1429f 200.1002f
cgd 2.9110f 5.8540f 8.8294f 11.8370f 14.8771f

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 TAMU-474-08 J. Silva-Martinez

Design Example: Constant voltages

i1 vdd vd1 dc 50u
m1 vd1 vd1 0 0 nmos l=0.8u w=10u ad=20p ps=30u pd=30u
m2 vdd vd1 0 0 nmos l=0.8u w=10u ad=20p ps=30u pd=30u
m3 vdd vd1 0 0 nmos l=1.6u w=20u ad=40p ps=40u pd=40u
m4 vdd vd1 0 0 nmos l=2.4u w=30u ad=60p ps=50u pd=50u
m5 vdd vd1 0 0 nmos l=3.2u w=40u ad=60p ps=50u pd=50u
50 µA m6 vdd vd1 0 0 nmos l=4u w=50u ad=60p ps=50u pd=50u

element 0:m1 0:m2 0:m3 0:m4 0:m5 0:m6

id 50.0000u 54.0916u 29.4063u 23.7290u 21.2627u 19.8905u
vgs 1.0131 1.0131 1.0131 1.0131 1.0131 1.0131
vth 664.089m 656.629m 733.0935m 756.3653m 767.6259m 774.2667m
vdsat 234.1784m 239.2634m 197.9108m 182.8535m 175.2647m 170.7093m
beta 1.0921m 1.1291m 1.0195m 988.7500u 974.2790u 965.8602u
gam eff 568.7409m 560.1827m 647.8953m 674.5905m 687.5075m 695.1252m
gm 281.3687u 298.2144u 210.1394u 185.3381u 173.8114u 167.1665u
gds 8.4442u 7.4984u 2.1990u 1.2244u 838.6260n 635.1918n
Array of transistors; gmb 71.9153u 75.4782u 69.0048u 65.2081u 63.1445u 61.8658u
only 4 transistors are cdtot 14.4417f 13.7280f 23.3207f 32.9599f 36.0176f 39.1218f
cgtot 12.3095f 12.3127f 40.6138f 85.0154f 145.5222f 222.1355f
shown. cstot 23.4292f 23.4292f 57.2574f 106.5620f 162.0429f 233.0002f
cbtot 26.0967f 25.3740f 42.1100f 59.4235f 61.3917f 63.9436f
cgs 9.1292f 9.1292f 33.6574f 73.6620f 129.1429f 200.1002f
cgd 2.9126f 2.9187f 5.8836f 8.8949f 11.9526f 15.0568f

Take advantage of the operating point information!!!!

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 TAMU-474-08 J. Silva-Martinez

• Avalanche: drain current ID and a substrate current IB

• The substrate current may contribute to latch-up

• The device noise increases

• The output impedance decreases

• Carriers can be trapped on the oxide and the VTh changes (hot electron
effect)
- 15 -
 Drain Induced Barrier Lowering
[Razavi]

[Stockinger]

• Drain potential controls channel charge also

• Higher VDS reduces barrier to the flow of charge,
resulting in a net reduction in the threshold voltage
16
 TAMU-474-08 J. Silva-Martinez

Saturation region :

ε
L
=
1
= 1+ (VDS − Vsat ) ≅ 1 + λVDS
L − ∆L 2ε 2
1− 2
(VDS − Vsat ) qN A L
qN A L
More accurate expression of the output conductance :

  I
 ∂V T h  D ∂µ ∂I S
g ds = λI D − g m ⋅ + ⋅ +
 ∂V DS  µ ∂V
  DS ∂V DS

(first order) (short channel) (velocity saturation) (avalanching)

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BSIM Model
• Berkeley Short-Channel IGFET Model (BSIM)
• Industry standard model for modern devices
• BSIM3v3 is model for this course

• Typically 40-100+ parameters

• Advanced software and expertise needed to
perform extraction

18
 Class 0.6µm Technology Model (NMOS)
*N8BN SPICE BSIM3 VERSION 3.1 (HSPICE Level 49) PARAMETERS XL=0 & CAPMOD=2 &
* level 11 for Cadence Spectre XW=0 & XPART=0.4 &
* DATE: Jan 25/99 DWG=-1.446149E-8 & CGDO=1.99E-10 &
* LOT: n8bn WAF: 03 DWB=2.077539E-8 & CGSO=1.99E-10 &
* Temperature_parameters=Default VOFF=-0.1137226 & CGBO=0 &
.MODEL ami06N NMOS ( LEVEL=11 & NFACTOR=1.2880596 & CJ=4.233802E-4 &
VERSION=3.1 & CIT=0 & PB=0.9899238 &
TNOM=27 & CDSC=1.506004E-4 & MJ=0.4495859 &
TOX=1.41E-8 & CDSCD=0 & CJSW=3.825632E-10 &
XJ=1.5E-7 & CDSCB=0 & PBSW=0.1082556 &
NCH=1.7E17 & ETA0=3.815372E-4 & MJSW=0.1083618 &
VTH0=0.7086 & ETAB=-1.029178E-3 & PVTH0=0.0212852 &
K1=0.8354582 & DSUB=2.173055E-4 & PRDSW=-16.1546703 &
K2=-0.088431 & PCLM=0.6171774 & PK2=0.0253069 &
K3=41.4403818 & PDIBLC1=0.185986 & WKETA=0.0188633 &
K3B=-14 & PDIBLC2=3.473187E-3 & LKETA=0.0204965 )
W0=6.480766E-7 & PDIBLCB=-1E-3 &
NLX=1E-10 & DROUT=0.4037723 &
DVT0W=0 & PSCBE1=5.998012E9 &
DVT1W=5.3E6 & PSCBE2=3.788068E-8 &
DVT2W=-0.032 & PVAG=0.012927 &
DVT0=3.6139113 & DELTA=0.01 &
DVT1=0.3795745 & MOBMOD=1 &
DVT2=-0.1399976 & PRT=0 &
U0=533.6953445 & UTE=-1.5 &
UA=7.558023E-10 & KT1=-0.11 &
UB=1.181167E-18 & KT1L=0 &
UC=2.582756E-11 & KT2=0.022 &
VSAT=1.300981E5 & UA1=4.31E-9 &
A0=0.5292985 & UB1=-7.61E-18 &
AGS=0.1463715 & UC1=-5.6E-11 &
B0=1.283336E-6 & AT=3.3E4 &
B1=1.408099E-6 & WL=0 &
KETA=-0.0173166 & WLN=1 &
A1=0 & WW=0 &
A2=1 & WWN=1 &
RDSW=2.268366E3 & WWL=0 &
PRWG=-1E-3 & LL=0 &
PRWB=6.320549E-5 & LLN=1 &
WR=1 & LW=0 &
WINT=2.043512E-7 & LWN=1 &
LINT=3.034496E-8 & LWL=0 &

19
VT Dependency on W
• Gate-controlled depletion
W
region extends in part
outside the gate width

• VT monotonically increases [Pierret]

with decreasing channel
width

VT = VTwide + ∆VT
qN AWT πWT
∆VT = L=4u
Cox 2W

L=0.6u

20
VT Dependency on L
• Source and drain assist in
forming the depletion
region under the gate

[Pierret]
• With simple model, VT
monotonically decreases
with decreasing channel
length
W=1.5u

VT = VTlong + ∆VT

qN AWT rj  2WT  W=50u

∆VT = − 1+ − 1
Cox L  rj 


21
Temperature Dependence
• Transistor mobility and threshold
voltage are dependent on temperature 32
 300 
• Mobility ∝T-3/2 due to increased scattering µ = µ0  
 T 
• Threshold voltage decreases with 7.02 ×10 −4 T 2
temperature due to reduced bandgap energy E g = 1.16 −
T + 1108

ID vs Temperature VT vs Temperature

W=2.4u, L=0.6u W=2.4u, L=0.6u

-3%
-23%

22
Process Corners
• Substantial process variations can exist from wafer to
wafer and lot to lot
• Device characteristics are guaranteed to lie in a
performance envelope
• To guarantee circuit yield, designers simulate over the
“corners” of this envelope
• Example: Slow Corner
• Thicker oxide (high VT, low Cox), low µ, high R

SF FF
TT

SS FS

[Razavi]
23
Inverter Delay Variation with
Process & Temperature
0.13µm CMOS

[Woo ISSCC 2009]

• CMOS inverter delay varies close to ±40%

over process and temperature
24
Next Time
• Layout Techniques

25