19-5959; Rev 1; 7/12

KIT
ATION
EVALU BL E
AVAILA

Complete Direct-Conversion L-Band Tuner

General Description Features

MAX2121
The MAX2121 low-cost, direct-conversion tuner IC is o 925MHz to 2175MHz Frequency Range
designed for satellite set-top and VSAT applications. o Monolithic VCO
The device directly converts the satellite signals from Low Phase Noise: -97dBc/Hz at 10kHz
the LNB to baseband using a broadband I/Q downcon- No Calibration Required
verter. The operating frequency range extends from o High Dynamic Range: -75dBm to 0dBm
925MHz to 2175MHz. o Integrated LP Filters: 123.75MHz
The device includes an LNA and an RF variable-gain o Single +3.3V ±5% Supply
amplifier, I and Q downconverting mixers, and base- o Low-Power Standby Mode
band lowpass filters and digitally controlled baseband
variable-gain amplifiers. Together, the RF and base- o Address Pin for Multituner Applications
band variable-gain amplifiers provide more than 80dB o Differential I/Q Interface
of gain control range. o I2C 2-Wire Serial Interface
The device includes fully monolithic VCOs, as well as a o Very Small, 5mm x 5mm, 28-Pin TQFN Package
complete fractional-N frequency synthesizer.
Additionally, an on-chip crystal oscillator is provided Ordering Information
along with a buffered output for driving additional tuners
and demodulators. Synthesizer programming and device PART TEMP RANGE PIN-PACKAGE
configuration are accomplished with a 2-wire serial inter- MAX2121ETI+ -40°C to +85°C 28 TQFN-EP*
face. The IC features a VCO autoselect (VAS) function
that automatically selects the proper VCO. For multituner *EP = Exposed pad.
applications, the device can be configured to have one +Denotes a lead(Pb)-free/RoHS-compliant package.
of two 2-wire interface addresses. A low-power standby
mode is available whereupon the signal path is shut Functional Diagram
down while leaving the reference oscillator, digital inter-
face, and buffer circuits active, providing a method to
VCC_BB
ADDR

QDC+
QDC-

IDC-
SCL

SDA

reduce power in single and multituner applications.

The device is the most advanced broadband/VSAT + 28 27 26 25 24 23 22

DBS tuner available. The low noise figure eliminates the VCC_RF2 1 DC OFFSET 21 IDC+
need for an external LNA. A small number of passive INTERFACE LOGIC CORRECTION
AND CONTROL MAX2121
components are needed to form a complete broadband VCC_RF1 2 20 IOUT-
satellite tuner DVB-S2 RF front-end solution. The tuner
is available in a very small, 5mm x 5mm, 28-pin thin
GND 3 19 IOUT+
QFN package.

Applications RFIN 4 18 QOUT-

VSATs
GC1 5 17 QOUT+

FREQUENCY
DIV2/DIV4 SYNTHESIZER
VCC_LO 6 16 VCC_DIG
EP

VCC_VCO 7 15 REFOUT

8 9 10 11 12 13 14
BYPVCO

TUNEVCO

GNDTUNE

GNDSYN

CPOUT

VCC_SYN

XTAL

For pricing, delivery, and ordering information, please contact Maxim Direct 1
at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
 Complete Direct-Conversion L-Band Tuner
ABSOLUTE MAXIMUM RATINGS
MAX2121

VCC_ to GND .........................................................-0.3V to +3.9V Operating Temperature Range .............................-40°C to +85°C

All Other Pins to GND.................................-0.3V to (VCC + 0.3V) Junction Temperature ......................................................+150°C
RF Input Power: RFIN .....................................................+10dBm Storage Temperature Range .............................-65°C to +160°C
BYPVCO, CPOUT, XTAL, REFOUT, IOUT_, QOUT_ , IDC_, Lead Temperature (soldering, 10s) .................................+300°C
QDC_ to GND Short-Circuit Protection...............................10s Soldering Temperature (reflow) .......................................+260°C
Continuous Power Dissipation (TA = +70°C)
TQFN (derate 34.5mW/°C above +70°C) ......................2.75W
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

CAUTION! ESD SENSITIVE DEVICE

DC ELECTRICAL CHARACTERISTICS
(MAX2121 Evaluation Kit: VCC_ = +3.13V to +3.47V, fXTAL = 27MHz, TA = -40°C to +85°C, VGC1 = +0.5V (max gain), default register
settings except BBG[3:0] = 1011. No input signals at RF, baseband I/Os are open circuited. Typical values measured at VCC =
+3.3V, TA = +25°C, unless otherwise noted.) (Note 1)

PARAMETER CONDITIONS MIN TYP MAX UNITS

SUPPLY
Supply Voltage (VCC_) 3.13 3.3 3.47 V
Receive mode, bit STBY = 0 148 200
Supply Current mA
Standby mode, bit STBY = 1 3
ADDRESS SELECT INPUT (ADDR)
Digital Input-Voltage High, VIH 2.4 V
Digital Input-Voltage Low, VIL 0.5 V
Digital Input-Current High, IIH 50 µA
Digital Input-Current Low, I IL -50 µA
ANALOG GAIN-CONTROL INPUT (GC1)
Input Voltage Range Maximum gain = 0.5V 0.5 2.7 V
Input Bias Current -50 +50 µA
VCO TUNING VOLTAGE INPUT (TUNEVCO)
Input Voltage Range 0.4 2.3 V
2-WIRE SERIAL INPUTS (SCL, SDA)
Clock Frequency 400 kHz
0.7 x
Input Logic-Level High V
VCC
0.3 x
Input Logic-Level Low V
VCC
Input Leakage Current Digital inputs = GND or VCC ±0.1 ±1 µA
2-WIRE SERIAL OUTPUT (SDA)
Output Logic-Level Low I SINK = 1mA (Note 2) 0.4 V

2
 Complete Direct-Conversion L-Band Tuner
AC ELECTRICAL CHARACTERISTICS

MAX2121
(MAX2121 Evaluation Kit: VCC = +3.13V to +3.47V, TA = -40°C to +85°C, default register settings except BBG[3:0] = 1111. Typical
values measured at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Note 1)

PARAMETER CONDITIONS MIN TYP MAX UNITS

MAIN SIGNAL PATH PERFORMANCE
Minimum Gain f IN = 2175MHz 72 78 dB
Gain Flatness 925MHz to 2175MHz (Note 2) 4 6 dB
Input Frequency Range (Note 3) 925 2175 MHz
RF Gain-Control Range (GC1) 0.5V < VGC1 < 2.7V 65 73 dB
Baseband Gain-Control Range Bits BBG[3:0] = 1111 to 0000 11.5 13.5 dB
In-Band Input IP3 (Note 4) +2 dBm
Out-of-Band Input IP3 (Note 5) +15 dBm
Input IP2 (Note 6) +40 dBm
VGC1 is set to 0.5V (maximum RF gain) and BBG[3:0]
is adjusted to give a 1VP-P baseband output level for a 8
Noise Figure -75dBm CW input tone at 1500MHz dB
Starting with the same BBG[3:0] setting as above,
9 12
VGC1 is adjusted to back off RF gain by 10dB (Note 2)
Minimum RF Input Return Loss
925MHz < fRF < 2175MHz, in 75
system 12 dB
BASEBAND OUTPUT CHARACTERISTICS
Nominal Output Voltage Swing RLOAD = 200
//5pF 0.5 1 VP-P
I/Q Amplitude Imbalance Measured at 500kHz ±1 dB
I/Q Quadrature Phase Imbalance Measured at 500kHz 3.5 Degrees
Single-Ended I/Q Output
Real Z O, from 1MHz to 140MHz 24

Impedance
Output 1dB Compression Voltage Differential 3 VP-P
Baseband Highpass -3dB
47nF capacitors at IDC_, QDC_ 400 Hz
Frequency Corner
BASEBAND LOWPASS FILTERS (5th-Order Butterworth with 1st-Order Group Delay Compensation)
Filter Bandwidth (-3dB) 123.75 MHz
Rejection Ratio At 247.5MHz 31 dB
Group Delay Up to 0.5dB bandwidth 1.0 ns
3dB Bandwidth Tolerance ±10 %
FREQUENCY SYNTHESIZER
RF-Divider Frequency Range 925 2175 MHz
RF-Divider Range (N) 19 251
Reference-Divider Frequency
12 30 MHz
Range
Reference-Divider Range (R) 1 1
Phase-Detector Comparison
12 30 MHz
Frequency

3
 Complete Direct-Conversion L-Band Tuner
AC ELECTRICAL CHARACTERISTICS (continued)
MAX2121

(MAX2121 Evaluation Kit: VCC = +3.13V to +3.47V, TA = -40°C to +85°C, default register settings except BBG[3:0] = 1111. Typical
values measured at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Note 1)

PARAMETER CONDITIONS MIN TYP MAX UNITS

VOLTAGE-CONTROLLED OSCILLATOR AND LO GENERATION
Guaranteed LO Frequency Range 925 2175 MHz
f OFFSET = 10kHz -97
LO Phase Noise f OFFSET = 100kHz -100 dBc/Hz
f OFFSET = 1MHz -122
XTAL/REFERENCE OSCILLATOR INPUT AND OUTPUT BUFFER
XTAL Oscillator Frequency
Parallel-resonance-mode crystal (Note 7) 12 30 MHz
Range f XTAL
Input Overdrive Level AC-coupled sine-wave input 0.5 1 2.0 VP-P
XTAL Output-Buffer Divider
1 8
Range
XTAL Output Voltage Swing 12MHz to 30MHz, CLOAD = 10pF 1 1.5 2 VP-P
XTAL Output Duty Cycle 50 %
Note 1: Min/max values are production tested at TA = +25°C. Min/max limits at TA = -40°C and TA = +85°C are guaranteed by
design and characterization.
Note 2: Guaranteed by design and characterization at TA = +25°C.
Note 3: Input gain range specifications met over this band.
Note 4: In-band IIP3 test conditions: GC1 set to provide the nominal baseband output drive when mixing down a -23dBm tone at
2175MHz to 5MHz baseband (fLO = 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at
-26dBm each are applied at 2174MHz and 2175MHz. The IM3 tone at 3MHz is measured at baseband, but is referred to the
RF input.
Note 5: Out-of-band IIP3 test conditions: GC1 set to provide nominal baseband output drive when mixing down a -23dBm tone at
2175MHz to 5MHz baseband (fLO = 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at
-20dBm each are applied at 1919MHz and 1663MHz. The IM3 tone at 5MHz is measured at baseband, but is referred to the
RF input.
Note 6: Input IP2 test conditions: GC1 set to provide nominal baseband output drive when mixing down a -23dBm tone at 2175MHz
to 5MHz baseband (fLO = 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at -20dBm
each are applied at 925MHz and 1250MHz. The IM2 tone at 5MHz is measured at baseband, but is referred to the RF input.
Note 7: See Table 16 for crystal ESR requirements.

4
 Complete Direct-Conversion L-Band Tuner
Typical Operating Characteristics

MAX2121
(MAX2121 Evaluation Kit: VCC = +3.3V, TA = +25°C, baseband output frequency = 5MHz, VGC1 = +1.2V, default register settings
except BBG[3:0] = 1011, unless otherwise noted.)
STANDBY SUPPLY CURRENT
SUPPLY CURRENT vs. SUPPLY VOLTAGE vs. SUPPLY VOLTAGE HD3 vs. VOUT
175 3.0 -10

MAX2121 toc02
MAX2121 toc01

MAX2121 toc03
BASEBAND 3RD-ORDER HARMONIC (dBc)
170 TA = +85°C -15

STANDBY SUPPLY CURRENT (mA)

165 -20
2.5
SUPPLY CURRENT (mA)

160 -25
155 TA = +85°C -30
TA = +25°C
150 2.0 -35
145 -40
140 TA = -40°C -45
TA = -40°C 1.5
135 -50
130 -55
125 1.0 -60
3.1 3.2 3.3 3.4 3.5 3.1 3.2 3.3 3.4 3.5 1.0 1.5 2.0 2.5 3.0
SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) VOUT (VP-P)

QUADRATURE PHASE ERROR QUADRATURE MAGNITUDE MATCHING QUADRATURE PHASE ERROR

vs. LO FREQUENCY vs. LO FREQUENCY vs. BASEBAND FREQUENCY
3.5 1.0 3.5
MAX2121 toc04

MAX2121 toc05

MAX2121 toc06
fBASEBAND = 50MHz fBASEBAND = 50MHz fLO = 1425MHz
QUADRATURE MAGNITUDE MATCHING (dB)

3.0 3.0
QUADRATURE PHASE ERROR (DEG)

QUADRATURE PHASE ERROR (DEG)

0.8 TA = -40°C
2.5 2.5
TA = +25°C TA = +85°C
0.6
2.0 TA = -40°C 2.0

1.5 1.5 TA = +25°C

0.4

1.0 TA = -40°C 1.0

TA = +85°C
TA = +85°C 0.2
0.5 TA = +25°C 0.5

0 0 0
900 1150 1400 1650 1900 2150 900 1150 1400 1650 1900 2150 0.1 1 10 100
LO FREQUENCY (MHz) LO FREQUENCY (MHz) BASEBAND FREQUENCY (MHz)

QUADRATURE MAGNITUDE MATCHING

vs. BASEBAND FREQUENCY BASEBAND FILTER FREQUENCY RESPONSE BASEBAND FILTER FREQUENCY RESPONSE
1.0 0 1
MAX2121 toc07

MAX2121 toc08

MAX2121 toc09

fLO = 1425MHz
QUADRATURE MAGNITUDE MATCHING (dB)

-5 0
-10
-1
BASEBAND OUTPUT LEVEL (dB)

BASEBAND OUTPUT LEVEL (dB)

0.8
-15
-2
-20
TA = +25°C -25 -3
0.6
-30 -4
-35 -5 TA = +25°C
0.4 -40 -6
-45
TA = +85°C -7
-50
0.2 -8
-55
TA = -40°C -60 -9
0 -65 -10
0.1 1 10 100 0 100 200 300 400 500 0 25 50 75 100 125 150
BASEBAND FREQUENCY (MHz) BASEBAND FREQUENCY (MHz) BASEBAND FREQUENCY (MHz)

5
 Complete Direct-Conversion L-Band Tuner
Typical Operating Characteristics (continued)
MAX2121

(MAX2121 Evaluation Kit: VCC = +3.3V, TA = +25°C, baseband output frequency = 5MHz, VGC1 = +1.2V, default register settings
except BBG[3:0] = 1011, unless otherwise noted.)

BASEBAND FILTER 3dB FREQUENCY BASEBAND FILTER HIGHPASS

vs. TEMPERATURE FREQUENCY RESPONSE VOLTAGE GAIN vs. VGC1
1.00 0 80

MAX2121 toc12
MAX2121 toc10

MAX2121 toc11
NORMALIZED AT TA = +25°C
-1
BASEBAND GAIN ERROR AT f-3dB (dB)

0.75 70
BASEBAND OUTPUT LEVEL (dB) -2 BBG[3:0] = 1111
0.50 60
-3

VOLTAGE GAIN (dB)

0.25 50
-4
0 -5 40

-0.25 -6 30
-7
-0.50 20
-8
-0.75 10
-9
-1.00 -10 0
-40 -20 0 20 40 60 80 100 1000 10,000 0 0.5 1.0 1.5 2.0 2.5 3.0
TEMPERATURE (°C) BASEBAND FREQUENCY (Hz) VGC1 (V)

NOISE FIGURE vs. LO FREQUENCY

(TA = +25°C) NOISE FIGURE vs. INPUT POWER OUT-OF-BAND IIP3 vs. INPUT POWER
11.0 35 30
MAX2121 toc13

MAX2121 toc14

MAX2121 toc15
ADJUST BBG[3:0] for 1VP-P SEE NOTE 5 ON PAGE 4 FOR CONDITIONS
10.5 BASEBAND OUTPUT WITH PIN = -75dBm
ADJUST BBG[3:0] FOR 1VP-P BASEBAND 30 AND VGC1 = -0.5V, fLO = 1500MHz 20
OUTPUT WITH PIN = -75dBm AND VGC1 = 0.5V
OUT-OF-BAND IIP3 (dBm)

10.0
NOISE FIGURE (dB)

NOISE FIGURE (dB)

25 10
9.5

9.0 10dB BACKED OFF GAIN 20 0

8.5
15 -10
8.0
10 -20
7.5

7.0 5 -30
900 1150 1400 1650 1900 2150 -75 -65 -55 -45 -35 -75 -65 -55 -45 -35 -25 -15 -5
LO FREQUENCY (MHz) INPUT POWER (dBm) INPUT POWER (dBm)

IN-BAND IIP3 vs. INPUT POWER IIP2 vs. INPUT POWER INPUT RETURN LOSS vs. FREQUENCY
20 40 0
MAX2121 toc16

MAX2121 toc17

MAX2121 toc18

SEE NOTE 4 ON PAGE 4 FOR CONDITIONS SEE NOTE 6 ON PAGE 4

10 35 FOR CONDITIONS
30 -5
0
INPUT RETURN LOSS (dB)

25
IN-BAND IIP3 (dBm)

-10 20 VGC1 = 0.5V

IIP2 (dBm)

-10
-20 15

-30 10 -15
5
-40
0 -20
-50 -5
VGC1 = 2.7V
-60 -10 -25
-75 -65 -55 -45 -35 -25 -15 -5 -75 -65 -55 -45 -35 -25 -15 -5 900 1125 1350 1575 1800 2025 2250
INPUT POWER (dBm) INPUT POWER (dBm) FREQUENCY (MHz)

6
 Complete Direct-Conversion L-Band Tuner
Typical Operating Characteristics (continued)

MAX2121
(MAX2121 Evaluation Kit: VCC = +3.3V, TA = +25°C, baseband output frequency = 5MHz, VGC1 = +1.2V, default register settings
except BBG[3:0] = 1011, unless otherwise noted.)

PHASE NOISE AT 10kHz OFFSET vs.

CHANNEL FREQUENCY PHASE NOISE vs. OFFSET FREQUENCY
-90 -90

MAX2121 toc20
MAX2121 toc19
PHASE NOISE AT 10kHz OFFSET (dBc/Hz)

-100

PHASE NOISE (dBc/Hz)

-95

-110

-100
-120

fLO = 1800MHz
-105 -130
925 1115 1305 1495 1685 1875 2065 2255 1.0E+03 1.0E+04 1.0E+05 1.0E+06
CHANNEL FREQUENCY (MHz) OFFSET FREQUENCY (Hz)

LO LEAKAGE vs. LO FREQUENCY VCO: KV vs. VTUNE

-70 450
MAX2121 toc21

MAX2121 toc22
MEASURED AT RF INPUT
400

350 SUB-BAND 23
-75
LO LEAKAGE (dBm)

300
KV (MHz/V)

250
-80
200 SUB-BAND 12
150
-85
100

50 SUB-BAND 0
-90 0
925 1175 1425 1675 1925 2175 0 0.5 1.0 1.5 2.0 2.5 3.0
LO FREQUENCY (MHz) VTUNE (V)

7
 Complete Direct-Conversion L-Band Tuner
Pin Configuration
MAX2121

VCC_BB
ADDR

QDC+
QDC-
TOP VIEW

IDC-
SCL

SDA
28 27 26 25 24 23 22

VCC_RF2 1 21 IDC+

+
VCC_RF1 2 20 IOUT-

GND 3 19 IOUT+

MAX2121
RFIN 4 18 QOUT-

GC1 5 17 QOUT+

VCC_LO 6 16 VCC_DIG
EP

VCC_VCO 7 15 REFOUT

8 9 10 11 12 13 14
BYPVCO

TUNEVCO

GNDTUNE

GNDSYN

CPOUT

VCC_SYN

XTAL

TQFN
(5mm x 5mm)

Pin Description
PIN NAME FUNCTION
DC Power Supply for LNA. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor
1 VCC_RF2
connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections.
DC Power Supply for LNA. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor
2 VCC_RF1
connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections.
3 GND Ground. Connect to board’s ground plane for proper operation.
4 RFIN Wideband 75 RF Input. Connect to an RF source through a DC-blocking capacitor.
RF Gain-Control Input. High-impedance analog input with a 0.5V to 2.7V operating range.
5 GC1
VGC1 = 0.5V corresponds to the maximum gain setting.
DC Power Supply for LO Generation Circuits. Connect to a +3.3V low-noise supply. Bypass to GND
6 VCC_LO with a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias
with other ground connections.
DC Power Supply for VCO Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF
7 VCC_VCO capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other
ground connections.

8
 Complete Direct-Conversion L-Band Tuner
Pin Description (continued)

MAX2121
PIN NAME FUNCTION
Internal VCO Bias Bypass. Bypass to GND with a 100nF capacitor connected as close as possible to
8 BYPVCO
the pin. Do not share capacitor ground vias with other ground connections.
High-Impedance VCO Tune Input. Connect the PLL loop filter output directly to this pin with as short of
9 TUNEVCO
a connection as possible.
10 GNDTUNE Ground for TUNEVCO. Connect to the PCB ground plane.
11 GNDSYN Ground for Synthesizer. Connect to the PCB ground plane.
Charge-Pump Output. Connect this output to the PLL loop filter input with the shortest
12 CPOUT
connection possible.
DC Power Supply for Synthesizer Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with
13 VCC_SYN a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with
other ground connections.
Crystal-Oscillator Interface. Use with an external parallel-resonance-mode crystal through a series
14 XTAL
1nF capacitor. See the Typical Application Circuit.
15 REFOUT Crystal-Oscillator Buffer Output. A DC-blocking capacitor must be used when driving external circuitry.
DC Power Supply for Digital Logic Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with
16 VCC_DIG a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with
other ground connections.
17 QOUT+
Quadrature Baseband Differential Output. AC-couple with 47nF capacitors to the demodulator input.
18 QOUT-
19 IOUT+
In-Phase Baseband Differential Output. AC-couple with 47nF capacitors to the demodulator input.
20 IOUT-
21 IDC+
I-Channel Baseband DC Offset Correction. Connect a 47nF ceramic chip capacitor from IDC- to IDC+.
22 IDC-
23 QDC+
Q-Channel Baseband DC Offset Correction. Connect a 47nF ceramic chip capacitor from QDC- to QDC+.
24 QDC-
DC Power Supply for Baseband Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with
25 VCC_BB a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with
other ground connections.
26 SDA 2-Wire Serial-Data Interface. Requires
1k pullup resistor to VCC.
27 SCL 2-Wire Serial-Clock Interface. Requires
1k pullup resistor to VCC.
28 ADDR Address. Must be connected to either ground (logic 0) or supply (logic 1).
— EP Exposed Pad. Solder evenly to the board’s ground plane for proper operation.

9
 Complete Direct-Conversion L-Band Tuner
Detailed Description shows each bit name and the bit usage information for all
MAX2121

registers. Note that all registers must be written after and

Register Description no earlier than 100µs after the device is powered up. The
The MAX2121 includes 12 user-programmable registers VCO autoselection circuit is triggered by writing to regis-
and two read-only registers. See Table 1 for register ter 5. Thus register 5 should be the last register to be
configurations. The register configuration of Table 1 written in order to ensure proper PLL lock.

Table 1. Register Configuration

MSB LSB
REG REGISTER READ/ REG
DATA BYTE
NUMBER NAME WRITE ADDRESS
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
N-Divider FRAC
1 Write 0x00 N[14] N[13] N[12] N[11] N[10] N[9] N[8]
MSB 1
N-Divider
2 Write 0x01 N[7] N[6] N[5] N[4] N[3] N[2] N[1] N[0]
LSB
Charge CPMP[1] CPMP[0] CPLIN[1] CPLIN[0]
3 Write 0x02 F[19] F[18] F[17] F[16]
Pump 0 0 0 1
F-Divider
4 Write 0x03 F[15] F[14] F[13] F[12] F[11] F[10] F[9] F[8]
MSB
F-Divider
5 Write 0x04 F[7] F[6] F[5] F[4] F[3] F[2] F[1] F[0]
LSB
XTAL
Buffer and
6 Write 0x05 XD[2] XD[1] XD[0] R[4] R[3] R[2] R[1] R[0]
Reference
Divider
7 PLL Write 0x06 D24 CPS ICP X X X X X
8 VCO Write 0x07 VCO[4] VCO[3] VCO[2] VCO[1] VCO[0] VAS ADL ADE
Lowpass
9 Write 0x08 10010111
Filter
PWDN
10 Control Write 0x09 STBY X X BBG[3] BBG[2] BBG[1] BBG[0]
0
PLL DIV VCO BB RFMIX RFVGA FE
11 Shutdown Write 0x0A X
0 0 0 0 0 0 0
LD LD LD
CPTST[2] CPTST[1] CPTST[0] TURBO
12 Test Write 0x0B X MUX[2] MUX[1] MUX[0]
0 0 0 1
0 0 0
Status
13 Read 0x0C POR VASA VASE LD X X X X
Byte-1
Status
14 Read 0x0D VCOSBR[4] VCOSBR[3] VCOSBR[2] VCOSBR[1] VCOSBR[0] ADC[2] ADC[1] ADC[0]
Byte-2
X = Don’t care. 0 = Set to 0 for factory-tested operation. 1 = Set to 1 for factory-tested operation.

10
 Complete Direct-Conversion L-Band Tuner
Table 2. N-Divider MSB Register (Address: 0x00)

MAX2121
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
FRAC 7 1 Users must program to 1 upon powering up the device.
Sets the most significant bits of the PLL integer-divide number (N). N can
N[14:8] 6–0 0000000
range from 19 to 251.

Table 3. N-Divider LSB Register (Address: 0x01)

BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
Sets the least significant bits of the PLL integer-divide number. N can range
N[7:0] 7–0 00100011
from 19 to 251.

Table 4. Charge-Pump Register (Address: 0x02)

BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
Charge-pump minimum pulse width. Users must program to 00 upon
CPMP[1:0] 7–6 00
powering up the device.
Controls charge-pump linearity. Users must program to 01 upon powering
CPLIN[1:0] 5–4 00
up the device.
Sets the 4 most significant bits of the PLL fractional divide number.
F[19:16] 3–0 0010
Default value is F = 194,180 decimal.

Table 5. F-Divider MSB Register (Address: 0x03)

BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
Sets the most significant bits of the PLL fractional-divide number (F).
F[15:8] 7–0 11110110
Default value is F = 194,180 decimal.

Table 6. F-Divider LSB Register (Address: 0x04)

BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
Sets the least significant bits of the PLL fractional-divide number (F).
F[7:0] 7–0 10000100
Default value is F = 194,180 decimal.

Table 7. XTAL Buffer and Reference Divider Register (Address: 0x05)

BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
Sets the crystal-divider setting.
000 = Divide by 1.
001 = Divide by 2.
XD[2:0] 7–5 000 011 = Divide by 3.
100 = Divide by 4.
101 through 110 = All divide values from 5 (101) to 7 (110).
111 = Divide by 8.
Sets the PLL reference-divider (R) number. Users must program to 00001
R[4:0] 4–0 00001 upon powering up the device.
00001 = Divide by 1; other values are not tested.

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 Complete Direct-Conversion L-Band Tuner
Table 8. PLL Register (Address: 0x06)
MAX2121

BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION

VCO divider setting.
D24 7 1 0 = Divide by 2. Use for LO frequencies
1125MHz.
1 = Divide by 4. Use for LO frequencies < 1125MHz.
Charge-pump current mode.
CPS 6 1 0 = Charge-pump current controlled by ICP bit.
1 = Charge-pump current controlled by VCO autoselect (VAS).
Charge-pump current.
ICP 5 0 0 = 600µA typical.
1 = 1200µA typical.
X 4–0 X Don’t care.

Table 9. VCO Register (Address: 0x07)

BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
Controls which VCO is activated when using manual VCO programming mode.
VCO[4:0] 7–3 11001
This also serves as the starting point for the VCO autoselection (VAS) mode.
VCO autoselection (VAS) circuit.
VAS 2 1 0 = Disable VCO selection must be programmed through I2C.
1 = Enable VCO selection controlled by autoselection circuit.
Enables or disables the VCO tuning voltage ADC latch when the VCO
autoselect mode (VAS) is disabled.
ADL 1 0
0 = Disables the ADC latch.
1 = Latches the ADC value.
Enables or disables VCO tuning voltage ADC read when the VCO
autoselect mode (VAS) is disabled.
ADE 0 0
0 = Disables ADC read.
1 = Enables ADC read.

Table 10. Lowpass Filter Register (Address: 0x08)

BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
Reserved 7–0 01001011 User must program to 10010111 (97h) upon powering up the device.

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 Complete Direct-Conversion L-Band Tuner
Table 11. Control Register (Address: 0x09)

MAX2121
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
Software standby control.
0 = Normal operation.
STBY 7 0 1 = Disables the signal path and frequency synthesizer leaving only the
2-wire bus, crystal oscillator, XTALOUT buffer, and XTALOUT buffer divider
active.
X 6 X Don’t care.
Factory use only.
PWDN 5 0
0 = Normal operation; other value is not tested.
X 4 X Don’t care.
Baseband gain setting (1dB typical per step).
0000 = Minimum gain (0dB, default).
BBG[3:0] 3–0 0000
…
1111 = Maximum gain (15dB typical).

Table 12. Shutdown Register (Address: 0x0A)

BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
X 7 X Don’t care.
PLL enable.
PLL 6 0 0 = Normal operation.
1 = Shuts down the PLL. Value not tested.
Divider enable.
DIV 5 0 0 = Normal operation.
1 = Shuts down the divider. Value not tested.
VCO enable.
VCO 4 0 0 = Normal operation.
1 = Shuts down the VCO. Value not tested.
Baseband enable.
BB 3 0 0 = Normal operation.
1 = Shuts down the baseband. Value not tested.
RF mixer enable.
RFMIX 2 0 0 = Normal operation.
1 = Shuts down the RF mixer. Value not tested.
RF VGA enable.
RFVGA 1 0 0 = Normal operation.
1 = Shuts down the RF VGA. Value not tested.
Front-end enable.
FE 0 0 0 = Normal operation.
1 = Shuts down the front-end. Value not tested.

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 Complete Direct-Conversion L-Band Tuner
Table 13. Test Register (Address: 0x0B)
MAX2121

BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION

Charge-pump test modes.
CPTST[2:0] 7–5 000
000 = Normal operation (default).
X 4 X Don’t care.
Charge-pump fast lock.
TURBO 3 1
Users must program to 1 after powering up the device.
REFOUT output.
LDMUX[2:0] 2–0 000
000 = Normal operation; other values are not tested.

Table 14. Status Byte-1 Register (Address: 0x0C)

BIT NAME BIT LOCATION (0 = LSB) FUNCTION
Power-on reset status.
0 = Chip status register has been read with a stop condition since last power-on.
POR 7
1 = Power-on reset (power cycle) has occurred. Default values have been loaded in
registers.
Indicates whether VCO autoselection was successful.
VASA 6 0 = Indicates the autoselect function is disabled or unsuccessful VCO selection.
1 = Indicates successful VCO autoselection.
Status indicator for the autoselect function.
VASE 5 0 = Indicates the autoselect function is active.
1 = Indicates the autoselect process is inactive.
PLL lock detector. TURBO bit must be programmed to 1 for valid LD reading.
LD 4 0 = Unlocked.
1 = Locked.
X 3–0 Don’t care.

Table 15. Status Byte-2 Register (Address: 0x0D)

BIT NAME BIT LOCATION (0 = LSB) FUNCTION
VCOSBR[4:0] 7–3 VCO band readback.
VAS ADC output readback.
000 = Out of lock.
001 = Locked.
ADC[2:0] 2–0 010 = VAS locked.
101 = VAS locked.
110 = Locked.
111 = Out of lock.

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 Complete Direct-Conversion L-Band Tuner
2-Wire Serial Interface Slave Address

MAX2121
The MAX2121 uses a 2-wire I2C-compatible serial inter- The MAX2121 has a 7-bit slave address that must be
face consisting of a serial-data line (SDA) and a serial- sent to the device following a START condition to initi-
clock line (SCL). SDA and SCL facilitate bidirectional ate communication. The slave address is internally pro-
communication between the MAX2121 and the master grammed to 1100000. The eighth bit (R/W) following
at clock frequencies up to 400kHz. The master initiates the 7-bit address determines whether a read or write
a data transfer on the bus and generates the SCL sig- operation occurs.
nal to permit data transfer. The MAX2121 behaves as a The MAX2121 continuously awaits a START condition
slave device that transfers and receives data to and followed by its slave address. When the device recog-
from the master. SDA and SCL must be pulled high nizes its slave address, it acknowledges by pulling the
with external pullup resistors (1kΩ or greater) for proper SDA line low for one clock period; it is ready to accept
bus operation. Pullup resistors should be referenced to or send data depending on the R/W bit (Figure 1).
the MAX2121’s VCC.
The write/read address is C0/C1 if ADDR pin is con-
One bit is transferred during each SCL clock cycle. A nected to ground. The write/read address is C2/C3 if
minimum of nine clock cycles is required to transfer a the ADDR pin is connected to VCC.
byte in or out of the MAX2121 (8 bits and an ACK/NACK).
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while SLAVE ADDRESS

SCL is high and stable are considered control signals S 1 1 0 0 0 0 0

(see the START and STOP Conditions section). Both SDA R/W ACK
and SCL remain high when the bus is not busy. SDA

START and STOP Conditions SCL

1 2 3 4 5 6 7 8 9
The master initiates a transmission with a START condi-
tion (S), which is a high-to-low transition on SDA while Figure 1. MAX2121 Slave Address Byte with ADDR Pin
SCL is high. The master terminates a transmission with Connected to Ground
a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high. Write Cycle
When addressed with a write command, the MAX2121
Acknowledge and Not-Acknowledge Conditions allows the master to write to a single register or to multi-
Data transfers are framed with an acknowledge bit ple successive registers.
(ACK) or a not-acknowledge bit (NACK). Both the mas-
A write cycle begins with the bus master issuing a
ter and the MAX2121 (slave) generate acknowledge
START condition followed by the seven slave address
bits. To generate an acknowledge, the receiving device
bits and a write bit (R/W = 0). The MAX2121 issues an
must pull SDA low before the rising edge of the
ACK if the slave address byte is successfully received.
acknowledge-related clock pulse (ninth pulse) and
The bus master must then send to the slave the address
keep it low during the high period of the clock pulse.
of the first register it wishes to write to (see Table 1 for
To generate a not-acknowledge condition, the receiver register addresses). If the slave acknowledges the
allows SDA to be pulled high before the rising edge of address, the master can then write one byte to the regis-
the acknowledge-related clock pulse, and leaves SDA ter at the specified address. Data is written beginning
high during the high period of the clock pulse. with the most significant bit. The MAX2121 again issues
Monitoring the acknowledge bits allows for detection of an ACK if the data is successfully written to the register.
unsuccessful data transfers. An unsuccessful data The master can continue to write data to the successive
transfer happens if a receiving device is busy or if a internal registers with the MAX2121 acknowledging each
system fault has occurred. In the event of an unsuc- successful transfer, or it can terminate transmission by
cessful data transfer, the bus master must reattempt issuing a STOP condition. The write cycle does not termi-
communication at a later time. nate until the master issues a STOP condition.

WRITE DEVICE WRITE REGISTER WRITE DATA TO WRITE DATA TO WRITE DATA TO
R/W ACK ACK ACK ACK ACK
START ADDRESS ADDRESS REGISTER 0x00 REGISTER 0x01 REGISTER 0x02 STOP
1100000 0 — 0x00 — 0x0E — 0xD8 — 0xE1 —

Figure 2. Example: Write Registers 0, 1, and 2 with 0x0E, 0xD8, and 0xE1, respectively.

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 Complete Direct-Conversion L-Band Tuner
MAX2121

ACK/
WRITE DEVICE ADDRESS R/W ACK READ FROM STATUS BYTE-1 REGISTER ACK READ FROM STATUS BYTE-2 REGISTER
START NACK STOP
1100000 1 — — — — —

Figure 3. Example: Receive Data from Read Registers

Read Cycle Table 16. Maximum Crystal ESR

When addressed with a read command, the MAX2121
allows the master to read back a single register, or mul-
Requirement
tiple successive registers. ESRMAX (
) XTAL FREQUENCY (MHz)
A read cycle begins with the bus master issuing a 80 12 < f XTAL  14
START condition followed by the seven slave address 60 14 < f XTAL  30
bits and a write bit (R/W = 0). The MAX2121 issues an
ACK if the slave address byte is successfully received. Baseband Lowpass Filter
The bus master must then send the address of the first The MAX2121 includes an on-chip 5th-order Butterworth
register it wishes to read (see Table 1 for register filter with 1st-order group delay compensation.
addresses). The slave acknowledges the address.
Then, a START condition is issued by the master, fol- DC Offset Cancellation
lowed by the seven slave address bits and a read bit The DC offset cancellation is required to maintain the
(R/W = 1). The MAX2121 issues an ACK if the slave I/Q output dynamic range. Connecting an external
address byte is successfully received. The MAX2121 capacitor between IDC+ and IDC- forms a highpass fil-
starts sending data MSB first with each SCL clock ter for the I channel and an external capacitor between
cycle. At the 9th clock cycle, the master can issue an QDC+ and QDC- forms a highpass filter for the Q chan-
ACK and continue to read successive registers, or the nel. Keep the value of the external capacitor less than
master can terminate the transmission by issuing a 47nF to form a typical highpass corner of 250Hz.
NACK. The read cycle does not terminate until the mas-
ter issues a STOP condition. XTAL Oscillator
The MAX2121 contains an internal reference oscillator,
Figure 3 illustrates an example in which registers 0, 1, reference output divider, and output buffer. All that is
and 2 are read back. required is to connect a crystal through a series 1nF
Application Information capacitor. To minimize parasitics, place the crystal and
series capacitor as close as possible to pin 14 (XTAL).
The MAX2121 downconverts RF signals in the 925MHz See Table 16 for crystal (XTAL) ESR (equivalent series
to 2175MHz range directly to the baseband I/Q signals. resistance) requirements.
RF Input Programming the Fractional
The RF input of the MAX2121 is internally matched to N- Synthesizer
75Ω. Only a DC-blocking capacitor is needed. See the The MAX2121 utilizes a fractional-N type synthesizer for
Typical Application Circuit. LO frequency programming. To program the frequency
synthesizer, the N and F values are encoded as
RF Gain Control straight binary numbers. Determination of these values
The MAX2121 features a variable-gain low-noise ampli- is illustrated by the following example:
fier providing 73dB of RF gain range. The voltage con-
trol (VGC) range is 0.5V (minimum attenuation) to 2.7V fLO is 2170MHz
(maximum attenuation). fXTAL is 27 MHz
Baseband Variable-Gain Amplifier Phase-detector comparison frequency is from 12MHz
and 30MHz
The receiver baseband variable-gain amplifiers provide
15dB of gain control range programmable in 1dB R divider = R[4:0] = 1
steps. The VGA gain can be serially programmed fCOMP = 27MHz/1 = 27MHz
through the I2C interface by setting bits BBG[3:0] in the D = fLO/fCOMP = 2170/27 = 80.37470
Control register.

16
 Complete Direct-Conversion L-Band Tuner
Integer portion: Table 17. ADC Trip Points and Lock Status

MAX2121
N = 80 ADC[2:0] LOCK STATUS
N[14:8] = 0 000 Out of lock
N[7:0] = 0101 0000 001 Locked
Fractional portion: 010 VAS locked
F = 0.370370 x 220 = 388,361 (round up the decimal portion) 101 VAS locked
F = 0101 1110 1101 0000 1001 110 Locked
Note: When changing LO frequencies, all the divider 111 Out of lock
registers (integer and fractional) must be programmed
to activate the VAS function regardless of whether indi- Table 17 summarizes the ADC output bits and the VCO
vidual registers are changed. lock indication. The VCO autoselect routine only selects
a VCO in the “VAS locked” range. This allows room for
VCO Autoselect (VAS) a VCO to drift over temperature and remain in a valid
The MAX2121 includes 24 VCOs. The local oscillator “locked” range.
frequency can be manually selected by programming
The ADC must first be enabled by setting the ADE bit in
the VCO[4:0] bits in the VCO register. The selected VCO
the VCO register. The ADC reading is latched by a sub-
is reported in the Status Byte-2 register (see Table 15).
sequent programming of the ADC latch bit (ADL = 1).
Alternatively, the MAX2121 can be set to autonomously The ADC value is reported in the Status Byte-2 register
choose a VCO by setting the VAS bit in the VCO regis- (see Table 15).
ter to logic-high. The VAS routine is initiated once the
F-Divider LSB register word (register 5) is loaded. Standby Mode
Thus it is important to write register 5 after any of the The MAX2121 features normal operating mode and
following PLL related bits have been changed: standby mode using the I2C interface. Setting a logic-
high to the STBY bit in the Control register puts the
N-Divider bits (registers 1 and/or 2) device into standby mode, during which only the 2-
F-Divider bits (registers 3 and/or 4) wire-compatible bus, the crystal oscillator, the XTAL
Reference Divider bits (register 6) buffer, and the XTAL buffer divider are active.
D24, CPS, or ICP bits (register 7) In all cases, register settings loaded prior to entering
shutdown are saved upon transition back to active
This will ensure all intended bits have been pro- mode. Default register values are provided for the
grammed before the VAS is initiated and the PLL is user’s convenience only. It is the user’s responsibility to
locked. The VCO value programmed in the VCO[4:0] load all the registers no sooner than 100µs after the
register serves as the starting point for the automatic device is powered up.
VCO selection process.
During the selection process, the VASE bit in the Status Layout Considerations
Byte-1 register is cleared to indicate the autoselection The MAX2121 EV kit serves as a guide for PCB layout.
function is active. Upon successful completion, bits VASE Keep RF signal lines as short as possible to minimize
and VASA are set and the VCO selected is reported in the losses and radiation. Use controlled impedance on all
Status Byte-2 register (see Table 15). If the search is high-frequency traces. For proper operation, the
unsuccessful, VASA is cleared and VASE is set. This indi- exposed paddle must be soldered evenly to the board’s
cates that searching has ended but no good VCO has ground plane. Use abundant vias beneath the exposed
been found, and occurs when trying to tune to a frequen- paddle for maximum heat dissipation. Use abundant
cy outside the VCO’s specified frequency range. ground vias between RF traces to minimize undesired
coupling. Bypass each VCC pin to ground with a 1nF
Refer to Application Note 4256: Extended Characterization capacitor placed as close as possible to the pin.
for the MAX2112/MAX2120 Satellite Tuners.
3-Bit ADC
The MAX2121 has an internal 3-bit ADC connected to
the VCO tune pin (TUNEVCO). This ADC can be used
for checking the lock status of the VCOs.

17
 Complete Direct-Conversion L-Band Tuner
Typical Application Circuit
MAX2121

SERIAL-DATA
INPUT/OUTPUT
SERIAL-CLOCK
INPUT VCC

VCC_BB
ADDR

QDC+
QDC-

IDC-
SDA
SCL
VCC
+ 28 27 26 25 24 23 22 IDC+
VCC_RF2
1 DC OFFSET 21
VCC
INTERFACE LOGIC CORRECTION
AND CONTROL IOUT-
VCC_RF1 MAX2121
2 20

IOUT+
GND
3 19
QOUT- BASEBAND
RF INPUT OUTPUTS
RFIN
4 18
VGC QOUT+
GC1
5 17
VCC VCC
DIV2 FREQUENCY
VCC_LO /DIV4 SYNTHESIZER VCC_DIG
VCC 6 16
EP
VCC_VCO REFOUT
7 15

8 9 10 11 12 13 14
BYPVCO

TUNEVCO

GNDTUNE

GNDSYN

CPOUT

VCC_SYN

XTAL

VCC

Chip Information Package Information

PROCESS: BiCMOS For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.

PACKAGE PACKAGE OUTLINE LAND

TYPE CODE NO. PATTERN NO.
28 TQFN-EP T2855+3 21-0140 90-0023

18
 Complete Direct-Conversion L-Band Tuner
Revision History

MAX2121
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 6/11 Initial release —
Corrected 2-tone frequencies, added new TOCs, added text to Register Description
1 7/12 section, corrected incorrect symbol in Table 8, corrected VCO Autoselect (VAS) 4, 6, 10, 17
section

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical. Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ____________________ 19
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