MAX2121
MAX2121
KIT
ATION
EVALU BL E
AVAILA
MAX2121
The MAX2121 low-cost, direct-conversion tuner IC is o 925MHz to 2175MHz Frequency Range
designed for satellite set-top and VSAT applications. o Monolithic VCO
The device directly converts the satellite signals from Low Phase Noise: -97dBc/Hz at 10kHz
the LNB to baseband using a broadband I/Q downcon- No Calibration Required
verter. The operating frequency range extends from o High Dynamic Range: -75dBm to 0dBm
925MHz to 2175MHz. o Integrated LP Filters: 123.75MHz
The device includes an LNA and an RF variable-gain o Single +3.3V ±5% Supply
amplifier, I and Q downconverting mixers, and base- o Low-Power Standby Mode
band lowpass filters and digitally controlled baseband
variable-gain amplifiers. Together, the RF and base- o Address Pin for Multituner Applications
band variable-gain amplifiers provide more than 80dB o Differential I/Q Interface
of gain control range. o I2C 2-Wire Serial Interface
The device includes fully monolithic VCOs, as well as a o Very Small, 5mm x 5mm, 28-Pin TQFN Package
complete fractional-N frequency synthesizer.
Additionally, an on-chip crystal oscillator is provided Ordering Information
along with a buffered output for driving additional tuners
and demodulators. Synthesizer programming and device PART TEMP RANGE PIN-PACKAGE
configuration are accomplished with a 2-wire serial inter- MAX2121ETI+ -40°C to +85°C 28 TQFN-EP*
face. The IC features a VCO autoselect (VAS) function
that automatically selects the proper VCO. For multituner *EP = Exposed pad.
applications, the device can be configured to have one +Denotes a lead(Pb)-free/RoHS-compliant package.
of two 2-wire interface addresses. A low-power standby
mode is available whereupon the signal path is shut Functional Diagram
down while leaving the reference oscillator, digital inter-
face, and buffer circuits active, providing a method to
VCC_BB
ADDR
QDC+
QDC-
IDC-
SCL
SDA
DBS tuner available. The low noise figure eliminates the VCC_RF2 1 DC OFFSET 21 IDC+
need for an external LNA. A small number of passive INTERFACE LOGIC CORRECTION
AND CONTROL MAX2121
components are needed to form a complete broadband VCC_RF1 2 20 IOUT-
satellite tuner DVB-S2 RF front-end solution. The tuner
is available in a very small, 5mm x 5mm, 28-pin thin
GND 3 19 IOUT+
QFN package.
VSATs
GC1 5 17 QOUT+
FREQUENCY
DIV2/DIV4 SYNTHESIZER
VCC_LO 6 16 VCC_DIG
EP
VCC_VCO 7 15 REFOUT
8 9 10 11 12 13 14
BYPVCO
TUNEVCO
GNDTUNE
GNDSYN
CPOUT
VCC_SYN
XTAL
For pricing, delivery, and ordering information, please contact Maxim Direct 1
at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Complete Direct-Conversion L-Band Tuner
ABSOLUTE MAXIMUM RATINGS
MAX2121
DC ELECTRICAL CHARACTERISTICS
(MAX2121 Evaluation Kit: VCC_ = +3.13V to +3.47V, fXTAL = 27MHz, TA = -40°C to +85°C, VGC1 = +0.5V (max gain), default register
settings except BBG[3:0] = 1011. No input signals at RF, baseband I/Os are open circuited. Typical values measured at VCC =
+3.3V, TA = +25°C, unless otherwise noted.) (Note 1)
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Complete Direct-Conversion L-Band Tuner
AC ELECTRICAL CHARACTERISTICS
MAX2121
(MAX2121 Evaluation Kit: VCC = +3.13V to +3.47V, TA = -40°C to +85°C, default register settings except BBG[3:0] = 1111. Typical
values measured at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Note 1)
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Complete Direct-Conversion L-Band Tuner
AC ELECTRICAL CHARACTERISTICS (continued)
MAX2121
(MAX2121 Evaluation Kit: VCC = +3.13V to +3.47V, TA = -40°C to +85°C, default register settings except BBG[3:0] = 1111. Typical
values measured at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Note 1)
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Complete Direct-Conversion L-Band Tuner
Typical Operating Characteristics
MAX2121
(MAX2121 Evaluation Kit: VCC = +3.3V, TA = +25°C, baseband output frequency = 5MHz, VGC1 = +1.2V, default register settings
except BBG[3:0] = 1011, unless otherwise noted.)
STANDBY SUPPLY CURRENT
SUPPLY CURRENT vs. SUPPLY VOLTAGE vs. SUPPLY VOLTAGE HD3 vs. VOUT
175 3.0 -10
MAX2121 toc02
MAX2121 toc01
MAX2121 toc03
BASEBAND 3RD-ORDER HARMONIC (dBc)
170 TA = +85°C -15
160 -25
155 TA = +85°C -30
TA = +25°C
150 2.0 -35
145 -40
140 TA = -40°C -45
TA = -40°C 1.5
135 -50
130 -55
125 1.0 -60
3.1 3.2 3.3 3.4 3.5 3.1 3.2 3.3 3.4 3.5 1.0 1.5 2.0 2.5 3.0
SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) VOUT (VP-P)
MAX2121 toc05
MAX2121 toc06
fBASEBAND = 50MHz fBASEBAND = 50MHz fLO = 1425MHz
QUADRATURE MAGNITUDE MATCHING (dB)
3.0 3.0
QUADRATURE PHASE ERROR (DEG)
0 0 0
900 1150 1400 1650 1900 2150 900 1150 1400 1650 1900 2150 0.1 1 10 100
LO FREQUENCY (MHz) LO FREQUENCY (MHz) BASEBAND FREQUENCY (MHz)
MAX2121 toc08
MAX2121 toc09
fLO = 1425MHz
QUADRATURE MAGNITUDE MATCHING (dB)
-5 0
-10
-1
BASEBAND OUTPUT LEVEL (dB)
0.8
-15
-2
-20
TA = +25°C -25 -3
0.6
-30 -4
-35 -5 TA = +25°C
0.4 -40 -6
-45
TA = +85°C -7
-50
0.2 -8
-55
TA = -40°C -60 -9
0 -65 -10
0.1 1 10 100 0 100 200 300 400 500 0 25 50 75 100 125 150
BASEBAND FREQUENCY (MHz) BASEBAND FREQUENCY (MHz) BASEBAND FREQUENCY (MHz)
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Complete Direct-Conversion L-Band Tuner
Typical Operating Characteristics (continued)
MAX2121
(MAX2121 Evaluation Kit: VCC = +3.3V, TA = +25°C, baseband output frequency = 5MHz, VGC1 = +1.2V, default register settings
except BBG[3:0] = 1011, unless otherwise noted.)
MAX2121 toc12
MAX2121 toc10
MAX2121 toc11
NORMALIZED AT TA = +25°C
-1
BASEBAND GAIN ERROR AT f-3dB (dB)
0.75 70
BASEBAND OUTPUT LEVEL (dB) -2 BBG[3:0] = 1111
0.50 60
-3
-0.25 -6 30
-7
-0.50 20
-8
-0.75 10
-9
-1.00 -10 0
-40 -20 0 20 40 60 80 100 1000 10,000 0 0.5 1.0 1.5 2.0 2.5 3.0
TEMPERATURE (°C) BASEBAND FREQUENCY (Hz) VGC1 (V)
MAX2121 toc14
MAX2121 toc15
ADJUST BBG[3:0] for 1VP-P SEE NOTE 5 ON PAGE 4 FOR CONDITIONS
10.5 BASEBAND OUTPUT WITH PIN = -75dBm
ADJUST BBG[3:0] FOR 1VP-P BASEBAND 30 AND VGC1 = -0.5V, fLO = 1500MHz 20
OUTPUT WITH PIN = -75dBm AND VGC1 = 0.5V
OUT-OF-BAND IIP3 (dBm)
10.0
NOISE FIGURE (dB)
25 10
9.5
8.5
15 -10
8.0
10 -20
7.5
7.0 5 -30
900 1150 1400 1650 1900 2150 -75 -65 -55 -45 -35 -75 -65 -55 -45 -35 -25 -15 -5
LO FREQUENCY (MHz) INPUT POWER (dBm) INPUT POWER (dBm)
IN-BAND IIP3 vs. INPUT POWER IIP2 vs. INPUT POWER INPUT RETURN LOSS vs. FREQUENCY
20 40 0
MAX2121 toc16
MAX2121 toc17
MAX2121 toc18
25
IN-BAND IIP3 (dBm)
-10
-20 15
-30 10 -15
5
-40
0 -20
-50 -5
VGC1 = 2.7V
-60 -10 -25
-75 -65 -55 -45 -35 -25 -15 -5 -75 -65 -55 -45 -35 -25 -15 -5 900 1125 1350 1575 1800 2025 2250
INPUT POWER (dBm) INPUT POWER (dBm) FREQUENCY (MHz)
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Complete Direct-Conversion L-Band Tuner
Typical Operating Characteristics (continued)
MAX2121
(MAX2121 Evaluation Kit: VCC = +3.3V, TA = +25°C, baseband output frequency = 5MHz, VGC1 = +1.2V, default register settings
except BBG[3:0] = 1011, unless otherwise noted.)
MAX2121 toc20
MAX2121 toc19
PHASE NOISE AT 10kHz OFFSET (dBc/Hz)
-100
-110
-100
-120
fLO = 1800MHz
-105 -130
925 1115 1305 1495 1685 1875 2065 2255 1.0E+03 1.0E+04 1.0E+05 1.0E+06
CHANNEL FREQUENCY (MHz) OFFSET FREQUENCY (Hz)
MAX2121 toc22
MEASURED AT RF INPUT
400
350 SUB-BAND 23
-75
LO LEAKAGE (dBm)
300
KV (MHz/V)
250
-80
200 SUB-BAND 12
150
-85
100
50 SUB-BAND 0
-90 0
925 1175 1425 1675 1925 2175 0 0.5 1.0 1.5 2.0 2.5 3.0
LO FREQUENCY (MHz) VTUNE (V)
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Complete Direct-Conversion L-Band Tuner
Pin Configuration
MAX2121
VCC_BB
ADDR
QDC+
QDC-
TOP VIEW
IDC-
SCL
SDA
28 27 26 25 24 23 22
VCC_RF2 1 21 IDC+
+
VCC_RF1 2 20 IOUT-
GND 3 19 IOUT+
MAX2121
RFIN 4 18 QOUT-
GC1 5 17 QOUT+
VCC_LO 6 16 VCC_DIG
EP
VCC_VCO 7 15 REFOUT
8 9 10 11 12 13 14
BYPVCO
TUNEVCO
GNDTUNE
GNDSYN
CPOUT
VCC_SYN
XTAL
TQFN
(5mm x 5mm)
Pin Description
PIN NAME FUNCTION
DC Power Supply for LNA. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor
1 VCC_RF2
connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections.
DC Power Supply for LNA. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor
2 VCC_RF1
connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections.
3 GND Ground. Connect to board’s ground plane for proper operation.
4 RFIN Wideband 75 RF Input. Connect to an RF source through a DC-blocking capacitor.
RF Gain-Control Input. High-impedance analog input with a 0.5V to 2.7V operating range.
5 GC1
VGC1 = 0.5V corresponds to the maximum gain setting.
DC Power Supply for LO Generation Circuits. Connect to a +3.3V low-noise supply. Bypass to GND
6 VCC_LO with a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias
with other ground connections.
DC Power Supply for VCO Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF
7 VCC_VCO capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other
ground connections.
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Complete Direct-Conversion L-Band Tuner
Pin Description (continued)
MAX2121
PIN NAME FUNCTION
Internal VCO Bias Bypass. Bypass to GND with a 100nF capacitor connected as close as possible to
8 BYPVCO
the pin. Do not share capacitor ground vias with other ground connections.
High-Impedance VCO Tune Input. Connect the PLL loop filter output directly to this pin with as short of
9 TUNEVCO
a connection as possible.
10 GNDTUNE Ground for TUNEVCO. Connect to the PCB ground plane.
11 GNDSYN Ground for Synthesizer. Connect to the PCB ground plane.
Charge-Pump Output. Connect this output to the PLL loop filter input with the shortest
12 CPOUT
connection possible.
DC Power Supply for Synthesizer Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with
13 VCC_SYN a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with
other ground connections.
Crystal-Oscillator Interface. Use with an external parallel-resonance-mode crystal through a series
14 XTAL
1nF capacitor. See the Typical Application Circuit.
15 REFOUT Crystal-Oscillator Buffer Output. A DC-blocking capacitor must be used when driving external circuitry.
DC Power Supply for Digital Logic Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with
16 VCC_DIG a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with
other ground connections.
17 QOUT+
Quadrature Baseband Differential Output. AC-couple with 47nF capacitors to the demodulator input.
18 QOUT-
19 IOUT+
In-Phase Baseband Differential Output. AC-couple with 47nF capacitors to the demodulator input.
20 IOUT-
21 IDC+
I-Channel Baseband DC Offset Correction. Connect a 47nF ceramic chip capacitor from IDC- to IDC+.
22 IDC-
23 QDC+
Q-Channel Baseband DC Offset Correction. Connect a 47nF ceramic chip capacitor from QDC- to QDC+.
24 QDC-
DC Power Supply for Baseband Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with
25 VCC_BB a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with
other ground connections.
26 SDA 2-Wire Serial-Data Interface. Requires 1k pullup resistor to VCC.
27 SCL 2-Wire Serial-Clock Interface. Requires 1k pullup resistor to VCC.
28 ADDR Address. Must be connected to either ground (logic 0) or supply (logic 1).
— EP Exposed Pad. Solder evenly to the board’s ground plane for proper operation.
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Complete Direct-Conversion L-Band Tuner
Detailed Description shows each bit name and the bit usage information for all
MAX2121
10
Complete Direct-Conversion L-Band Tuner
Table 2. N-Divider MSB Register (Address: 0x00)
MAX2121
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
FRAC 7 1 Users must program to 1 upon powering up the device.
Sets the most significant bits of the PLL integer-divide number (N). N can
N[14:8] 6–0 0000000
range from 19 to 251.
11
Complete Direct-Conversion L-Band Tuner
Table 8. PLL Register (Address: 0x06)
MAX2121
12
Complete Direct-Conversion L-Band Tuner
Table 11. Control Register (Address: 0x09)
MAX2121
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
Software standby control.
0 = Normal operation.
STBY 7 0 1 = Disables the signal path and frequency synthesizer leaving only the
2-wire bus, crystal oscillator, XTALOUT buffer, and XTALOUT buffer divider
active.
X 6 X Don’t care.
Factory use only.
PWDN 5 0
0 = Normal operation; other value is not tested.
X 4 X Don’t care.
Baseband gain setting (1dB typical per step).
0000 = Minimum gain (0dB, default).
BBG[3:0] 3–0 0000
…
1111 = Maximum gain (15dB typical).
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Complete Direct-Conversion L-Band Tuner
Table 13. Test Register (Address: 0x0B)
MAX2121
14
Complete Direct-Conversion L-Band Tuner
2-Wire Serial Interface Slave Address
MAX2121
The MAX2121 uses a 2-wire I2C-compatible serial inter- The MAX2121 has a 7-bit slave address that must be
face consisting of a serial-data line (SDA) and a serial- sent to the device following a START condition to initi-
clock line (SCL). SDA and SCL facilitate bidirectional ate communication. The slave address is internally pro-
communication between the MAX2121 and the master grammed to 1100000. The eighth bit (R/W) following
at clock frequencies up to 400kHz. The master initiates the 7-bit address determines whether a read or write
a data transfer on the bus and generates the SCL sig- operation occurs.
nal to permit data transfer. The MAX2121 behaves as a The MAX2121 continuously awaits a START condition
slave device that transfers and receives data to and followed by its slave address. When the device recog-
from the master. SDA and SCL must be pulled high nizes its slave address, it acknowledges by pulling the
with external pullup resistors (1kΩ or greater) for proper SDA line low for one clock period; it is ready to accept
bus operation. Pullup resistors should be referenced to or send data depending on the R/W bit (Figure 1).
the MAX2121’s VCC.
The write/read address is C0/C1 if ADDR pin is con-
One bit is transferred during each SCL clock cycle. A nected to ground. The write/read address is C2/C3 if
minimum of nine clock cycles is required to transfer a the ADDR pin is connected to VCC.
byte in or out of the MAX2121 (8 bits and an ACK/NACK).
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while SLAVE ADDRESS
WRITE DEVICE WRITE REGISTER WRITE DATA TO WRITE DATA TO WRITE DATA TO
R/W ACK ACK ACK ACK ACK
START ADDRESS ADDRESS REGISTER 0x00 REGISTER 0x01 REGISTER 0x02 STOP
1100000 0 — 0x00 — 0x0E — 0xD8 — 0xE1 —
Figure 2. Example: Write Registers 0, 1, and 2 with 0x0E, 0xD8, and 0xE1, respectively.
15
Complete Direct-Conversion L-Band Tuner
MAX2121
ACK/
WRITE DEVICE ADDRESS R/W ACK READ FROM STATUS BYTE-1 REGISTER ACK READ FROM STATUS BYTE-2 REGISTER
START NACK STOP
1100000 1 — — — — —
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Complete Direct-Conversion L-Band Tuner
Integer portion: Table 17. ADC Trip Points and Lock Status
MAX2121
N = 80 ADC[2:0] LOCK STATUS
N[14:8] = 0 000 Out of lock
N[7:0] = 0101 0000 001 Locked
Fractional portion: 010 VAS locked
F = 0.370370 x 220 = 388,361 (round up the decimal portion) 101 VAS locked
F = 0101 1110 1101 0000 1001 110 Locked
Note: When changing LO frequencies, all the divider 111 Out of lock
registers (integer and fractional) must be programmed
to activate the VAS function regardless of whether indi- Table 17 summarizes the ADC output bits and the VCO
vidual registers are changed. lock indication. The VCO autoselect routine only selects
a VCO in the “VAS locked” range. This allows room for
VCO Autoselect (VAS) a VCO to drift over temperature and remain in a valid
The MAX2121 includes 24 VCOs. The local oscillator “locked” range.
frequency can be manually selected by programming
The ADC must first be enabled by setting the ADE bit in
the VCO[4:0] bits in the VCO register. The selected VCO
the VCO register. The ADC reading is latched by a sub-
is reported in the Status Byte-2 register (see Table 15).
sequent programming of the ADC latch bit (ADL = 1).
Alternatively, the MAX2121 can be set to autonomously The ADC value is reported in the Status Byte-2 register
choose a VCO by setting the VAS bit in the VCO regis- (see Table 15).
ter to logic-high. The VAS routine is initiated once the
F-Divider LSB register word (register 5) is loaded. Standby Mode
Thus it is important to write register 5 after any of the The MAX2121 features normal operating mode and
following PLL related bits have been changed: standby mode using the I2C interface. Setting a logic-
high to the STBY bit in the Control register puts the
N-Divider bits (registers 1 and/or 2) device into standby mode, during which only the 2-
F-Divider bits (registers 3 and/or 4) wire-compatible bus, the crystal oscillator, the XTAL
Reference Divider bits (register 6) buffer, and the XTAL buffer divider are active.
D24, CPS, or ICP bits (register 7) In all cases, register settings loaded prior to entering
shutdown are saved upon transition back to active
This will ensure all intended bits have been pro- mode. Default register values are provided for the
grammed before the VAS is initiated and the PLL is user’s convenience only. It is the user’s responsibility to
locked. The VCO value programmed in the VCO[4:0] load all the registers no sooner than 100µs after the
register serves as the starting point for the automatic device is powered up.
VCO selection process.
During the selection process, the VASE bit in the Status Layout Considerations
Byte-1 register is cleared to indicate the autoselection The MAX2121 EV kit serves as a guide for PCB layout.
function is active. Upon successful completion, bits VASE Keep RF signal lines as short as possible to minimize
and VASA are set and the VCO selected is reported in the losses and radiation. Use controlled impedance on all
Status Byte-2 register (see Table 15). If the search is high-frequency traces. For proper operation, the
unsuccessful, VASA is cleared and VASE is set. This indi- exposed paddle must be soldered evenly to the board’s
cates that searching has ended but no good VCO has ground plane. Use abundant vias beneath the exposed
been found, and occurs when trying to tune to a frequen- paddle for maximum heat dissipation. Use abundant
cy outside the VCO’s specified frequency range. ground vias between RF traces to minimize undesired
coupling. Bypass each VCC pin to ground with a 1nF
Refer to Application Note 4256: Extended Characterization capacitor placed as close as possible to the pin.
for the MAX2112/MAX2120 Satellite Tuners.
3-Bit ADC
The MAX2121 has an internal 3-bit ADC connected to
the VCO tune pin (TUNEVCO). This ADC can be used
for checking the lock status of the VCOs.
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Complete Direct-Conversion L-Band Tuner
Typical Application Circuit
MAX2121
SERIAL-DATA
INPUT/OUTPUT
SERIAL-CLOCK
INPUT VCC
VCC_BB
ADDR
QDC+
QDC-
IDC-
SDA
SCL
VCC
+ 28 27 26 25 24 23 22 IDC+
VCC_RF2
1 DC OFFSET 21
VCC
INTERFACE LOGIC CORRECTION
AND CONTROL IOUT-
VCC_RF1 MAX2121
2 20
IOUT+
GND
3 19
QOUT- BASEBAND
RF INPUT OUTPUTS
RFIN
4 18
VGC QOUT+
GC1
5 17
VCC VCC
DIV2 FREQUENCY
VCC_LO /DIV4 SYNTHESIZER VCC_DIG
VCC 6 16
EP
VCC_VCO REFOUT
7 15
8 9 10 11 12 13 14
BYPVCO
TUNEVCO
GNDTUNE
GNDSYN
CPOUT
VCC_SYN
XTAL
VCC
18
Complete Direct-Conversion L-Band Tuner
Revision History
MAX2121
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 6/11 Initial release —
Corrected 2-tone frequencies, added new TOCs, added text to Register Description
1 7/12 section, corrected incorrect symbol in Table 8, corrected VCO Autoselect (VAS) 4, 6, 10, 17
section
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical. Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ____________________ 19
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